JPH07202519A - Micro wave circuit - Google Patents
Micro wave circuitInfo
- Publication number
- JPH07202519A JPH07202519A JP5334652A JP33465293A JPH07202519A JP H07202519 A JPH07202519 A JP H07202519A JP 5334652 A JP5334652 A JP 5334652A JP 33465293 A JP33465293 A JP 33465293A JP H07202519 A JPH07202519 A JP H07202519A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- dielectric substrate
- strip line
- micro wave
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000004020 conductor Substances 0.000 claims 4
- 239000010410 layer Substances 0.000 abstract description 9
- 239000002344 surface layer Substances 0.000 abstract 3
- 239000011229 interlayer Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 238000012544 monitoring process Methods 0.000 description 5
- 239000002356 single layer Substances 0.000 description 2
- 229910003336 CuNi Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0286—Programmable, customizable or modifiable circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Waveguides (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明はマイクロ波インピーダン
ス調整回路を有するマイクロ波回路に関する。特に、ト
リミング可能な多層ストリップラインの構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microwave circuit having a microwave impedance adjusting circuit. In particular, it relates to a trimmable multilayer stripline structure.
【0002】[0002]
【従来の技術】従来のマイクロ波回路のインピーダンス
調整は図4に示すように単層誘電体基板1の上に厚膜形
成技術を用いてU字形に形成されたストリップライン2
とこのラインの内側でラインを短絡するようにラインに
接続してあるラダー状のストリップラインを有してい
た。インピーダンス調整においては、関連特性をモニタ
ーしながら、レーザービームにより選択的にラダー状ス
トリップラインのU字形に近接した部位を図4のA−
B、A′−B′方向に熱的切断を行い回路の動作を変化
させている。(特開昭58−18768号公報)2. Description of the Related Art As shown in FIG. 4, impedance adjustment of a conventional microwave circuit is a stripline 2 formed in a U shape on a single-layer dielectric substrate 1 by using a thick film forming technique.
And had a ladder-like strip line connected to the line so as to short the line inside this line. In the impedance adjustment, while monitoring the relevant characteristics, a portion of the ladder-shaped stripline that is close to the U-shape is selectively irradiated by the laser beam.
The operation of the circuit is changed by thermally cutting in the B and A'-B 'directions. (Japanese Patent Laid-Open No. 58-18768)
【0003】[0003]
【発明が解決しようとする課題】このマイクロ波回路の
インピーダンス調整用回路構成では、ラダー状のストリ
ップラインが平面的に構成されている為に回路パターン
の面積が大きくなり、小型化が困難であった。In this impedance adjusting circuit configuration of the microwave circuit, since the ladder-shaped strip line is formed in a plane, the area of the circuit pattern becomes large, and it is difficult to reduce the size. It was
【0004】[0004]
【課題を解決するための手段】本発明のマイクロ波回路
は多層又は単層の誘電体基板の表面に形成されたストリ
ップラインとストリップライン上に設けられたスルーホ
ールとこのスルホールで接続される誘電体基板下層又は
層間のストリップラインを備えている。インピーダンス
調整は関連特性をモニターしながら、前記基板上面のス
トリップラインを選択的に切断する事によりインダクタ
ンスを増加させ、回路の動作を変化させる。A microwave circuit according to the present invention is a strip line formed on the surface of a multilayer or single-layer dielectric substrate, a through hole provided on the strip line, and a dielectric connected by this through hole. A strip line between the lower layer of the body substrate or the interlayer is provided. The impedance adjustment increases the inductance by selectively cutting the strip line on the upper surface of the substrate while monitoring the related characteristics, thereby changing the operation of the circuit.
【0005】[0005]
【実施例】次に本発明について図面を用いて説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.
【0006】図1は本発明の一実施例のマイクロ波回路
のインピーダンス調整用回路構成の部分見取り図であ
る。FIG. 1 is a partial sketch of a circuit configuration for impedance adjustment of a microwave circuit according to an embodiment of the present invention.
【0007】図1において例えば厚さ0.6mmのアル
ミナ4層からなる20×14mmの誘電体基板1の基板
上面にCu50μm膜によりストリップライン2が形成
され、このストリップライン2には下層の誘電体基板3
と接続される例えば200μmφのスルーホール4が形
成されており、下層の誘電体基板3にはスルーホール4
間を接続する誘電体基板1に作られているストリップラ
イン2と同じ幅を持つストリップライン2が形成されて
いる。In FIG. 1, a strip line 2 is formed of a Cu 50 μm film on the upper surface of a 20 × 14 mm dielectric substrate 1 made of, for example, 4 layers of alumina having a thickness of 0.6 mm. Board 3
A through hole 4 of, for example, 200 μmφ connected to the through hole 4 is formed in the lower dielectric substrate 3.
A strip line 2 having the same width as the strip line 2 formed on the dielectric substrate 1 for connecting the two is formed.
【0008】下層の誘電体基板3の下面は接地電板面7
とする為の例えばCuNi合金厚さ0.5mmの金属に
よる接地電極が形成されている。The lower surface of the lower dielectric substrate 3 is a ground electric plate surface 7.
For this purpose, a ground electrode made of, for example, a CuNi alloy having a thickness of 0.5 mm is formed.
【0009】インピーダンス調整に際しては、所望周波
数でのS11,S22等インピーダンス及び出力電力、利得
等の関連特性をモニターしながら、誘電体基板1の表面
に形成されたストリップライン2の上面だけで接続され
ている例えば1mm長のa−bをレーザービームにてA
−B方向に切断する事で、ストリップライン2のパスは
誘電体基板1の上下面を通るaa′b′bのようにな
り、ストリップライン2のラインが長くなり、これによ
り回路の動作を変化させる。(a′b′はどの層間又は
接地電極パターンを避けた基板下面でも可である。) 図2に本発明の第2の実施例の構成図を示す。When adjusting the impedance, only the upper surface of the strip line 2 formed on the surface of the dielectric substrate 1 is monitored while monitoring the impedance such as S 11 and S 22 at a desired frequency and related characteristics such as output power and gain. A, for example, ab with a length of 1 mm is connected with a laser beam A
By cutting in the -B direction, the path of the strip line 2 becomes like aa'b'b passing through the upper and lower surfaces of the dielectric substrate 1, and the line of the strip line 2 becomes longer, which changes the operation of the circuit. Let (A'b 'can be the underside of the substrate avoiding any interlayer or ground electrode pattern.) FIG. 2 shows a configuration diagram of the second embodiment of the present invention.
【0010】誘電体基板1,3は実施例1と同等であ
り、誘電体基板1の上面に形成されたストリップライン
2を図2の如く配置し、例えば幅0.5mmで長さ1m
mの枝状に伸ばしたストリップライン2の両端に下層の
誘電体基板3と接続する為のスルーホール4が形成さ
れ、下層の誘電体基板3の上面では、隣り合った枝状の
ストリップライン2の一方のスルーホール4と他端のス
ルーホール4′とを接続するストリップライン2が形成
されている。The dielectric substrates 1 and 3 are the same as those in the first embodiment, and the strip line 2 formed on the upper surface of the dielectric substrate 1 is arranged as shown in FIG. 2, and for example, the width is 0.5 mm and the length is 1 m.
Through-holes 4 for connecting to the lower dielectric substrate 3 are formed at both ends of the strip line 2 extending in a branch shape of m. A strip line 2 is formed to connect one through hole 4 to the other through hole 4 '.
【0011】インピーダンス調整の際には、上層基板の
上面の枝状のストリップライン2を接続しているストリ
ップライン2をインピーダンス及び関連特性をモニター
しながら、レーザービーム等により切断することでスト
リップラインの電気長を変化させ、回路の動作を変化さ
せる。When adjusting the impedance, the stripline 2 connected to the branch-shaped stripline 2 on the upper surface of the upper substrate is cut by a laser beam or the like while monitoring the impedance and related characteristics, so that the stripline It changes the electrical length and changes the operation of the circuit.
【0012】図3に本発明の第3の実施例を示す。多層
誘電体基板1は実施例1と同様であるが、層間にはスル
ーホール4と層間ストリップライン5を避けて、誘電体
基板1の下面の接地電板パターン6とスルーホール4″
により接続された層間接地電極7を有する基板上面スト
リップライン2と層間ストリップライン5は実施例1と
同様であり、インピーダンス調整は関連特性をモニター
しながら誘電体基板1の基板上面ストリップライン2を
選択的に切断し、回路の動作を変化させる。この実施例
3は実施例1に対して層間に接地電極パターン7を配置
する事により、回路的に安定となり、例えば、接地電極
パターン層7の有無によりカップリングが10dB以上
減少する。FIG. 3 shows a third embodiment of the present invention. The multilayer dielectric substrate 1 is the same as that of the first embodiment, except that the through holes 4 and the interlayer strip lines 5 are avoided between layers, and the ground electric plate pattern 6 and the through holes 4 ″ on the lower surface of the dielectric substrate 1 are provided.
The substrate upper surface stripline 2 and the interlayer stripline 5 having the interlayer ground electrode 7 connected by are similar to those of the first embodiment, and the impedance adjustment adjusts the substrate upper surface stripline 2 of the dielectric substrate 1 while monitoring the related characteristics. To change the operation of the circuit. Compared to the first embodiment, the third embodiment has a circuit-stable circuit by arranging the ground electrode pattern 7 between layers. For example, the presence or absence of the ground electrode pattern layer 7 reduces coupling by 10 dB or more.
【0013】[0013]
【発明の効果】以上説明したように本発明はラダー状の
ストリップラインを基板を多層化する事により縦方向に
構成したので、基板面積を縮少でき、基板を小型化でき
るという効果を有する。As described above, according to the present invention, since the ladder-shaped strip line is formed in the vertical direction by forming the substrate in multiple layers, the substrate area can be reduced and the substrate can be miniaturized.
【0014】基板縮少率は、回路基板の30%をラダー
状ストリップラインが占めている場合、基板状面で平面
的に広げているパターンを多層基板の層間又は下層へ移
動させる事により、ラダー部比率30%を80%縮少
し、基板面積で24%縮少する事が可能となる。従っ
て、基板縮少及び基板を包むケースについても18×1
2×4mmのケースを原形とした場合、20%の表面積
縮少から3%のコスト低減という効果を有する。When the ladder-like strip line occupies 30% of the circuit board, the reduction rate of the board is determined by moving the pattern, which is planarly spread on the board-like surface, to the interlayer or lower layer of the multilayer board. It is possible to reduce the part ratio of 30% by 80% and the substrate area by 24%. Therefore, the size of the board and the case that wraps the board are 18 × 1
When the case of 2 × 4 mm is used as the original shape, there is an effect of reducing the surface area by 20% and reducing the cost by 3%.
【図面の簡単な説明】[Brief description of drawings]
【図1】本発明の第1の実施例の構成図である。FIG. 1 is a configuration diagram of a first embodiment of the present invention.
【図2】本発明の第2の実施例の構成図である。FIG. 2 is a configuration diagram of a second embodiment of the present invention.
【図3】本発明の第3の実施例の構成図である。FIG. 3 is a configuration diagram of a third embodiment of the present invention.
【図4】従来例の構成図FIG. 4 is a block diagram of a conventional example
1…誘電体多層基板 2…基板上ストリップライン 3…下層誘電体基板 4…スルーホール 5…層間ストリップライン 6…基板下面接地電板 7…層間接地電極 4″…接地電極接続用スルーホール DESCRIPTION OF SYMBOLS 1 ... Dielectric multilayer board 2 ... Board stripline 3 ... Lower dielectric board 4 ... Through hole 5 ... Interlayer stripline 6 ... Substrate bottom surface grounding electric plate 7 ... Interlayer ground electrode 4 ″ ... Ground electrode connecting through hole
Claims (2)
面に形成された配線パターンと下層誘電体基板上に形成
されたストリップラインとを接続する複数のスルーホー
ル導体とで構成する複数の並列支路を有する導体と該導
体に接続される電子回路を備え前記最上層面に形成され
た配線パターンの一部を切断することにより回路の作動
を変化させることを特徴とするマイクロ波回路。1. A plurality of through hole conductors for connecting a wiring pattern formed on the uppermost layer surface of a dielectric substrate having a plurality of layer structures and a strip line formed on a lower layer dielectric substrate. A microwave circuit comprising a conductor having parallel branches and an electronic circuit connected to the conductor, wherein the operation of the circuit is changed by cutting a part of a wiring pattern formed on the uppermost layer surface.
層誘電体基板上に形成された複数の独立したストリップ
線路とを該ストリップ線路の先端からスルーホール導体
で接続することを特徴とした請求項1記載のマイクロ波
回路。2. The wiring pattern formed on the uppermost layer surface and a plurality of independent strip lines formed on the lower dielectric substrate are connected by a through-hole conductor from the tip of the strip line. 1. The microwave circuit according to 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5334652A JPH07202519A (en) | 1993-12-28 | 1993-12-28 | Micro wave circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5334652A JPH07202519A (en) | 1993-12-28 | 1993-12-28 | Micro wave circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH07202519A true JPH07202519A (en) | 1995-08-04 |
Family
ID=18279757
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5334652A Pending JPH07202519A (en) | 1993-12-28 | 1993-12-28 | Micro wave circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH07202519A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000059113A (en) * | 1998-08-04 | 2000-02-25 | Murata Mfg Co Ltd | Transmission line and transmission line resonator |
WO2011122502A1 (en) * | 2010-03-30 | 2011-10-06 | 日本電気株式会社 | Noise suppression structure |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0458601A (en) * | 1990-06-28 | 1992-02-25 | Taiyo Yuden Co Ltd | Circuit device having strip line |
JPH05175357A (en) * | 1991-12-25 | 1993-07-13 | Casio Comput Co Ltd | Stripline structure of multilayer substrate |
JPH05335835A (en) * | 1992-05-29 | 1993-12-17 | Kyocera Corp | Oscillation circuit |
-
1993
- 1993-12-28 JP JP5334652A patent/JPH07202519A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0458601A (en) * | 1990-06-28 | 1992-02-25 | Taiyo Yuden Co Ltd | Circuit device having strip line |
JPH05175357A (en) * | 1991-12-25 | 1993-07-13 | Casio Comput Co Ltd | Stripline structure of multilayer substrate |
JPH05335835A (en) * | 1992-05-29 | 1993-12-17 | Kyocera Corp | Oscillation circuit |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000059113A (en) * | 1998-08-04 | 2000-02-25 | Murata Mfg Co Ltd | Transmission line and transmission line resonator |
WO2011122502A1 (en) * | 2010-03-30 | 2011-10-06 | 日本電気株式会社 | Noise suppression structure |
US9225049B2 (en) | 2010-03-30 | 2015-12-29 | Nec Corporation | Noise suppression structure |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19970902 |