JPH07183108A - Manufacture of chip resistor - Google Patents
Manufacture of chip resistorInfo
- Publication number
- JPH07183108A JPH07183108A JP5326529A JP32652993A JPH07183108A JP H07183108 A JPH07183108 A JP H07183108A JP 5326529 A JP5326529 A JP 5326529A JP 32652993 A JP32652993 A JP 32652993A JP H07183108 A JPH07183108 A JP H07183108A
- Authority
- JP
- Japan
- Prior art keywords
- electrode layer
- ceramic substrate
- vertical
- resin
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000000919 ceramic Substances 0.000 claims abstract description 53
- 239000000758 substrate Substances 0.000 claims abstract description 44
- 229920005989 resin Polymers 0.000 claims abstract description 39
- 239000011347 resin Substances 0.000 claims abstract description 39
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 16
- 239000011521 glass Substances 0.000 claims description 19
- 239000010410 layer Substances 0.000 abstract description 111
- 239000011241 protective layer Substances 0.000 abstract description 10
- 238000000034 method Methods 0.000 abstract description 7
- 239000004519 grease Substances 0.000 abstract 1
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 8
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 6
- 229910052709 silver Inorganic materials 0.000 description 6
- 239000004332 silver Substances 0.000 description 6
- 238000010304 firing Methods 0.000 description 5
- 239000002923 metal particle Substances 0.000 description 4
- 229910052763 palladium Inorganic materials 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 238000009966 trimming Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Landscapes
- Details Of Resistors (AREA)
- Apparatuses And Processes For Manufacturing Resistors (AREA)
- Non-Adjustable Resistors (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、チップ抵抗器の製造方
法に関し、より詳しくは、セラミック基板の側面に樹脂
系の電極層を形成してなるチップ抵抗器の製造方法に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a chip resistor, and more particularly, to a method of manufacturing a chip resistor in which a resin-based electrode layer is formed on a side surface of a ceramic substrate.
【0002】[0002]
【従来の技術】従来のチップ抵抗器の一般的な構成を図
6に示す。セラミック基板1の表面の両端に表面電極層
2が形成され、この表面電極層2間に跨って抵抗体層3
が形成され、抵抗体層3は抵抗値調整によるトリミング
溝4が形成されており、保護層5で覆われている。一
方、上記セラミック基板1の裏面には、その両端に裏面
電極層6が形成されており、この裏面電極層6と上記表
面電極層2とを接続する側面電極層7が形成されてお
り、更にこれら電極層2,6,7はメッキ層8で覆われ
ている。2. Description of the Related Art A general structure of a conventional chip resistor is shown in FIG. Surface electrode layers 2 are formed on both ends of the surface of the ceramic substrate 1, and a resistor layer 3 is formed between the surface electrode layers 2.
Is formed, and the resistor layer 3 has a trimming groove 4 formed by adjusting the resistance value and is covered with a protective layer 5. On the other hand, a back surface electrode layer 6 is formed on both sides of the back surface of the ceramic substrate 1, and a side surface electrode layer 7 connecting the back surface electrode layer 6 and the front surface electrode layer 2 is formed. These electrode layers 2, 6 and 7 are covered with a plated layer 8.
【0003】従来、上記チップ抵抗器の製造は、未焼成
セラミックシートの表面に、複数の縦横溝を格子状とな
るようにして設けた後、焼成して、図7に示すような、
表面に縦横溝1a,1bを有するセラミック基板1を
得、このセラミック基板1表面の上記縦横溝1a,1b
で区画される単位領域A毎に、図8に示すように、表面
電極層2及び抵抗体層3を形成する一方、上記セラミッ
ク基板1の裏面に該セラミック基板1を挟んで上記表面
電極層2と対向する位置に裏面電極層6を形成し、上記
抵抗体層3をトリミングして抵抗値調整した後に、上記
抵抗体層3を覆う保護層5を形成し、次に、図4に示す
ように、上記縦溝1aに沿ってブレイクして上記セラミ
ック基板1を複数の棒状片1’とし、図5に示すよう
に、上記棒状片1’の長手方向両側面1’a,1’bに
側面電極層7を形成し、その後、上記棒状片1’を横溝
1bに沿ってブレイクすることによりチップ状とすると
いう方法により行われている。Conventionally, in the manufacture of the above chip resistor, a plurality of vertical and horizontal grooves are provided in a lattice pattern on the surface of an unfired ceramic sheet and then fired, as shown in FIG.
A ceramic substrate 1 having vertical and horizontal grooves 1a and 1b on its surface is obtained, and the vertical and horizontal grooves 1a and 1b on the surface of the ceramic substrate 1 are obtained.
As shown in FIG. 8, the surface electrode layer 2 and the resistor layer 3 are formed in each of the unit areas A divided by, and the surface electrode layer 2 is sandwiched on the back surface of the ceramic substrate 1 with the ceramic substrate 1 interposed therebetween. A back electrode layer 6 is formed at a position facing the resistance layer 3, the resistance layer 3 is trimmed to adjust the resistance value, and then a protection layer 5 covering the resistance layer 3 is formed. Next, as shown in FIG. Then, the ceramic substrate 1 is broken into a plurality of rod-shaped pieces 1'by breaking along the vertical grooves 1a, and as shown in FIG. 5, on both longitudinal side surfaces 1'a, 1'b of the rod-shaped pieces 1 '. The side electrode layer 7 is formed, and then the rod-shaped piece 1'is broken along the lateral groove 1b to obtain a chip shape.
【0004】一般に、上記棒状片1’の長手方向両側面
1’a,1’bに側面電極層7を形成する方法として
は、銀、パラジウム等の金属粒子をガラスペーストに混
入したメタルグレーズ系導電ペーストを印刷・焼成して
ガラス系の電極層を形成する方法が採られている。しか
し、上記保護層5及び側面電極層7は、抵抗体層3の抵
抗値調整後に形成されるために、これら保護層5及び側
面電極層7を高温焼成により設けると、上記抵抗体層3
中の金属成分の酸化状態等が変化して抵抗体層3の抵抗
値が調整値から僅かにずれるという問題がある。この問
題は、最近益々電子部品の高精度化が要求される中、チ
ップ抵抗器における解決課題の一つとなっている。そこ
で、上記現状に対応すべく、最近になって、上記側面電
極層7を、エポキシ樹脂等の熱硬化性樹脂に銀、パラジ
ウム等の金属粒子を混入させたメタルレジン系導電ペー
ストを印刷・硬化して樹脂系の電極層として、比較的低
温で形成することにより、抵抗値のズレを少しでも低減
することが行われるようになってきている。Generally, as a method of forming the side surface electrode layer 7 on both longitudinal side surfaces 1'a, 1'b of the rod-shaped piece 1 ', a metal glaze system in which metal particles such as silver and palladium are mixed in a glass paste. A method of printing and firing a conductive paste to form a glass-based electrode layer is adopted. However, since the protective layer 5 and the side surface electrode layer 7 are formed after the resistance value of the resistor layer 3 is adjusted, when the protective layer 5 and the side surface electrode layer 7 are provided by high temperature firing, the resistor layer 3 is formed.
There is a problem that the resistance value of the resistor layer 3 is slightly deviated from the adjusted value due to changes in the oxidation state of the metal components therein. This problem has become one of the problems to be solved in the chip resistor as the precision of electronic parts has been required more and more recently. Therefore, in order to cope with the present situation, recently, the side electrode layer 7 is printed and cured with a metal resin conductive paste in which a thermosetting resin such as an epoxy resin is mixed with metal particles such as silver and palladium. By forming the resin-based electrode layer at a relatively low temperature, the deviation of the resistance value can be reduced as much as possible.
【0005】[0005]
【発明が解決しようとする課題】しかしながら、上記の
ように樹脂系の側面電極層を用いるときは、該樹脂系の
側面電極層が上記ガラス系のものよりセラミック基板と
の密着性が悪く剥離し易いという問題がある。即ち、上
記従来の方法に従い、表面電極層2、抵抗体層3及び保
護層5が形成されたセラミック基板1を、その縦溝1a
に沿ってブレイクし、得られた棒状片1’の長手方向両
側面1’a,1’bに樹脂系の側面電極層7を形成する
場合、上記棒状片1’の長手方向両側面1’a,1’b
は、上記縦溝1aの側壁部と実際に分割される破断部と
からなり、上記側壁部は、未焼成セラミックシートの焼
成時、外気と接触しつつ焼成が進むために、その表面は
比較的粗面となり、一方、上記破断部は、ブレイクした
ときのセラミックの特性上、鏡面となっており、このよ
うな棒状片1’の長手方向両側面1’a,1’bに樹脂
系の側面電極層7を形成すると、鏡面となっている上記
破断部の部分で特に側面電極層7の密着力が低く、側面
電極層7が剥離するという問題があり、導通不良を招く
原因となっている。However, when the resin-based side electrode layer is used as described above, the resin-based side electrode layer has poorer adhesion to the ceramic substrate than the glass-based side electrode layer and peels off. There is a problem that it is easy. That is, according to the above-mentioned conventional method, the ceramic substrate 1 on which the surface electrode layer 2, the resistor layer 3 and the protective layer 5 are formed is provided with the vertical groove 1a.
When the resin-based side electrode layer 7 is formed on both side surfaces 1'a, 1'b in the longitudinal direction of the obtained rod-shaped piece 1 ', the side surface layers 1'in the longitudinal direction of the rod-shaped piece 1'are broken. a, 1'b
Is composed of a side wall portion of the vertical groove 1a and a fractured portion that is actually divided. The side wall portion has a relatively large surface because the firing proceeds while contacting with the outside air during firing of the unfired ceramic sheet. On the other hand, the fractured portion is a mirror surface due to the characteristics of the ceramic when it is broken, and the resinous side surfaces are formed on both side surfaces 1'a, 1'b in the longitudinal direction of the rod-shaped piece 1 '. When the electrode layer 7 is formed, there is a problem that the side surface electrode layer 7 has a low adhesive force particularly at the fractured portion, which is a mirror surface, and the side surface electrode layer 7 is peeled off, which causes poor conduction. .
【0006】本発明は、セラミック基板の両側面に樹脂
系の側面電極層を形成してなるチップ抵抗器において、
上記側面電極層の剥離による導通不良の発生を低減して
信頼性の高いチップ抵抗器を提供することを目的とす
る。The present invention provides a chip resistor having resin-based side electrode layers formed on both sides of a ceramic substrate,
An object of the present invention is to provide a highly reliable chip resistor by reducing the occurrence of conduction failure due to the peeling of the side surface electrode layer.
【0007】[0007]
【課題を解決するための手段】上記目的を達成するため
に、本発明は、セラミック基板の両側面に切り欠き部を
設け、上記セラミック基板の両側部のそれぞれをメタル
レジン系導電ペーストに浸漬して、樹脂系の側面電極層
を形成するようにした。即ち、本発明は、次の方法に係
るものである。 未焼成セラミックシートの表面に複数の縦溝及び横
溝を設けるとともに、上記縦溝上に沿って複数の貫通孔
を設け、この未焼成セラミックシートを焼成して、複数
のブレイク用の縦溝及び横溝、並びに複数の貫通孔を有
するセラミック基板を形成する工程と、上記各縦溝と横
溝とによって1個のチップ抵抗器に相当する単位領域に
区画されてあるセラミック基板の表面に、その縦方向に
並ぶ各単位領域毎に独立し、且つ縦溝の両端に跨り、し
かも上記貫通孔の少なくとも一部を覆うようにメタルグ
レーズ系導電ペーストを印刷してガラス系の表面電極層
を形成し、次いで横方向に隣合う上記表面電極間に跨っ
て抵抗体層を形成する工程と、上記縦溝に沿ってセラミ
ック基板をブレイクして棒状片とする工程と、上記棒状
片の長手方向に沿う両側面の各々に、メタルレジン系導
電ペーストを浸漬により塗着して樹脂系の側面電極層を
形成する工程と、上記棒状片を上記横溝に沿ってブレイ
クすることにより個々のチップ抵抗器とする工程と、を
具備することを特徴とするチップ抵抗器の製造方法。In order to achieve the above object, the present invention provides notches on both side surfaces of a ceramic substrate and dips each side portion of the ceramic substrate in a metal resin conductive paste. Then, the resin-based side electrode layer was formed. That is, the present invention relates to the following method. Along with providing a plurality of vertical grooves and lateral grooves on the surface of the unfired ceramic sheet, providing a plurality of through holes along the vertical groove, the unfired ceramic sheet is fired, a plurality of breaking vertical grooves and lateral grooves, And a step of forming a ceramic substrate having a plurality of through-holes, and the ceramic substrate is divided into unit regions corresponding to one chip resistor by the vertical grooves and the horizontal grooves, and is arranged in the vertical direction on the surface of the ceramic substrate. Independently for each unit area, straddling both ends of the vertical groove, and forming a glass-based surface electrode layer by printing a metal glaze-based conductive paste so as to cover at least a part of the through hole, and then in the lateral direction. A step of forming a resistor layer across the surface electrodes adjacent to each other, a step of breaking the ceramic substrate along the vertical groove into a rod-shaped piece, and a step of forming a rod-shaped piece along the longitudinal direction of the rod-shaped piece. A step of forming a resin side electrode layer by applying a metal resin conductive paste on each of the surfaces by dipping, and a step of breaking the rod-shaped pieces along the lateral grooves to form individual chip resistors. A method of manufacturing a chip resistor, comprising:
【0008】[0008]
【発明の作用及び効果】本発明においてセラミック基板
は、その表面に複数の縦溝及び横溝を有し、また、上記
縦溝上に沿う貫通孔を有していることとなる。このセラ
ミック基板の表面において、各縦溝と横溝とによって1
個のチップ抵抗器に相当する単位領域に区画され、その
縦方向に並ぶ各単位領域毎に独立し、且つ縦溝の両端に
跨り、しかも上記貫通孔の少なくとも一部を覆うように
メタルグレーズ系導電ペーストを印刷してガラス系の表
面電極層を形成すると、上記貫通孔の一部乃至全部に上
記ガラス系の表面電極層が形成されることとなる。According to the present invention, the ceramic substrate has a plurality of vertical grooves and horizontal grooves on its surface, and also has through holes extending along the vertical grooves. On the surface of this ceramic substrate, 1 is formed by each vertical groove and horizontal groove.
The metal glaze system is divided into unit regions corresponding to individual chip resistors, is independent for each unit region arranged in the vertical direction, extends over both ends of the vertical groove, and covers at least a part of the through hole. When the glass-based surface electrode layer is formed by printing the conductive paste, the glass-based surface electrode layer is formed in a part or all of the through hole.
【0009】上記のようにガラス系の表面電極層が形成
された上記セラミック基板を縦溝に沿ってブレイクする
から、得られるセラミックの棒状片の両側面における切
り欠き部の壁面の一部乃至全部には、ガラス系の表面電
極層が形成された状態となっている。従って、上記棒状
片の側面において露出するセラミック面の面積は、上記
切り欠き部に形成された表面電極層の分、減少される。
この棒状片の両側部をメタルレジン系導電ペーストに浸
漬して樹脂系の側面電極層を形成すると、樹脂系の側面
電極層は、上記切り欠き部において上記ガラス系の表面
電極層と密着することになり、樹脂系の側面電極層とガ
ラス系の表面電極層とが重なる面積が増加することとな
る。また、上記側面電極層は、上記切り欠き部における
窪みを略完全に充填するように形成される。Since the ceramic substrate on which the glass-based surface electrode layer is formed is broken along the vertical groove as described above, a part or all of the wall surface of the cutout portion on both sides of the obtained ceramic rod-shaped piece is broken. Has a glass-based surface electrode layer formed thereon. Therefore, the area of the ceramic surface exposed on the side surface of the rod-shaped piece is reduced by the amount of the surface electrode layer formed in the cutout portion.
When both sides of this rod-shaped piece are dipped in a metal resin conductive paste to form a resin-based side electrode layer, the resin-based side electrode layer should adhere to the glass-based surface electrode layer at the notch. Therefore, the area where the resin-based side surface electrode layer and the glass-based surface electrode layer overlap with each other increases. Further, the side surface electrode layer is formed so as to substantially completely fill the recess in the cutout portion.
【0010】ガラス系の表面電極層は、樹脂系の側面電
極層に比して、セラミック基板に対する密着性に優れ、
また、上記樹脂系の側面電極層は、セラミック基板に対
するよりもガラス系の表面電極層に対する密着性に優れ
る。よって、上記のように樹脂系の側面電極層は、ガラ
ス系の表面電極層との接触面積が増大する一方、セラミ
ック基板との接触面積が減少するので、上記樹脂系の側
面電極層の密着性を向上し得る。The glass-based surface electrode layer is superior in adhesiveness to the ceramic substrate as compared with the resin-based side electrode layer,
Further, the resin-based side surface electrode layer is more excellent in adhesion to the glass-based surface electrode layer than to the ceramic substrate. Therefore, as described above, the contact area of the resin-based side surface electrode layer with the glass-based surface electrode layer increases, while the contact area with the ceramic substrate decreases, so that the adhesion of the resin-based side surface electrode layer is improved. Can improve.
【0011】また、上記切り欠き部により樹脂系の側面
電極層の塗着面積が増大するとともに、切り欠き部にお
いて上記樹脂系の側面電極層の層厚を大きくし得、更に
上記切り欠き部に生じた窪み部によりアンカー効果が増
大されるので、樹脂系の側面電極層の密着性を向上し得
る。このように、本発明によれば、上記樹脂系の側面電
極層の密着性を向上し得るので、該側面電極層の剥離に
よる導通不良の問題を軽減でき、信頼性の高いチップ抵
抗器を提供することができるのである。Further, the notch portion increases the coating area of the resin-based side surface electrode layer, and the layer thickness of the resin-based side surface electrode layer can be increased at the notch portion. Since the anchor effect is increased by the resulting recessed portion, the adhesion of the resin-based side electrode layer can be improved. As described above, according to the present invention, the adhesiveness of the resin-based side electrode layer can be improved, so that the problem of conduction failure due to peeling of the side electrode layer can be reduced, and a highly reliable chip resistor is provided. You can do it.
【0012】[0012]
【実施例】以下、本発明の実施例を示すことにより、本
発明の特徴とするところをより詳細に説明するが、本発
明がこれに限定されることはない。本発明の方法により
得られるチップ抵抗器の一例の縦断面図及び水平断面図
を図1(a)及び(b)に示す。図1(a)及び(b)
中、符号11はセラミック基板を、符号11c’は切り
欠き部を、符号12は表面電極層を、符号13は裏面電
極層を、符号14は抵抗体層を、符号14aはトリミン
グ溝を、符号15は保護層を、符号16は側面電極層
を、符号17はメッキ層をそれぞれ示す。EXAMPLES The features of the present invention will be described below in more detail by showing Examples of the present invention, but the present invention is not limited thereto. A vertical sectional view and a horizontal sectional view of an example of a chip resistor obtained by the method of the present invention are shown in FIGS. 1 (a) and (b)
Among them, reference numeral 11 is a ceramic substrate, reference numeral 11c ′ is a notch, reference numeral 12 is a front electrode layer, reference numeral 13 is a back electrode layer, reference numeral 14 is a resistor layer, reference numeral 14a is a trimming groove, and reference numeral 14a is a trimming groove. Reference numeral 15 is a protective layer, reference numeral 16 is a side electrode layer, and reference numeral 17 is a plating layer.
【0013】先ず、未焼成セラミックシートの表面に、
該未焼成セラミックシートの厚みの半分程度の深さの複
数の縦溝及び横溝を格子状に設けるともに、上記縦溝上
に沿ってセラミックシートの厚さ方向に貫通する複数の
貫通孔を設け、これを焼成して、図2に示すように、ブ
レイク用の縦溝11a及び横溝11b、並びに貫通孔1
1cを有するセラミック基板11を得る。このとき、上
記貫通孔11cは、上記縦溝11a及び横溝11bによ
って区画され一個のチップ抵抗器に相当する単位領域B
における両端の縦溝11a上に少なくとも1つ以上設け
られる。また、貫通孔11cは、平面視円形に限られ
ず、例えば楕円状、四角形状、H字状等の適宜形状とし
てもかまわない。First, on the surface of the unfired ceramic sheet,
A plurality of vertical grooves and horizontal grooves having a depth of about half the thickness of the unsintered ceramic sheet are provided in a grid pattern, and a plurality of through holes penetrating in the thickness direction of the ceramic sheet are provided along the vertical grooves. As shown in FIG. 2, the vertical groove 11a and the horizontal groove 11b for breaking, and the through hole 1 are fired.
A ceramic substrate 11 having 1c is obtained. At this time, the through hole 11c is divided by the vertical groove 11a and the horizontal groove 11b, and is a unit area B corresponding to one chip resistor.
At least one or more are provided on the vertical grooves 11a at both ends of. The through hole 11c is not limited to a circular shape in plan view, and may have an appropriate shape such as an elliptical shape, a quadrangular shape, and an H shape.
【0014】次に、図3に示すように、上記縦溝11a
及び横溝11bによって上記単位領域Bに区画されてあ
るセラミック基板11の表面に、その縦方向に並ぶ各単
位領域B毎に独立し、且つ縦溝11aの両側に跨り、し
かも上記貫通孔11cの少なくとも一部を覆うように、
例えば銀、銀/パラジウム等の金属粒子をガラスペース
トに混入した、いわゆるメタルグレーズ系導電ペースト
を印刷・焼成してガラス系の表面電極層12を設ける。
更に、セラミック基板11の裏面において、該セラミッ
ク基板11を挟んで上記表面電極層12と対向する位置
に、例えばメタルグレーズ系導電ペーストを印刷・焼成
してガラス系の裏面電極層13を形成するとともに、横
方向に隣合う上記表面電極層12間に跨って抵抗体層1
4を設ける。そして、必要に応じてトリミングにより抵
抗値調整し、上記抵抗体層14を覆うようにガラス製又
は樹脂製の保護層15を形成する。Next, as shown in FIG. 3, the vertical groove 11a is formed.
On the surface of the ceramic substrate 11 divided into the unit regions B by the lateral grooves 11b, each of the unit regions B arranged in the vertical direction is independent, and extends over both sides of the vertical groove 11a, and at least the through hole 11c. To cover a part
For example, a so-called metal glaze-based conductive paste in which metal particles such as silver or silver / palladium are mixed in the glass paste is printed and fired to form the glass-based surface electrode layer 12.
Further, on the back surface of the ceramic substrate 11, a glass-based back electrode layer 13 is formed by printing and firing, for example, a metal glaze-based conductive paste at a position facing the front electrode layer 12 with the ceramic substrate 11 interposed therebetween. , The resistor layer 1 across the surface electrode layers 12 adjacent in the lateral direction.
4 is provided. Then, the resistance value is adjusted by trimming as necessary, and a protective layer 15 made of glass or resin is formed so as to cover the resistor layer 14.
【0015】次に、図4に示すように、上記のようにし
て各層12,13,14,15が形成されたセラミック
基板11を上記縦溝11aに沿ってブレイクして棒状片
11’を得る。次いで、図5に示すように、上記棒状片
11’の長手方向両側部11’a,11’b(ブレイク
面側)をそれぞれ、例えば銀粒子、銀/パラジウム粒子
等の金属粒子をエポキシ樹脂等の熱硬化性樹脂もしくは
紫外線硬化性樹脂に混入させたメタルレジン系導電ペー
ストに浸漬し、加熱もしくは紫外線照射して硬化させて
樹脂系の側面電極層16を設ける。上記棒状片11’の
長手方向両側部11’a,11’bをメタルレジン系導
電ペーストに浸漬する方法としては、特に限定されるこ
となく、例えば、特公平3−52201号公報に記載さ
れた、外周面に切り欠き溝を刻設した塗布ローラを用い
た装置及び方法により行うことができる。このとき、樹
脂系の側面電極層16は、セラミック基板11の表面、
側面及び裏面において、ガラス系の表面電極層12及び
裏面電極層13と密着するようになる。Next, as shown in FIG. 4, the ceramic substrate 11 on which the layers 12, 13, 14, and 15 are formed as described above is broken along the vertical grooves 11a to obtain rod-shaped pieces 11 '. . Next, as shown in FIG. 5, the longitudinal side portions 11'a and 11'b (break surface side) of the rod-shaped piece 11 'are respectively provided with, for example, silver particles, silver / palladium particles, or other metal particles, epoxy resin, or the like. The resin side electrode layer 16 is provided by immersing the resin in the metal resin conductive paste mixed with the thermosetting resin or the ultraviolet curable resin and heating or irradiating the resin to cure the resin. The method of immersing the longitudinal side portions 11'a, 11'b of the rod-shaped piece 11 'in the metal resin-based conductive paste is not particularly limited, and is described in, for example, Japanese Patent Publication No. 3-52201. It can be performed by an apparatus and method using a coating roller having a notched groove formed on the outer peripheral surface. At this time, the resin-based side surface electrode layer 16 is formed on the surface of the ceramic substrate 11,
The side surface and the back surface come into close contact with the glass-based front surface electrode layer 12 and the back surface electrode layer 13.
【0016】そして、上記棒状片11’を上記横溝11
bに沿ってブレイクしてチップ状とし、上記表面電極層
12、裏面電極層13及び側面電極層16を覆うよう
に、メッキ層17、例えばNiメッキ層及び半田メッキ
層を設けることによりチップ抵抗器とされる。Then, the rod-shaped piece 11 'is attached to the lateral groove 11'.
A chip resistor is formed by breaking along b to form a chip and providing a plating layer 17, for example, a Ni plating layer and a solder plating layer so as to cover the front surface electrode layer 12, the back surface electrode layer 13 and the side surface electrode layer 16. It is said that
【図1】本発明の実施例におけいて得られるチップ抵抗
器を示す(a)縦断面図及び(b)水平断面図である。FIG. 1A is a vertical sectional view and FIG. 1B is a horizontal sectional view showing a chip resistor obtained in an embodiment of the present invention.
【図2】本発明の実施例におけるセラミック基板を示す
部分上面図である。FIG. 2 is a partial top view showing a ceramic substrate according to an example of the present invention.
【図3】図1のセラミック基板上に表面電極層、裏面電
極層、抵抗体層及び保護層が設けられた状態を示す部分
上面図である。3 is a partial top view showing a state in which a front surface electrode layer, a back surface electrode layer, a resistor layer and a protective layer are provided on the ceramic substrate of FIG.
【図4】図2のセラミック基板を縦溝に沿ってブレイク
して棒状片とされる様子を説明する概略上面図である。FIG. 4 is a schematic top view illustrating a state in which the ceramic substrate of FIG. 2 is broken along a vertical groove to form a rod-shaped piece.
【図5】本発明の実施例における棒状片の長手方向に沿
う両側部に側面電極層を設けた状態を示す拡大上面図で
ある。FIG. 5 is an enlarged top view showing a state in which side electrode layers are provided on both side portions along the longitudinal direction of the rod-shaped piece in the example of the present invention.
【図6】従来の方法におけいて得られるチップ抵抗器を
示す縦断面図である。FIG. 6 is a vertical sectional view showing a chip resistor obtained by a conventional method.
【図7】従来の方法におけるセラミック基板を示す部分
上面図である。FIG. 7 is a partial top view showing a ceramic substrate in a conventional method.
【図8】図7のセラミック基板上に表面電極層、裏面電
極層、抵抗体層及び保護層が設けられた状態を示す部分
上面図である。8 is a partial top view showing a state in which a front surface electrode layer, a back surface electrode layer, a resistor layer and a protective layer are provided on the ceramic substrate of FIG.
11 セラミック基板 11a 縦溝 11b 横溝 11c 貫通孔 11c’ 切り欠き部 11’ 棒状片 11’a,11’b 棒状片の長手方向側面 12 表面電極層 13 裏面電極層 14 抵抗体層 15 保護層 16 側面電極層 B 単位領域 11 Ceramic Substrate 11a Vertical Groove 11b Horizontal Groove 11c Through Hole 11c 'Notch 11' Rod-like Piece 11'a, 11'b Longitudinal Side of Rod-like Piece 12 Front Electrode Layer 13 Back Electrode Layer 14 Resistor Layer 15 Protective Layer 16 Side Electrode layer B Unit area
Claims (1)
縦溝及び横溝を設けるとともに、上記縦溝上に沿って複
数の貫通孔を設け、この未焼成セラミックシートを焼成
して、複数のブレイク用の縦溝及び横溝、並びに複数の
貫通孔を有するセラミック基板を形成する工程と、 上記各縦溝と横溝とによって1個のチップ抵抗器に相当
する単位領域に区画されてあるセラミック基板の表面
に、その縦方向に並ぶ各単位領域毎に独立し、且つ縦溝
の両端に跨り、しかも上記貫通孔の少なくとも一部を覆
うようにメタルグレーズ系導電ペーストを印刷してガラ
ス系の表面電極層を形成し、次いで横方向に隣合う上記
表面電極間に跨って抵抗体層を形成する工程と、 上記縦溝に沿ってセラミック基板をブレイクして棒状片
とする工程と、 上記棒状片の長手方向に沿う両側部のそれぞれをメタル
レジン系導電ペーストに浸漬することにより樹脂系の側
面電極層を形成する工程と、 上記棒状片を上記横溝に沿ってブレイクすることにより
個々のチップ抵抗器とする工程と、を具備することを特
徴とするチップ抵抗器の製造方法。1. A plurality of vertical grooves and horizontal grooves are provided on the surface of an unfired ceramic sheet, and a plurality of through holes are provided along the vertical groove, and the unfired ceramic sheet is fired to obtain a plurality of breaks. A step of forming a ceramic substrate having vertical grooves, horizontal grooves, and a plurality of through holes; and a surface of the ceramic substrate partitioned by the vertical grooves and horizontal grooves into a unit area corresponding to one chip resistor, A glass-based surface electrode layer is formed by printing a metal glaze-based conductive paste so as to be independent for each unit region arranged in the vertical direction, straddle both ends of the vertical groove, and cover at least a part of the through hole. Then, a step of forming a resistor layer across the surface electrodes adjacent to each other in the lateral direction, a step of breaking the ceramic substrate along the vertical groove to form a rod-shaped piece, and a length of the rod-shaped piece A step of forming a resin-based side electrode layer by immersing each of both side portions along the hand direction in a metal resin-based conductive paste, and an individual chip resistor by breaking the rod-shaped piece along the lateral groove. A method of manufacturing a chip resistor, comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5326529A JPH07183108A (en) | 1993-12-24 | 1993-12-24 | Manufacture of chip resistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5326529A JPH07183108A (en) | 1993-12-24 | 1993-12-24 | Manufacture of chip resistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH07183108A true JPH07183108A (en) | 1995-07-21 |
Family
ID=18188857
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5326529A Pending JPH07183108A (en) | 1993-12-24 | 1993-12-24 | Manufacture of chip resistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH07183108A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1129144C (en) * | 1996-05-14 | 2003-11-26 | 阿尔卑斯电气株式会社 | Chip electronic device and its mfg. method |
WO2016158240A1 (en) * | 2015-03-31 | 2016-10-06 | Koa株式会社 | Chip resistor |
US10332660B2 (en) | 2016-11-23 | 2019-06-25 | Samsung Electro-Mechanics Co., Ltd. | Resistor element |
US11017923B1 (en) | 2019-12-12 | 2021-05-25 | Samsung Electro-Mechanics Co., Ltd. | Resistor component |
-
1993
- 1993-12-24 JP JP5326529A patent/JPH07183108A/en active Pending
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1129144C (en) * | 1996-05-14 | 2003-11-26 | 阿尔卑斯电气株式会社 | Chip electronic device and its mfg. method |
WO2016158240A1 (en) * | 2015-03-31 | 2016-10-06 | Koa株式会社 | Chip resistor |
JP2016192509A (en) * | 2015-03-31 | 2016-11-10 | Koa株式会社 | Chip resistor |
US10192658B2 (en) | 2015-03-31 | 2019-01-29 | Koa Corporation | Chip resistor |
US10332660B2 (en) | 2016-11-23 | 2019-06-25 | Samsung Electro-Mechanics Co., Ltd. | Resistor element |
US11017923B1 (en) | 2019-12-12 | 2021-05-25 | Samsung Electro-Mechanics Co., Ltd. | Resistor component |
KR20210074612A (en) | 2019-12-12 | 2021-06-22 | 삼성전기주식회사 | Resistor component |
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