JPH09120905A - Chip electronic part and method for manufacturing the same - Google Patents
Chip electronic part and method for manufacturing the sameInfo
- Publication number
- JPH09120905A JPH09120905A JP8124972A JP12497296A JPH09120905A JP H09120905 A JPH09120905 A JP H09120905A JP 8124972 A JP8124972 A JP 8124972A JP 12497296 A JP12497296 A JP 12497296A JP H09120905 A JPH09120905 A JP H09120905A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- substrate
- electrodes
- ceramic substrate
- slits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000000034 method Methods 0.000 title claims description 6
- 239000000758 substrate Substances 0.000 claims abstract description 83
- 239000000919 ceramic Substances 0.000 claims abstract description 48
- 239000011347 resin Substances 0.000 claims abstract description 28
- 229920005989 resin Polymers 0.000 claims abstract description 28
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052709 silver Inorganic materials 0.000 claims abstract description 11
- 239000004332 silver Substances 0.000 claims abstract description 11
- 238000007747 plating Methods 0.000 claims description 22
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 19
- 238000005476 soldering Methods 0.000 claims description 7
- 239000003973 paint Substances 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 abstract description 3
- 238000000576 coating method Methods 0.000 abstract description 3
- 230000002950 deficient Effects 0.000 abstract description 2
- 239000000463 material Substances 0.000 abstract 1
- 229910000679 solder Inorganic materials 0.000 description 12
- 239000011521 glass Substances 0.000 description 7
- 230000003628 erosive effect Effects 0.000 description 6
- 238000009966 trimming Methods 0.000 description 5
- 238000005452 bending Methods 0.000 description 4
- 230000005012 migration Effects 0.000 description 4
- 238000013508 migration Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 2
- 239000005011 phenolic resin Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- CTQNGGLPUBDAKN-UHFFFAOYSA-N O-Xylene Chemical compound CC1=CC=CC=C1C CTQNGGLPUBDAKN-UHFFFAOYSA-N 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 1
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 1
- 238000005488 sandblasting Methods 0.000 description 1
- 239000008096 xylene Substances 0.000 description 1
Landscapes
- Apparatuses And Processes For Manufacturing Resistors (AREA)
- Non-Adjustable Resistors (AREA)
- Details Of Resistors (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、チップ状の絶縁性
セラミック基板の表面に印刷素子が設けられ、この基板
の両端部に電極が形成されたチップ電子部品及びその製
造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip electronic component in which a printing element is provided on the surface of a chip-shaped insulating ceramic substrate and electrodes are formed at both ends of the substrate, and a method for manufacturing the same.
【0002】[0002]
【従来の技術】チップ電子部品の一種のチップ抵抗器の
基本構造は、絶縁性セラミック基板の表面の両端部に一
対の電極が形成され、これら一対の電極に接続されるよ
うに基板表面上に抵抗体が印刷形成された構造である。
半田付け性を向上させるために、この種のチップ電子部
品には、絶縁性セラミック基板の側面及び裏面に更に側
面電極及び裏面電極を設けた構造も提案されている。2. Description of the Related Art The basic structure of a chip resistor, which is a type of chip electronic component, is such that a pair of electrodes are formed on both ends of the surface of an insulating ceramic substrate, and the electrodes are formed on the substrate surface so as to be connected to the pair of electrodes. It is a structure in which a resistor is formed by printing.
In order to improve solderability, a structure in which a side surface electrode and a back surface electrode are further provided on the side surface and the back surface of the insulating ceramic substrate has been proposed for this type of chip electronic component.
【0003】[0003]
【発明が解決しようとする課題】絶縁性セラミック基板
は、大きなセラミック板を分割して形成されるため、側
面電極は絶縁性セラミック基板の分割面に形成されるこ
とになる。絶縁性セラミック基板の基板表面及び基板裏
面と分割面(側面電極を形成する端面)との間の角部の
角度は鋭角になるため、側面電極を導電ペーストを用い
て形成する場合に、導電ペーストが基板の角部で切れて
しまう問題が発生する。特に導電ペーストとして、ガラ
スを含むメタルグレーズ系の導電ペーストを用いた場合
には、この導電ペーストの切れが発生する率が高い。Since the insulating ceramic substrate is formed by dividing a large ceramic plate, the side electrodes are formed on the dividing surface of the insulating ceramic substrate. The angle between the front and back surfaces of the insulating ceramic substrate and the dividing surface (the end surface forming the side electrode) is an acute angle. Therefore, when the side electrode is formed by using the conductive paste, the conductive paste Occurs at the corners of the substrate. In particular, when a metal glaze-based conductive paste containing glass is used as the conductive paste, breakage of the conductive paste is high.
【0004】本発明の目的は、絶縁性セラミック基板の
分割面に形成される電極で導通不良が発生することのな
いチップ電子部品及びその製造方法を提供することにあ
る。SUMMARY OF THE INVENTION It is an object of the present invention to provide a chip electronic component that does not cause defective conduction in electrodes formed on the divided surface of an insulating ceramic substrate and a method of manufacturing the same.
【0005】[0005]
【課題を解決するための手段】本発明のチップ抵抗器で
は、厚み方向に対向するように基板両面に分割用のスリ
ット14が複数本形成されたセラミック板13がスリッ
トに沿って分割されて形成されて両端面に分割面を有す
る絶縁性セラミック基板2を用いる。絶縁性セラミック
基板2の基板表面の両端面側に位置する両端部には、メ
タルグレーズ系の一対の第1電極6を形成する。また絶
縁性セラミック基板2の基板裏面に一対の第1電極6と
対向する位置にメタルグレーズ系の一対の第2電極7を
形成する。そして基板表面に一対の第1電極と直接接続
された抵抗体を形成する。更に、第1電極及び第2電極
と幅広に一部重畳するように絶縁性セラミック基板2の
両端面に略コの字状のAg−レジン系の一対の第3電極
8を形成する。また第1電極及び第2電極の一部分と第
3電極を覆うようにメッキ層(9,10)を形成する。In the chip resistor of the present invention, a ceramic plate 13 having a plurality of dividing slits 14 formed on both surfaces of the substrate so as to face each other in the thickness direction is formed along the slits. The insulating ceramic substrate 2 having the divided surfaces on both end surfaces is used. A pair of first electrodes 6 of metal glaze type are formed on both ends of the insulating ceramic substrate 2 which are located on both end sides of the substrate surface. A pair of second electrodes 7 of metal glaze type are formed on the back surface of the insulating ceramic substrate 2 at positions facing the pair of first electrodes 6. Then, a resistor that is directly connected to the pair of first electrodes is formed on the surface of the substrate. Further, a pair of substantially U-shaped Ag-resin based third electrodes 8 are formed on both end surfaces of the insulating ceramic substrate 2 so as to partially overlap the first electrode and the second electrode in a wide range. Further, a plating layer (9, 10) is formed so as to cover a part of the first electrode and the second electrode and the third electrode.
【0006】本発明の方法によれば、まず厚み方向に対
向するように基板両面に分割用のスリット14が複数本
形成されたセラミック板13の基板表面に形成された複
数本のスリット14をそれぞれ挟んで基板表面にメタル
グレーズ系の第1電極6を印刷形成する。またセラミッ
ク板の基板裏面に形成された複数本のスリット14を挟
んで基板裏面にメタルグレーズ系の第2電極7を印刷形
成する。そして隣接する2本のスリット14の間に形成
した一対の第1電極に直接接続される抵抗体3を基板表
面上に印刷形成する。第1電極、第2電極及び抵抗体が
印刷形成されたセラミック板を両端部に第1電極及び第
2電極が位置するようにスリット14に沿ってスクライ
ブする。その後スクライブしたセラミック板の分割面を
含む両側端部に第1電極及び記第2電極と幅広に一部重
畳する状態でレジン含有銀塗料を略コの字状に直接塗布
した後に加熱処理して両側端部に第3電極8を形成し、
第1電極、第2電極及び第3電極の外面上にメッキ層
(9,10)を形成する。According to the method of the present invention, first, the plurality of slits 14 formed on the substrate surface of the ceramic plate 13 having the plurality of dividing slits 14 formed on the both surfaces of the substrate so as to face each other in the thickness direction, respectively. A metal glaze-based first electrode 6 is formed by printing on the surface of the substrate while sandwiching it. Further, the metal glaze-based second electrode 7 is formed by printing on the back surface of the substrate while sandwiching a plurality of slits 14 formed on the back surface of the substrate of the ceramic plate. Then, the resistor 3 which is directly connected to the pair of first electrodes formed between the two adjacent slits 14 is formed by printing on the surface of the substrate. The ceramic plate on which the first electrode, the second electrode and the resistor are printed is scribed along the slit 14 so that the first electrode and the second electrode are located at both ends. After that, the resin-containing silver coating is directly applied in a substantially U-shape in a state where it partially overlaps with the first electrode and the second electrode on both side portions including the divided surface of the scribed ceramic plate, and then heat treatment is performed. Form the third electrodes 8 on both side ends,
A plating layer (9, 10) is formed on the outer surfaces of the first electrode, the second electrode and the third electrode.
【0007】厚み方向に対向するように基板両面に分割
用のスリット14が複数本形成されたセラミック板13
をスリット14に沿って分割して形成された絶縁性セラ
ミック基板2の両端面に形成される分割面には、厚み方
向に対向する2本のスリット14を形成するための2つ
の傾斜面が残る。そのため基板表面及び基板裏面とこれ
らの2つの傾斜面との間の角度及び2つの傾斜面と残り
の分割面との間の角度は、いずれも鈍角になる。そのた
め絶縁性セラミック基板2の両端面に第3電極8を導電
ペーストにより形成する場合に、導電ペーストが切れ難
くなる。しかしながら、ガラスを含むメタルグレーズ系
の導電ペーストで第3電極を形成した場合には、導電ペ
ーストが基板の角部で切れる率は依然として高い。これ
は導電ペーストに含まれるガラスが影響しているものと
考えられる。そこで本発明では、第3電極8を形成する
ための導電ペースとしてレジン含有銀塗料を用いる。レ
ジン含有銀塗料は、ガラスを含有するメタルグレーズ系
の導電ペーストと比べて流動性が低く、基板に形成され
る角部が鈍角の場合には、ほとんど切れることはない。
そのため本発明によれば歩留まりが大幅に向上する。ま
た基板の端面に設けたAg−レジン系の第3電極8は、
適度の柔軟性を有するため、回路基板の曲げに対しても
十分に耐えることができ、剥離することがない。しかし
ながらAg−レジン系の第3電極を形成する際の硬化温
度は、メタルグレーズ系の第1電極6及び第2電極7を
形成する際の硬化温度と比べて大幅に低く、耐熱性が低
い。そのため半田食われが発生するおそれがある。また
Ag−レジン系の第3電極8からは、銀マイグレーショ
ンが発生するおそれがある。そこで本発明では、第1電
極、第2電極及び第3電極をメッキ層(9,10)で覆
っている。このメッキ層により、半田食われを防止して
銀マイグレーションの発生を防止することができる。A ceramic plate 13 having a plurality of dividing slits 14 formed on both sides of the substrate so as to face each other in the thickness direction.
Two inclined surfaces for forming two slits 14 facing each other in the thickness direction are left on the divided surfaces formed on both end surfaces of the insulating ceramic substrate 2 formed by dividing the slit 14 along the slit 14. . Therefore, the angle between the front surface and the back surface of the substrate and these two inclined surfaces and the angle between the two inclined surfaces and the remaining divided surfaces are both obtuse angles. Therefore, when the third electrodes 8 are formed on both end surfaces of the insulating ceramic substrate 2 with the conductive paste, the conductive paste is unlikely to break. However, when the third electrode is formed of a metal glaze-based conductive paste containing glass, the rate at which the conductive paste is cut at the corners of the substrate is still high. It is considered that this is due to the glass contained in the conductive paste. Therefore, in the present invention, a resin-containing silver paint is used as a conductive pace for forming the third electrode 8. The resin-containing silver paint has lower fluidity than a metal-glaze-based conductive paste containing glass, and almost never breaks when the corners formed on the substrate are obtuse.
Therefore, according to the present invention, the yield is significantly improved. The Ag-resin-based third electrode 8 provided on the end surface of the substrate is
Since it has appropriate flexibility, it can sufficiently withstand the bending of the circuit board and does not peel off. However, the curing temperature at the time of forming the Ag-resin type third electrode is significantly lower than the curing temperature at the time of forming the metal glaze type first electrode 6 and the second electrode 7, and the heat resistance is low. Therefore, solder erosion may occur. Further, silver migration may occur from the Ag-resin-based third electrode 8. Therefore, in the present invention, the first electrode, the second electrode, and the third electrode are covered with the plating layers (9, 10). This plated layer can prevent solder erosion and silver migration.
【0008】また基板の下面側では第3電極を第2電極
に一部重畳して設けてあるため、電極が段状に形成さ
れ、本発明のチップ抵抗器をプリント回路基板に取り付
けた際、電極の下面側と回路基板との間に生じた隙間に
ハンダが回り込み、本発明のチップ抵抗器が小さくても
充分な固着力が得られる。Since the third electrode is provided so as to partially overlap with the second electrode on the lower surface side of the substrate, the electrodes are formed in a step shape, and when the chip resistor of the present invention is attached to the printed circuit board, Solder wraps around the gap formed between the lower surface of the electrode and the circuit board, and a sufficient fixing force can be obtained even if the chip resistor of the present invention is small.
【0009】更に、第3電極を第1電極及び第2電極に
一部重畳させる程度は、半田付け時の熱により、第3電
極と第1電極及び第2電極との間に剥離が生じない程度
である。Ag−レジン系の一対の第3電極は、メタルグ
レーズ系の第1及び第2電極と熱膨脹係数が大きく相違
する。そのためメッキ層(9,10)で第3電極を覆っ
ていても、半田付け時にメッキ層を通して第1電極〜第
3電極に伝わる熱によって生じる第3電極と第1及び第
2電極との間の膨脹差が原因となって両者間に剥離が発
生する可能性がある。これを防ぐには第3電極と第1電
極及び第2電極との接触面積を、両者間に剥離が発生し
ない程度まで大きくしておく必要がある。本発明では、
この点を考慮して第3電極と第1電極及び第2電極との
間に剥離が生じない程度に第3電極を第1電極及び第2
電極に幅広に一部重畳させる。Further, to the extent that the third electrode is partially overlapped with the first electrode and the second electrode, heat generated during soldering does not cause peeling between the third electrode and the first electrode and the second electrode. It is a degree. The pair of third electrodes of Ag-resin system has a great difference in thermal expansion coefficient from the first and second electrodes of metal glaze system. Therefore, even if the third electrode is covered with the plating layer (9, 10), between the third electrode and the first and second electrodes generated by the heat transmitted to the first electrode to the third electrode through the plating layer during soldering. Peeling may occur between the two due to the difference in expansion. In order to prevent this, it is necessary to increase the contact area between the third electrode and the first and second electrodes to such an extent that peeling does not occur between them. In the present invention,
In consideration of this point, the third electrode is provided to the first electrode and the second electrode to the extent that peeling does not occur between the third electrode and the first electrode and the second electrode.
Widely overlap the electrode.
【0010】[0010]
【発明の実施の形態】以下本発明の一実施例を図面に基
づいて説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.
【0011】この実施例のチップ抵抗器1は、図1に示
すように、セラミックの基板2の表面に凸型の抵抗体3
が印刷され、この両端に電極4が設けられている。この
セラミックの基板2は、図3に示すように、厚み方向に
対向するように基板両面に分割用のスリット14が複数
本形成されたセラミック板13をスリットに沿って分割
するものである。したがって実際には、基板2の両端部
の角部は図示のように90度にはなっておらず、基板2
の両端部の角部にはスリット14を形成する傾斜面が残
る。したがって実際の基板2の両端部に形成される角部
は90度よりも大きい鈍角になる。また、スリット14
が入っていなかった部分の分割面とスリット14を形成
する傾斜面との間の角部も鈍角になっている。抵抗体3
は、酸化ルテニウム約10μの厚みに設け、レーザ又は
サンドブラストにより凸型の底辺から上方に向ってトリ
ミング溝5を形成し、抵抗値のトリミングが成されてい
る。As shown in FIG. 1, a chip resistor 1 of this embodiment has a ceramic substrate 2 and a convex resistor 3 on the surface thereof.
Is printed, and the electrodes 4 are provided on both ends thereof. As shown in FIG. 3, this ceramic substrate 2 divides along a slit a ceramic plate 13 having a plurality of dividing slits 14 formed on both sides of the substrate so as to face each other in the thickness direction. Therefore, in reality, the corners of both ends of the substrate 2 are not 90 degrees as shown in the drawing, and the substrate 2
Slopes forming the slits 14 remain at the corners of both ends of the. Therefore, the corners formed on both ends of the actual substrate 2 are obtuse angles larger than 90 degrees. In addition, the slit 14
The corners between the divided surface where the mark is not included and the inclined surface forming the slit 14 are also obtuse angles. Resistor 3
Is provided with a thickness of about 10 μm of ruthenium oxide, and a trimming groove 5 is formed upward from the bottom of the convex shape by laser or sandblasting to trim the resistance value.
【0012】このチップ抵抗器1の電極4は、抵抗体3
が直接に接続している第1電極6と、この第1電極6と
基板2をはさんで対向して形成された第2電極7を有
し、この第1,第2電極6,7はAg−Pd、Ag−P
t等のメタルグレーズペーストを印刷形成したものであ
る。さらに、第1,第2電極6,7をはさんで基板2の
端面に、キシレンフェノール樹脂又はエポキシフェノー
ル樹脂にAgを混入したAg−レジン系の導電ペースト
による第3電極8が設けられ、この第3電極8は、第
1,第2電極6,7を一部被覆するように設けられ、両
者の導通を図っている。図2に示すように、第3電極8
は、第1電極6及び第2電極7に幅広に一部重畳してい
る。その程度は、半田付け時の熱により、第3電極8と
第1電極6及び第2電極7との間に剥離が生じない程度
である。そして、この第1,第2,第3電極全体を覆っ
てNiメッキ9及びハンダメッキ10が施されている。The electrode 4 of the chip resistor 1 is connected to the resistor 3
Has a first electrode 6 directly connected thereto and a second electrode 7 formed so as to face the first electrode 6 and the substrate 2, and the first and second electrodes 6 and 7 are Ag-Pd, Ag-P
It is formed by printing a metal glaze paste such as t. Further, a third electrode 8 made of an Ag-resin-based conductive paste in which Ag is mixed with xylene phenol resin or epoxy phenol resin is provided on the end surface of the substrate 2 with the first and second electrodes 6 and 7 interposed therebetween. The third electrode 8 is provided so as to partially cover the first and second electrodes 6 and 7 so as to establish electrical continuity between them. As shown in FIG. 2, the third electrode 8
Partially overlaps the first electrode 6 and the second electrode 7 in a wide range. The degree is such that peeling does not occur between the third electrode 8 and the first electrode 6 and the second electrode 7 due to heat during soldering. Then, Ni plating 9 and solder plating 10 are applied to cover the entire first, second and third electrodes.
【0013】また、抵抗体3の表面には、ガラスコート
11及びレジンコート12を施して保護している。The surface of the resistor 3 is protected by a glass coat 11 and a resin coat 12.
【0014】この実施例のチップ抵抗器の製造方法は、
図3AないしFに示すように、先ず基板となるセラミッ
ク板13の基板表面側のスリット14をはさんで所定間
隔で第1電極6となるメタルグレーズペーストを複数列
印刷して、900℃近い温度で焼成する。メタルグレー
ズペーストを基板表面上に塗布するとその一部はスリッ
ト14の内部に流れ込む場合が殆どである。さらに同様
にして第2電極7も第1電極6と対向する基板裏面の位
置に形成する。次に、図3Bに示すように、第1電極6
の間のセラミック板13上にマトリクス状に抵抗体3を
印刷形成し、平均850℃の温度で焼成する。そして、
図3Cに示すように、抵抗体3の表面にガラスコート1
1を施し平均650℃の温度で焼成する。この後、セラ
ミック板13を各チップ抵抗器毎に縦横に設けられたス
リット14に沿って切断(スクライブ)し、図3Dに示
すように、基板2の端面にAg−レジン系の導電ペース
トの第3電極8を20μ程度の厚みに塗布し、200℃
程度の温度で硬化させる。そして、図3E,Fに示すよ
うに、Niメッキ9,ハンダメッキ10を各々順次施
し、第1,第2,第3電極6,7,8を被覆する。The manufacturing method of the chip resistor of this embodiment is as follows.
As shown in FIGS. 3A to 3F, first, a plurality of rows of metal glaze paste to be the first electrodes 6 are printed at predetermined intervals across the slits 14 on the substrate surface side of the ceramic plate 13 to be the substrate, and the temperature is set to about 900 ° C. Bake at. In most cases, when the metal glaze paste is applied on the surface of the substrate, a part thereof flows into the slit 14. Further, similarly, the second electrode 7 is also formed at a position on the back surface of the substrate facing the first electrode 6. Next, as shown in FIG. 3B, the first electrode 6
The resistors 3 are printed and formed in a matrix on the ceramic plate 13 between them and fired at a temperature of 850 ° C. on average. And
As shown in FIG. 3C, a glass coat 1 is formed on the surface of the resistor 3.
And firing at an average temperature of 650 ° C. After that, the ceramic plate 13 is cut (scribed) along the slits 14 provided in the vertical and horizontal directions for each chip resistor, and as shown in FIG. 3 electrode 8 is applied to a thickness of about 20μ, 200 ℃
Cure at moderate temperature. Then, as shown in FIGS. 3E and 3F, Ni plating 9 and solder plating 10 are sequentially applied to cover the first, second, and third electrodes 6, 7, and 8.
【0015】この場合、スリット14は基板の両側より
厚み方向に対向するように設けられているため、セラミ
ック基板端面に、樹脂を一部重畳する状態で塗布する
と、電気的にも機械的にも良好な状態が得られる。In this case, since the slits 14 are provided so as to face each other in the thickness direction from both sides of the substrate, when the resin is applied to the end face of the ceramic substrate in a state of partially overlapping, both electrically and mechanically. A good condition is obtained.
【0016】この方法によるとセラミック基板端面にお
いて、端子電極即ち第3電極8の剥がれやクラック等の
欠陥が生じなくなる。According to this method, defects such as peeling and cracks of the terminal electrode, that is, the third electrode 8 do not occur on the end surface of the ceramic substrate.
【0017】最後に、各チップ抵抗器の抵抗体3をトリ
ミングして抵抗値を調整し、エポキシ樹脂等のレジンコ
ート12を施し200℃付近の温度で硬化させる。Finally, the resistor 3 of each chip resistor is trimmed to adjust its resistance value, and a resin coat 12 of epoxy resin or the like is applied and cured at a temperature of about 200.degree.
【0018】また、トリミングは、図3Cの状態で行う
こともあり、この場合はその後レジンコート12を施し
て図3D以下の工程を行う。これによって、セラミック
板13をチップ毎に分離しない状態で抵抗値のトリミン
グを行うので効率良くトリミング作業を行うことがで
き、しかもレジンコート12によって、後のメッキ作業
時にも抵抗体に悪影響を与えることもない。Trimming may also be performed in the state of FIG. 3C. In this case, the resin coat 12 is then applied and the steps of FIG. 3D and thereafter are performed. As a result, since the resistance value is trimmed without separating the ceramic plate 13 into chips, the trimming work can be performed efficiently, and the resin coat 12 adversely affects the resistor during the subsequent plating work. Nor.
【0019】この実施例のチップ抵抗器によれば、半田
食われに対して電極4の耐性が向上し、しかも、回路基
板の曲げに対しても、メタルグレーズ系のみでできた電
極と比べ柔軟性が高いので電極が強い。また、半田付け
の際の回路基板に対する固着力も、第1,第2電極6,
7が回路基板に強固に半田付けされるので、極めて強
く、第3電極をAg−レジン系にしたことによる固着力
の低下は生じない。According to the chip resistor of this embodiment, the resistance of the electrode 4 to the solder erosion is improved, and moreover, it is more flexible against the bending of the circuit board as compared with the electrode made of only the metal glaze type. The electrode is strong because it has high properties. In addition, the fixing force to the circuit board during soldering also depends on the first and second electrodes 6, 6.
Since 7 is firmly soldered to the circuit board, it is extremely strong, and the adhesion strength does not decrease due to the third electrode being made of Ag-resin.
【0020】尚、この発明のチップ抵抗器の抵抗体は、
金属皮膜抵抗体、炭素皮膜抵抗体等その用途に合わせて
適宜選定し得るものである。またメタルグレーズペース
ト、Ag−レジン系導電ペーストの成分は、適宜他の添
加物が入っていても良い。本願のものは抵抗体上にガラ
スコートを施しトリミングしているが、適宜公知の方法
で変更しうるものであり、他の抵抗体を用いたチップ部
品にも同様に応用でき、この実施例のものに限定される
ものではない。The resistor of the chip resistor of the present invention is
A metal film resistor, a carbon film resistor or the like can be appropriately selected according to its application. In addition, the metal glaze paste and the Ag-resin-based conductive paste components may appropriately contain other additives. In the present application, a glass coat is applied on the resistor and trimming is performed, but it can be appropriately changed by a known method, and it can be similarly applied to a chip component using another resistor. It is not limited to one.
【0021】本実施例のチップ抵抗器は、基板の両面に
設けたメタルグレーズ系の第1,第2電極にまたがって
基板の端面にAg−レジン系の第3電極を設け、この第
1,第2,第3電極を覆うNiメッキ層及び該Niメッ
キ層を覆う半田メッキ層を形成したので、半田食われに
強く、回路基板への付け直しが可能である。また基板の
下面側の第2電極に一部重畳して第3電極を設けたの
で、基板の下面側の電極で段差が形成され、回路基板へ
半田付けした際、下面側電極と回路基板の間に生じる隙
間に半田が回り込んで強い固着力が得られる。しかも基
板の端面に設けたAg−レジン系の第3電極が適度の柔
軟性を有するので、回路基板の曲げに対しても十分に耐
え得るものである。また本実施例のように、スクライブ
後の基板側端部面にレジン含有銀塗料を表裏面の第1,
第2電極上に幅広に一部重畳する状態で直接塗布し低温
で加熱処理して第3電極を形成すると、切断されたまま
の粗い基板断面に対し直接に接合し第3電極の接着力が
強い。また半田付け用電極にメッキ処理する際、第3電
極がメッキ液の浸透を効果的に防止し、電極に剥れやク
ラック等の欠陥を生ずることのない高品質の製品を製造
し得る。またメッキ前にレジンコートをすればメッキ液
に弱い抵抗体をレジンコートにより保護するので、抵抗
体の特性も維持できる。In the chip resistor of the present embodiment, the Ag-resin type third electrode is provided on the end face of the substrate across the metal glaze type first and second electrodes provided on both sides of the substrate. Since the Ni plating layer that covers the second and third electrodes and the solder plating layer that covers the Ni plating layer are formed, they are resistant to solder erosion and can be reattached to the circuit board. Further, since the third electrode is provided so as to partially overlap the second electrode on the lower surface side of the board, a step is formed on the electrode on the lower surface side of the board, and when soldered to the circuit board, the lower surface electrode and the circuit board are separated. Solder wraps around the gap between them to obtain a strong fixing force. Moreover, since the Ag-resin-based third electrode provided on the end surface of the substrate has appropriate flexibility, it can sufficiently withstand bending of the circuit board. Further, as in this example, the resin-containing silver coating was applied to the end surface of the substrate side after scribing on the front and back surfaces.
When the third electrode is formed by directly applying it on the second electrode in a partially overlapped state and heat-treating it at a low temperature, the third electrode is directly bonded to the rough substrate section that has been cut, and the adhesive force of the third electrode is increased. strong. Further, when the soldering electrode is plated, the third electrode can effectively prevent the plating solution from penetrating, and it is possible to manufacture a high-quality product that does not cause defects such as peeling and cracks on the electrode. If the resin coat is applied before plating, the resistor which is weak against the plating solution is protected by the resin coat, so that the characteristics of the resistor can be maintained.
【0022】従って、今日の実装密度の高度化の要求に
よりチップ抵抗器も小型化しているが、電極が小さくて
も十分な固着力が得られ、電気製品の小型軽量化、信頼
性、耐久性及び生産性の向上に大きく寄与するものであ
る。Therefore, although the chip resistors have been miniaturized due to today's demand for higher packaging density, sufficient fixing force can be obtained even if the electrodes are small, and the electrical products can be made compact, lightweight, reliable and durable. It also contributes greatly to the improvement of productivity.
【0023】[0023]
【発明の効果】本発明のように、厚み方向に対向するよ
うに基板両面に分割用のスリットが複数本形成されたセ
ラミック基板をスリットに沿って分割して形成された絶
縁性セラミック基板を用いると、基板の両端部に形成さ
れる角部は鈍角になるため、絶縁性セラミック基板の両
端面に第3電極を導電ペーストにより形成する場合で
も、導電ペーストが切れ難くなる。その上、特に本発明
では、第3電極を形成するための導電ペーストとして流
動性の低いレジン含有銀塗料を用いるため、基板に形成
される角部が鈍角の場合に、導電ペーストがほとんど切
れることはない。そのため本発明によれば歩留まりが大
幅に向上する利点がある。また基板の端面に設けたAg
−レジン系の第3電極は、適度の柔軟性を有するため、
回路基板の曲げに対しても十分に耐えることができ、剥
離することがないという利点がある。更にAg−レジン
系の第3電極からは、銀マイグレーションが発生するお
それがある上、半田食われが発生するおそれもあるが、
本発明では第1電極,第2電極及び第3電極をメッキ層
で覆っているため、このメッキ層により、半田食われを
防止して銀マイグレーションの発生を防止することがで
きる利点がある。As in the present invention, an insulating ceramic substrate formed by dividing a ceramic substrate having a plurality of dividing slits formed on both sides of the substrate so as to face each other in the thickness direction along the slits is used. Since the corners formed on both ends of the substrate are obtuse, the conductive paste is difficult to cut even when the third electrodes are formed on the both ends of the insulating ceramic substrate with the conductive paste. Moreover, particularly in the present invention, since the resin-containing silver paint having low fluidity is used as the conductive paste for forming the third electrode, the conductive paste is almost cut when the corners formed on the substrate are obtuse angles. There is no. Therefore, according to the present invention, there is an advantage that the yield is significantly improved. In addition, Ag provided on the end surface of the substrate
-Since the resin-based third electrode has appropriate flexibility,
It has an advantage that it can sufficiently withstand bending of the circuit board and does not peel off. Furthermore, silver migration may occur from the Ag-resin-based third electrode, and solder erosion may occur.
In the present invention, since the first electrode, the second electrode and the third electrode are covered with the plating layer, the plating layer has an advantage that solder erosion can be prevented and silver migration can be prevented.
【0024】また第3電極を第1電極及び第2電極に幅
広に一部重畳させているので、半田付け時の熱により、
第3電極と第1電極及び第2電極との間に剥離が生じな
い利点がある。Further, since the third electrode is partially overlapped on the first electrode and the second electrode in a wide range, heat generated during soldering may cause the third electrode to overlap.
There is an advantage that peeling does not occur between the third electrode and the first and second electrodes.
【図1】本発明をチップ抵抗器に適用した一実施例の平
面図である。FIG. 1 is a plan view of an embodiment in which the present invention is applied to a chip resistor.
【図2】図1のA−A断面図である。FIG. 2 is a sectional view taken along line AA of FIG.
【図3】A,B,C,D,E,Fは本発明によりチップ
抵抗器を製造する場合の製造工程を示す横断面図であ
る。3A, 3B, 3C, 3D, 3E, 3F, 3E, 3F, 3E, 3F, 3E, 3F, 3E, 3F, 3E, 3F, 3E, 3F, 3E, 3F, 3E, 3F, 3E, 3F, 3F, 3F, 3F, 3F, 3D, 3F, 3D, and 3F are cross-sectional views showing a manufacturing process for manufacturing a chip resistor according to the present invention.
1 チップ抵抗器 2 絶縁性セラミック基板 3 抵抗体 4 電極 5 トリミング溝 6 第1電極 7 第2電極 8 第3電極 9 Niメッキ 10 半田メッキ 11 ガラスコート 12 レジンコート 13 セラミック板 14 スリット 1 Chip Resistor 2 Insulating Ceramic Substrate 3 Resistor 4 Electrode 5 Trimming Groove 6 First Electrode 7 Second Electrode 8 Third Electrode 9 Ni Plating 10 Solder Plating 11 Glass Coat 12 Resin Coat 13 Ceramic Plate 14 Slit
───────────────────────────────────────────────────── フロントページの続き (72)発明者 小原 陽三 富山県上新川郡大沢野町下大久保3158番地 北陸電気工業株式会社内 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yozo Ohara 3158 Shimookubo, Osawano-cho, Kamishinkawa-gun, Toyama Prefecture Hokuriku Electric Industry Co., Ltd.
Claims (3)
割用のスリット(14)が複数本形成されたセラミック
板(13)が前記スリットに沿って分割されて形成され
て両端面に分割面を有する絶縁性セラミック基板(2)
と、 前記絶縁性セラミック基板(2)の基板表面の前記両端
面側に位置する両端部に形成されたメタルグレーズ系の
一対の第1電極(6)と、 前記絶縁性セラミック基板(2)の基板裏面に前記一対
の第1電極(6)と対向する位置に形成されたメタルグ
レーズ系の一対の第2電極(7)と、 前記基板表面に形成されて前記一対の第1電極と直接接
続された印刷素子と、 前記第1電極及び前記第2電極と幅広に一部重畳するよ
うに前記絶縁性セラミック基板(2)の前記両端面に形
成された略コの字状のAg−レジン系の一対の第3電極
(8)と、 前記第1電極及び第2電極の一部分と前記第3電極を覆
うメッキ層(9,10)とを具備するチップ電子部品。1. A ceramic plate (13) having a plurality of dividing slits (14) formed on both surfaces of a substrate so as to face each other in the thickness direction, is divided along the slits, and is formed on both end faces. Insulating Ceramic Substrate (2)
A pair of metal glaze-type first electrodes (6) formed at both ends of the insulating ceramic substrate (2) located on both end sides of the substrate surface of the insulating ceramic substrate (2); A pair of metal glaze type second electrodes (7) formed on the back surface of the substrate at a position facing the pair of first electrodes (6), and directly connected to the pair of first electrodes formed on the front surface of the substrate Printed element, and a substantially U-shaped Ag-resin system formed on both end surfaces of the insulating ceramic substrate (2) so as to partially overlap the first electrode and the second electrode in a wide range. A chip electronic component comprising a pair of third electrodes (8), a part of the first and second electrodes, and a plating layer (9, 10) covering the third electrodes.
により、前記第3電極と前記第1電極及び第2電極との
間に剥離が生じないように前記第1電極及び前記第2電
極と一部重畳している請求項1に記載のチップ電子部
品。2. The third electrode (8) and the first electrode and the second electrode (8) are prevented from peeling between the third electrode and the first and second electrodes due to heat during soldering. The chip electronic component according to claim 1, which partially overlaps with the second electrode.
割用のスリット(14)が複数本形成されたセラミック
板(13)の基板表面に形成された複数本の前記スリッ
ト(14)をそれぞれ挟んで前記基板表面にメタルグレ
ーズ系の第1電極(6)を印刷形成する工程と、 前記セラミック基板の基板裏面に形成された複数本の前
記スリット(14)を挟んで前記基板裏面にメタルグレ
ーズ系の第2電極(7)を印刷形成する工程と、 隣接する2本の前記スリット(14)の間に形成した一
対の前記第1電極に直接接続される抵抗体(3)を前記
基板表面上に印刷形成する工程と、 前記第1電極、前記第2電極及び前記抵抗体が印刷形成
された前記セラミック基板を両端部に前記第1電極及び
前記第2電極が位置するように前記スリット(14)に
沿ってスクライブする工程と、 スクライブしたセラミック基板の分割面を含む両側端部
に前記第1電極及び前記第2電極と幅広に一部重畳する
状態でレジン含有銀塗料を略コの字状に直接塗布した後
に加熱処理して前記両側端部に第3電極(8)を形成す
る工程と、 前記第1電極、前記第2電極及び前記第3電極の外面上
にメッキ層(9,10)を形成する工程とからなるチッ
プ電子部品の製造方法。3. A plurality of said slits (14) formed on the substrate surface of a ceramic plate (13) having a plurality of dividing slits (14) formed on both sides of the substrate so as to face each other in the thickness direction. A step of printing and forming a metal glaze-based first electrode (6) on the front surface of the substrate while sandwiching the metal glaze on the back surface of the substrate by sandwiching the plurality of slits (14) formed on the back surface of the substrate of the ceramic substrate; A step of printing and forming a second electrode (7) of the system, and a resistor (3) directly connected to the pair of first electrodes formed between the two adjacent slits (14), the substrate surface And a step of forming the first electrode, the second electrode, and the resistor by printing so that the first electrode and the second electrode are located at both ends of the ceramic substrate. 14 ) Along with a step of scribing the resin-containing silver paint in a substantially U-shape in a state of partially overlapping the first electrode and the second electrode at both end portions including the divided surface of the scribed ceramic substrate. Forming a third electrode (8) on both side ends by directly applying it to the outer surface of the first electrode, the second electrode and the third electrode, and plating layers (9, 10) on the outer surfaces of the first electrode, the second electrode and the third electrode. The manufacturing method of the chip electronic component which consists of the process of forming.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12497296A JP3172673B2 (en) | 1996-05-20 | 1996-05-20 | Manufacturing method of chip resistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12497296A JP3172673B2 (en) | 1996-05-20 | 1996-05-20 | Manufacturing method of chip resistor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH09120905A true JPH09120905A (en) | 1997-05-06 |
JP3172673B2 JP3172673B2 (en) | 2001-06-04 |
Family
ID=14898782
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JP12497296A Expired - Lifetime JP3172673B2 (en) | 1996-05-20 | 1996-05-20 | Manufacturing method of chip resistor |
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JP (1) | JP3172673B2 (en) |
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JP6089013B2 (en) * | 2014-10-02 | 2017-03-01 | 株式会社ザップ | Panel hook |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57119501U (en) * | 1981-01-16 | 1982-07-24 | ||
JPS61268001A (en) * | 1984-12-28 | 1986-11-27 | コーア株式会社 | Chip-shaped electronic component |
-
1996
- 1996-05-20 JP JP12497296A patent/JP3172673B2/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57119501U (en) * | 1981-01-16 | 1982-07-24 | ||
JPS61268001A (en) * | 1984-12-28 | 1986-11-27 | コーア株式会社 | Chip-shaped electronic component |
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