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JPH07120702B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

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Publication number
JPH07120702B2
JPH07120702B2 JP61136556A JP13655686A JPH07120702B2 JP H07120702 B2 JPH07120702 B2 JP H07120702B2 JP 61136556 A JP61136556 A JP 61136556A JP 13655686 A JP13655686 A JP 13655686A JP H07120702 B2 JPH07120702 B2 JP H07120702B2
Authority
JP
Japan
Prior art keywords
layer
silicon
ions
ion
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61136556A
Other languages
Japanese (ja)
Other versions
JPS62293637A (en
Inventor
文二 水野
正文 久保田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP61136556A priority Critical patent/JPH07120702B2/en
Publication of JPS62293637A publication Critical patent/JPS62293637A/en
Publication of JPH07120702B2 publication Critical patent/JPH07120702B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】 産業上の利用分野 本発明はイオン注入により半導体装置の製造方法に関す
るものであり、特にシリコン層と組成比の正しい絶縁物
層が急峻な界面で接するSOI(Silicon on Insulator)
基板からなる半導体装置の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device by ion implantation, and particularly, an SOI (Silicon on Insulator) in which a silicon layer and an insulating layer having a correct composition ratio are in contact with each other at a sharp interface. )
The present invention relates to a method for manufacturing a semiconductor device including a substrate.

従来の技術 例えば、酸素イオンを注入してSOI構造を作り、この構
造に半導体素子を作り込むSIMOX技術(Separation bu I
Mplanted OX−ygev)の場合について第3図を用いて説
明する。第3図(a)の様にシリコン単結晶2の(10
0)面20aに、16O+21を80KeVの加速エネルギーで、1×1
018ious/cm2注入し、窒素雰囲気中1150℃でアニールを
行って絶縁物層21を形成した後、第3図(b)の様に1
μm程度のエピタキシャル層22を積み、この層22に第3
図(c)の様に所定の半導体素子23を形成している。24
は周辺絶縁物領域、25はゲート電極、26,27はソース,
ドレイン電極、28はゲート絶縁膜である。
Conventional technology For example, SIMOX technology (Separation bu I
The case of Mplanted OX-ygev) will be described with reference to FIG. As shown in FIG. 3 (a), the silicon single crystal 2 (10
0) 16 O + 21 on the surface 20a at an acceleration energy of 80 KeV and 1 × 1
After injecting 18 ious / cm 2 and annealing at 1150 ° C. in a nitrogen atmosphere to form the insulating layer 21, 1 as shown in FIG.
An epitaxial layer 22 of about μm is stacked, and a third layer is formed on this layer 22.
A predetermined semiconductor element 23 is formed as shown in FIG. twenty four
Is a peripheral insulator region, 25 is a gate electrode, 26 and 27 are sources,
The drain electrode 28 is a gate insulating film.

この様な方法で形成されたSOI構造基板は表面エピタキ
シャル層を除くと、第3図(d)の様に表面側から、基
板の一部からなるシリコン単結晶層20、照射損傷を受け
酸素を不純物として多量に含む層29、組成比の正しいSi
O2層21となる。
Except for the surface epitaxial layer, the SOI structure substrate formed by such a method, as shown in FIG. 3 (d), has a silicon single crystal layer 20 made of a part of the substrate, irradiation damage and oxygen from the surface side. Layer 29 containing a large amount of impurities, Si with the correct composition ratio
It becomes the O 2 layer 21.

発明が解決しようとする問題点 従来の方法ではイオン注入に際して生じる照射損傷の
為、表面シリコン層20とSiO2層21との間に第3図のごと
く広く損傷層29が残る。この層29がSi−SiO2界面の急峻
性を低下させ、又、表面シリコン層に半導体素子を形成
した場合リーク電流の経路となる。其の為に現状の装置
では第3図のごとく表面シリコン層上にエピタキシャル
層22を積み、この層22に素子を形成している。この場合
半導体素子の不純物拡散層たとえば26,27はSi−SiO2
面に達しておらず、SOI構造の寄生容量が小さいという
特徴が生かされず、又エピタキシャル層22を積む為、高
価にもなる。
Problems to be Solved by the Invention In the conventional method, a damage layer 29 is widely left between the surface silicon layer 20 and the SiO 2 layer 21 as shown in FIG. This layer 29 reduces the steepness of the Si-SiO 2 interface, also in the case of forming a semiconductor element on a surface silicon layer a path for leakage current. Therefore, in the current device, an epitaxial layer 22 is stacked on the surface silicon layer and an element is formed on this layer 22 as shown in FIG. Impurity diffusion layer for example 26 and 27 in this case semiconductor element has not reached the Si-SiO 2 interface, it is not alive, characterized in that the parasitic capacitance of the SOI structure is small, and since the gain epitaxial layer 22, also becomes expensive.

問題点を解決するための手段 本発明はSOI基板作製時に用いるイオンの飛程より深く
シリコンイオンもしくは希ガスイオンを注入して、照射
損傷層を形成し、同一基板にイオン注入により絶縁物層
を形成して、この絶縁物層上のシリコン基板の一部に半
導体素子を作り込む構造を得る方法である。
Means for Solving the Problems The present invention is to form a radiation damage layer by implanting silicon ions or rare gas ions deeper than the range of ions used in manufacturing an SOI substrate, and forming an insulator layer on the same substrate by ion implantation. It is a method of obtaining a structure in which a semiconductor element is formed on a part of the silicon substrate on the insulating layer.

作用 イオン注入によって生じた点欠陥はアニールによってSO
I構造の絶縁物層の両側に2次欠陥として残るが、別の
イオン注入による損傷層にSOI作製時の2次欠陥を捕獲
させる事により、表面シリコン層と絶縁物層間の損傷を
軽減し、急峻な界面を得る。
Action Point defects caused by ion implantation are annealed to SO
Although it remains as a secondary defect on both sides of the I structure insulator layer, the damage between the surface silicon layer and the insulator layer is reduced by trapping the secondary defect at the time of SOI production in the damage layer by another ion implantation, Get a steep interface.

実 施 例 以下に、シリコン基板(100)面にシリコンイオンと酸
素イオンを注入した本発明の一実施例について第1図を
用いて説明する。第1図(a)の様にシリコン基板1の
(100)表面1aにシリコンイオン2を加速エネルギー200
KeVで1×1016cm-2程度注入して照射損傷層3を形成し
ておく。層3上の基板1の一部は表面シリコン単結晶層
1Aとなる。次に、第1図(b)に示すごとくこれによっ
て生じる照射損傷層3より浅く飛程を設定して酸素イオ
ン4を加速エネルギー100〜120KeVで1×1018cm-2程度
注入して絶縁物層5を形成する。その後窒素もしくはア
ルゴン雰囲気中1000〜1200℃で1〜10時間程度アニール
して、酸素イオン注入に伴う欠陥をシリコンオイルによ
る損傷層3に捕獲させる。この方法で作製したSOI基板
は第1図(b)のように表面シリコン層1Aと絶縁物層5
との界面の損傷を含む欠陥6が少なく、皆面が急峻とな
る。
Example An example of the present invention in which silicon ions and oxygen ions are implanted into the surface of a silicon substrate (100) will be described below with reference to FIG. As shown in FIG. 1 (a), the silicon ion 2 is accelerated on the (100) surface 1a of the silicon substrate 1 with an acceleration energy of 200.
An irradiation damage layer 3 is formed in advance by injecting about 1 × 10 16 cm -2 with KeV. Part of the substrate 1 on the layer 3 is a surface silicon single crystal layer
It becomes 1A. Next, as shown in FIG. 1 (b), a range is set to be shallower than the irradiation damage layer 3 generated by this, and oxygen ions 4 are implanted at an acceleration energy of 100 to 120 KeV to about 1 × 10 18 cm -2 and an insulator is formed. Form layer 5. After that, annealing is performed at 1000 to 1200 ° C. for about 1 to 10 hours in a nitrogen or argon atmosphere, and defects caused by oxygen ion implantation are captured in the damaged layer 3 of silicon oil. The SOI substrate manufactured by this method has a surface silicon layer 1A and an insulator layer 5 as shown in FIG. 1 (b).
There are few defects 6 including damage at the interface with and, and all surfaces are steep.

シリコン基板面を(111)面にしても、イオンビームと
してのシリコンの代わりに希ガスイオンを用い、酸素の
代わりに酸素分子、窒素,窒素分子イオンを用いても同
様の結果が得られる事は言うまでもない。この様にして
SOI構造を作製した後、表面の結晶シリコン層1Aに所定
のMOSトランジスタ等の半導体素子23を形成しSOI構造の
集積回路構造を形成する。24は、素子23の周囲に形成さ
れたSiO2等の絶縁膜である。
Even if the silicon substrate surface is the (111) surface, similar results can be obtained by using rare gas ions instead of silicon as an ion beam and oxygen molecule, nitrogen, or nitrogen molecule ions instead of oxygen. Needless to say. In this way
After the SOI structure is manufactured, a semiconductor element 23 such as a predetermined MOS transistor is formed on the crystalline silicon layer 1A on the surface to form an integrated circuit structure having an SOI structure. Reference numeral 24 is an insulating film such as SiO 2 formed around the element 23.

以下に、シリコン基板(100)面に窒素イオンと酸素イ
オンを注入した本発明の他の実施例について第2図を用
いて説明する。先ず第2図(a)の様にシリコン基板1
の(100)表面1Aに窒素イオン11を200KeV程度で、ドー
ズ2×1017〜2×1018cm-2注入して窒化物層12を形成
し、窒素もしくはアルゴン雰囲気中1000−1200℃でアニ
ールする。次いで第2図(b)の様に酸素イオン4を14
0〜180KeVでドーズ1〜3×1018cm2注入して、窒素もし
くはアルゴン雰囲気中1000−1200℃でアニールして酸化
物層13を形成する。
Another embodiment of the present invention in which nitrogen ions and oxygen ions are implanted into the surface of the silicon substrate (100) will be described below with reference to FIG. First, as shown in FIG. 2 (a), the silicon substrate 1
Nitrogen ions 11 are implanted at a dose of 2 × 10 17 to 2 × 10 18 cm -2 on (100) surface 1A of about 200 KeV to form a nitride layer 12, which is annealed at 1000-1200 ° C. in a nitrogen or argon atmosphere. To do. Then, as shown in FIG.
A dose of 1 to 3 × 10 18 cm 2 is implanted at 0 to 180 KeV and annealed at 1000 to 1200 ° C. in a nitrogen or argon atmosphere to form an oxide layer 13.

以上のプロセスにより先ずSi3N4層12を作製する事によ
って、この層12がシリコン単結晶層中に大きなストレス
を誘起する。このストレス層12に酸素イオン注入に伴う
欠陥さらには不要注入不純物を捕獲させる。この方法で
作製したSOI基板は表面シリコン層と酸化膜層13との界
面の欠陥が少なく、界面が急峻となる。
By first producing the Si 3 N 4 layer 12 by the above process, this layer 12 induces a large stress in the silicon single crystal layer. The stress layer 12 is made to capture defects associated with oxygen ion implantation and further unwanted implantation impurities. The SOI substrate manufactured by this method has few defects at the interface between the surface silicon layer and the oxide film layer 13, and the interface becomes sharp.

シリコン基板面を(111)面にしても、イオンビームと
して、酸素イオンの代わりに酸素分子イオン、窒素イオ
ンの代わりに窒素分子イオンを用いても同様の結果が得
られる事は言うまでもない。この様にしてSOI構造を作
製した後、第1図(c)に示す結晶シリコン層に所定の
半導体素子23を形成する。
It is needless to say that the same result can be obtained even when the silicon substrate surface is the (111) plane and oxygen molecular ions are used instead of oxygen ions and nitrogen molecular ions are used instead of nitrogen ions as the ion beam. After the SOI structure is manufactured in this manner, a predetermined semiconductor element 23 is formed on the crystalline silicon layer shown in FIG. 1 (c).

発明の効果 以上の様に本発明によれば、絶縁物層を形成する為のイ
オン注入による照射損傷とさらには不要の注入不純物と
を、他のイオン注入による損傷層もしくは化合物膜によ
るストレス層を用いて捕獲させる事により、表面シリコ
ン層と絶縁物層との界面は急峻かつ低欠陥となる。従っ
て、表面シリコン層に半導体素子を作り込む場合、不純
物拡散層の深さを界面まで下げる事が可能と成り、SOI
本来の構成を採用する事が出来、高性能なSOI型の半導
体装置作成に寄与するものである。
EFFECTS OF THE INVENTION As described above, according to the present invention, irradiation damage due to ion implantation for forming an insulating layer, and unnecessary implanted impurities are prevented, and damage layer due to other ion implantation or stress layer due to compound film is eliminated. By using the traps, the interface between the surface silicon layer and the insulating layer becomes steep and has a low defect. Therefore, when a semiconductor element is built in the surface silicon layer, the depth of the impurity diffusion layer can be lowered to the interface.
The original configuration can be adopted, which contributes to the production of high-performance SOI semiconductor devices.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の一実施例に於けるシリコン(100)基
板面にシリコンイオンを注入し、次に酸素イオンを注入
して基板内部に絶縁物層を作製する方法を示す工程断面
図、第2図は本発明の他の実施例に於けるシリコン(10
0)基板面に窒素イオンを注入し窒化物層を作製し、次
いで、酸素イオンを注入して酸化物層を作製する方法を
示す工程断面図、第3図は従来例を説明するための工程
断面図である。 1……シリコン基板、1A……表面シリコン単結晶層、2
……シリコンイオンビーム、4……酸素イオンビーム、
3……照射損傷層、5,13……絶縁物層、11……窒素イオ
ンビーム、12……窒化物層。
FIG. 1 is a process cross-sectional view showing a method for producing an insulator layer inside a substrate by implanting silicon ions into a silicon (100) substrate surface and then implanting oxygen ions in one embodiment of the present invention, FIG. 2 shows a silicon (10) according to another embodiment of the present invention.
0) Process cross-sectional views showing a method of implanting nitrogen ions into the substrate surface to form a nitride layer, and then implanting oxygen ions to form an oxide layer, and FIG. 3 is a process for explaining a conventional example. FIG. 1 ... Silicon substrate, 1A ... Surface silicon single crystal layer, 2
...... Silicon ion beam, 4 ... Oxygen ion beam,
3 ... Irradiation damage layer, 5, 13 ... Insulator layer, 11 ... Nitrogen ion beam, 12 ... Nitride layer.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】シリコン単結晶基板中に複数回のイオン注
入を行って前記基板中に絶縁物層を形成し、前記絶縁物
層上のシリコン層に半導体素子を形成する半導体装置の
製造方法であって、シリコンイオンまたは希ガスイオン
を注入する第1の工程と、前記第1の工程の後に前記第
1の工程で注入されるイオンの飛程より浅く酸素原子を
含むイオンまたは窒素原子を含むイオンを注入する第2
の工程を有することを特徴とする半導体装置の製造方
法。
1. A method of manufacturing a semiconductor device, comprising: implanting ions into a silicon single crystal substrate a plurality of times to form an insulator layer in the substrate; and forming a semiconductor element in the silicon layer on the insulator layer. A first step of implanting silicon ions or rare gas ions, and an ion or oxygen atom containing oxygen atoms shallower than the range of the ions implanted in the first step after the first step. Second ion implantation
A method of manufacturing a semiconductor device, comprising:
【請求項2】シリコン単結晶基板中に複数回のイオン注
入を行って前記基板中に絶縁物層を形成し、前記絶縁物
層上のシリコン層に半導体素子を形成する半導体装置の
製造方法であって、酸素原子を含むイオンまたは窒素原
子を含むイオンを注入する第1の工程と、前記第1の工
程の後に前記第1の工程で注入されるイオンの飛程より
深くシリコンイオンまたは希ガスイオンを注入する第2
の工程を有することを特徴とする半導体装置の製造方
法。
2. A method of manufacturing a semiconductor device, comprising ion-implanting a silicon single crystal substrate a plurality of times to form an insulator layer in the substrate, and forming a semiconductor element in the silicon layer on the insulator layer. A first step of implanting an ion containing an oxygen atom or an ion containing a nitrogen atom, and a silicon ion or a rare gas deeper than the range of the ion implanted in the first step after the first step. Second ion implantation
A method of manufacturing a semiconductor device, comprising:
JP61136556A 1986-06-12 1986-06-12 Method for manufacturing semiconductor device Expired - Lifetime JPH07120702B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61136556A JPH07120702B2 (en) 1986-06-12 1986-06-12 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61136556A JPH07120702B2 (en) 1986-06-12 1986-06-12 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS62293637A JPS62293637A (en) 1987-12-21
JPH07120702B2 true JPH07120702B2 (en) 1995-12-20

Family

ID=15177985

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61136556A Expired - Lifetime JPH07120702B2 (en) 1986-06-12 1986-06-12 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH07120702B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH069227B2 (en) * 1987-03-05 1994-02-02 日本電気株式会社 Method for manufacturing semiconductor substrate
JPS6467937A (en) * 1987-09-08 1989-03-14 Mitsubishi Electric Corp Formation of high breakdown strength buried insulating film
JP2666757B2 (en) * 1995-01-09 1997-10-22 日本電気株式会社 Method for manufacturing SOI substrate

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59159563A (en) * 1983-03-02 1984-09-10 Toshiba Corp Manufacture of semiconductor device
JPS59208851A (en) * 1983-05-13 1984-11-27 Hitachi Ltd Semiconductor devices and their manufacturing methods

Also Published As

Publication number Publication date
JPS62293637A (en) 1987-12-21

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