JP2545904B2 - Semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a MIS semiconductor device melt-recrystallized on an insulating film by a laser, a lamp, or the like, and particularly to a channel leakage current thereof reduced and a built-in insulated gate electric field. The present invention relates to a semiconductor device in which the characteristics of an effect transistor are stabilized.
The semiconductor device of the present invention can be applied to a MOS integrated circuit device and the like.

[Prior Art] Conventionally, a polysilicon layer is formed on a silicon substrate via an intermediate insulating film such as a silicon dioxide film, and the polysilicon layer is melted and recrystallized by a laser or a lamp and recrystallized. A three-dimensional semiconductor device in which an insulated gate field effect transistor is formed using the above silicon layer has been proposed and is generally called an SOI semiconductor device. In this SOI semiconductor device, reducing the channel leak current of the N-type channel insulated gate field effect transistor has been a problem, and in order to improve this problem, the P-type silicon layer (hereinafter referred to as P-type silicon layer) is used. It has been proposed to ion implant boron.

That is, since the main component of the channel leak current is a so-called back channel current that mainly flows in a region of the P-type silicon layer adjacent to the intermediate insulating film (hereinafter referred to as a boundary region), boron ions are conventionally ionized in the boundary region. It was injected to prevent its reversal.

[Problems Requiring Solution] However, the conventional SOI semiconductor device described above has the following problems.

The first problem is that the threshold voltage of the N-channel insulated gate field effect transistor formed in the silicon layer on the intermediate insulating film varies. It was conventionally thought that this threshold voltage fluctuates due to displacement of sodium ions in various insulating films on the silicon layer, but not only that, but also due to displacement of sodium ions in the intermediate insulating film below the silicon layer. It turned out to be affected. That is, when the sodium ions in the intermediate insulating film are displaced, the potential of the silicon layer on the intermediate insulating film is changed, and the back bias effect changes the threshold voltage of the insulated gate field effect transistor. This problem also occurs in the SOI semiconductor device having the N-type silicon layer on the intermediate insulating film.

The second problem is that when boron is ion-implanted into the P-type silicon layer on the intermediate insulating film to prevent the inversion of the conductivity type in the boundary region, the boron is redistributed by the annealing after the ion implantation, and the insulation gate Vg-Id of field effect transistor
It is difficult to control the characteristics and the drain breakdown voltage.

In particular, since the silicon layer is generally thinned with higher integration, the problem of boron redistribution and the problem of fluctuation of the threshold voltage have recently become more important.

The present invention has been made in view of the above problems, and provides an SOI semiconductor device in which channel leakage current of a built-in insulated gate field effect transistor is reduced and electric characteristics of the insulated gate field effect transistor are stabilized. With the goal.

[Means for Solving the Problems] A semiconductor device of the present invention includes: a silicon substrate; an intermediate insulating film formed on the silicon substrate and ion-implanted with boron and phosphorus or arsenic; and an intermediate insulating film on the intermediate insulating film. The formed and melt-recrystallized P-type silicon layer, the P-type auto-doped region formed in the P-type silicon layer by auto-doping of the boron from the intermediate insulating film to the P-type silicon layer, and the P-type silicon layer. -Type gate insulating film formed on the surface of a silicon layer, a gate electrode formed on the gate insulating film, and an N-type which is formed on the surface of the P-type silicon layer and whose conduction is controlled by the gate electrode A source region and an N-type drain region.

The P-type silicon layer is preferably a single crystal layer, but may be a polycrystalline layer.

[Operation] In the semiconductor device of the present invention, phosphorus or arsenic implanted into the intermediate insulating film below the P-type silicon layer passivates alkali ions such as sodium ions in the intermediate insulating film, and The potential change of the P-type silicon layer due to the movement is prevented, and the change of the threshold voltage of the N-type channel insulated gate field effect transistor formed on the surface of the P-type silicon layer is prevented.

Boron implanted into the intermediate insulating film below the P-type silicon layer is auto-doped into the P-type silicon layer by the subsequent heat treatment, and a P-type auto-doped region is formed in the boundary region of the P-type silicon layer. The P-type auto-doped region prevents the back channel current in the boundary region.

[Embodiment] A MOS integrated circuit device which is an embodiment of the semiconductor device of the present invention will be described below with reference to the drawings.

FIG. 1 is a partial cross-sectional view of the MOS integrated circuit device of this embodiment, and FIGS. 2 to 4 are cross-sectional views showing the manufacturing process of the MOS integrated circuit device.

The MOS integrated circuit device of the present invention comprises a silicon substrate 1, a separation silicon dioxide film 2 as an intermediate insulating film formed on the silicon substrate 1 by the LOCOS method, and a laser re-formation film formed on the separation silicon dioxide film 2. A P-type silicon layer 5 single-crystallized by the crystallization method, a P-type auto-doped region 6 formed by auto-doping of boron from the separating silicon dioxide film 2 to the P-type silicon layer 5, and a P-type silicon layer. 5, a gate insulating film 7 formed on the surface of the gate electrode 5, a gate electrode 8 formed on the gate insulating film 5, and an N-type source region formed on the P-type silicon layer 5 and controlled in mutual conduction by the gate electrode 8. 9A and N-type drain region 9B.

The silicon substrate 1 is an N-type substrate of about 10 ¹⁵ atoms / cm ³ .

The isolation silicon dioxide film 2 is LO on the silicon substrate 1.
0.1-2 μm (preferably about 1.2) formed by the COS method
(μm) thick insulating film for insulation separation, and boron and phosphorus are ion-implanted by ion implantation.

The P-type silicon layer 5 is formed on the separating silicon dioxide film 2.
A single crystal film obtained by single crystallizing a polysilicon layer formed by a CVD method by a laser recrystallization method, having a concentration of about 10 ¹⁵ atoms / cm ³ and a thickness of 0.1 to 0.5 μm (preferably about 0.4 μm). With.

The P-type auto-doped region 6 is a high-concentration P-type region formed in the P-type silicon layer 5 by auto-doping boron ions from the separating silicon dioxide film 2 into the P-type silicon layer 5. It has a thickness less than half of.

The gate insulating film 7 is a 0.05 μm silicon dioxide film formed on the surface of the P-type silicon layer by a thermal oxidation method.

The gate electrode 8 is a 0.5 μm thick polysilicon electrode formed on the gate insulating film 7 by the CVD method.

The N-type source region 9A and the N-type drain region 9B are N-type regions formed by implanting phosphorus ions into the P-type silicon layer 5 by about 10 ¹⁵ atoms / cm ² and are the source or drain of the insulated gate field effect transistor. Is a region that functions as.

The manufacturing process of the MOS integrated circuit device of this embodiment will be described with reference to FIGS.

First, as shown in FIG. 2, a separation silicon dioxide film 2 is formed on the surface of the N-type silicon substrate 1 other than the openings 21 by the LOCOS method.

Next, as shown in FIG. 3, a photomask 22 is set on the surface of the opening 21, and then phosphorus ions are ion-implanted into the silicon dioxide film 2 for isolation at an acceleration voltage of 300 keV by about 10 ¹⁵ to ¹⁷ atoms / cm ^2. Then, boron ions are accelerated at an acceleration voltage of 30 keV for approximately 10 ¹⁵
Ion implantation of only ~ ¹⁷ atoms / cm ² .

Next, as shown in FIG. 4, the separation silicon dioxide film 2
P type polysilicon film 5 and 1 μm on top by CVD method
A thick protective silicon dioxide film 51 is sequentially formed. Then P
The type polysilicon film 5 is melted and crystallized by laser scanning to form a P type silicon layer 5. Infrared heating or electron beam heating may be adopted instead of laser heating.

Next, as shown in FIG. 5, a protective silicon dioxide film 51 is formed.
Are removed, and the P-type silicon layer 5 is formed into a trapezoid by selective etching.

After that, the P-type silicon layer 5 is formed by the normal MOS process.
Ion implantation for controlling threshold voltage, P-type silicon layer 5
Forming the gate insulating film 7 on the surface, forming the gate electrode 8 of polysilicon on the gate insulating film 7, oxidizing the surface of the gate electrode 8 and forming the silicon dioxide film 10 by it, N ⁺ type source by ion implantation, etc. Formation of the region 9A and the drain region 9B, annealing at about 800 ° C. as a post-process of each of the ion implantation steps, formation of a BPSG film 11 for passivation, BP on the gate electrode 8 and the source region 9A and the drain region 9B.
Opening of SG film 11, aluminum electrode wire 12 for wiring on BPSG film 11
The formation of A, 12B, 12C, the formation of the silicon nitride film 13 for passivation by the plasma CVD method, etc. are sequentially carried out.

The surface of the P-type silicon layer 5 below the gate electrode 8 is a channel region 14 in which an N-type channel is formed by the gate electrode 8. Further, the P-type auto-doped region 6 is formed not only by performing the annealing but also by irradiating the P-type polysilicon layer with a laser.

As a modification of this embodiment, instead of making the P-type silicon layer 5 a mesa type, the active region of the P-type silicon layer 5, that is, a region other than a required region may be selectively oxidized to be a silicon dioxide region. In this case, since a step is formed between the P-type silicon layer 5 and the silicon dioxide region formed by oxidizing the P-type silicon layer 5, the region of the P-type silicon layer 5 to be oxidized is etched to some extent in advance and then the oxidation is performed. can do. Further, arsenic, which exhibits a similar alkali gettering effect, can be used in place of phosphorus injected into the silicon dioxide film 2 for isolation as an intermediate insulating film. It is preferable that the phosphorus or arsenic is implanted deeper than the boron implanted in the P-type silicon layer 5. However, when a semiconductor element is formed on the surface of the silicon substrate 1, it is preferable that the phosphorus, arsenic, and boron do not reach the surface of the silicon substrate 1.

 The operation and effect of this embodiment will be described below.

First, the P-type auto-doped region 6 prevents formation of a back channel of the P-type silicon layer 5 and prevents fluctuations in electrical characteristics such as the threshold voltage of the insulated gate field effect transistor on the isolation silicon dioxide film 2. . The phosphorus or arsenic implanted in the separating silicon dioxide film 2 getsters the alkali ions in the separating silicon dioxide film 2. As a result, variations in electrical characteristics such as the threshold voltage of the insulated gate field effect transistor formed on the isolation silicon dioxide film 2 are reduced. This operation will be described in more detail. A P-type silicon layer 5 which is a channel region of an insulated gate field effect transistor on the isolation silicon dioxide film 2.
In FIG. 1, the depletion layer is almost depleted in actual use. Therefore, if the alkali ions move in the separation silicon dioxide film 2, an electrostatic potential change occurs in the depletion layer, which causes a potential change in the channel region 14 on the surface of the P-type silicon layer 5, and this insulation The threshold voltage of the gate field effect transistor is changed.
This problem in the SOI semiconductor device is greatly improved by the present embodiment in which the alkali ions in the separating silicon dioxide film 2 are gettered.

Further, in the present embodiment, phosphorus or arsenic or boron is doped into the separation silicon dioxide film 2 by ion implantation, so that the processing temperature can be kept low as compared with the case of doping by diffusion. Generally, the annealing temperature for ion implantation is 850 ° C. or lower, and the diffusion temperature is about 1000 ° C. Therefore, when a semiconductor element is formed on the silicon substrate 1, thermal deterioration of its electrical characteristics can be reduced.

The separation silicon dioxide film 2 has only to be installed above the silicon substrate 1, and does not necessarily have to be installed directly above the silicon substrate 1. Of course, an insulating film, an electrode or the like can be formed between the separating silicon dioxide film 2 and the silicon substrate 1. Furthermore, the separating silicon dioxide film 2 can be placed between two recrystallized silicon layers.

10 and 11 show the effect of stabilizing the threshold voltage of the N-type channel insulated gate field effect transistor in the MOS integrated circuit device of this embodiment.

FIG. 10 shows the variation of the threshold voltage after conducting the BT test when phosphorus ion implantation is omitted from the insulated gate field effect transistor of this embodiment shown in FIG. 1, and FIG. 11 shows the insulation of this embodiment. 7 shows the variation of the threshold voltage after the BT test is performed when the phosphorus ion implantation from the gate field effect transistor is not omitted. However, + BT represents an atmosphere temperature of 300 ° C., a gate / substrate voltage of +20 V (assuming the gate electrode 8 is positive), and a test time of 3 minutes. −BT represents an atmosphere temperature of 300 ° C., a gate / substrate voltage of −20 V The gate electrode 8 is defined as positive), and the test condition is 3 minutes. 10th
As can be seen from Fig. 11 and Fig. 11, the threshold voltage changes due to the implantation of phosphorus ions (change due to alkali ions).
Is significantly reduced.

In this embodiment, the implantation of phosphorus ions and boron ions may be selectively performed only in a specific region by using a mask. The isolation silicon dioxide film 2 can of course be changed to another insulating film. It is also possible to implant other trivalent ions instead of boron ions.
The P-type silicon layer 5 may be recrystallized in a seedless manner, particularly single crystallized, without providing the opening 21.

In this embodiment, since the alkali ion gettering and the back channel prevention can be performed only by changing the ion species in the ion process, there is an advantage that the productivity is high.

Another manufacturing process of the device of this embodiment will be described with reference to FIGS.
Shown in the figure.

First, as shown in FIG. 6, a separation silicon dioxide film 32 is formed on the surface of the N-type silicon substrate 31 other than the openings 30 by the LOCOS method.

Next, as shown in FIG. 7, a separating silicon dioxide film 32 is formed.
A P-type polysilicon film 35 having a thickness of about 0.4 .mu.m and a protective silicon dioxide film 61 having a thickness of about 1 .mu.m are sequentially formed on the upper surface by the CVD method. Next, the P-type polysilicon film 35 is melted and crystallized by laser scanning to form a P-type silicon layer 35. In this case, of course, electron beams or infrared lamps may be used instead of lasers.

Next, as shown in FIG. 8, a protective silicon dioxide film 61 is formed.
Are removed, and the P-type silicon layer 35 is formed in a trapezoidal shape by selective etching. Then, a trapezoidal P-type photomask is placed on the surface of the separating silicon dioxide film 32 in addition to the silicon layer 35, and phosphorus ions are accelerated to the separating silicon dioxide film 32 by an accelerating voltage.
About 10 ^15-17 atom / cm ² by ion implantation at 600 keV, to only the ion implantation about 10 ^15-17 atom / cm ² of boron ions at an acceleration voltage 150 keV.

Next, as shown in FIG. 9, a protective silicon dioxide film 61 is formed.
Is removed, and P is formed under the P-type silicon layer 35 by annealing.
A mold auto-doped region 36 is formed. This annealing temperature is
850 ℃, about 30 minutes.

After that, the insulated gate field effect transistor shown in FIG. 1 is formed by the same MOS process as that of the first embodiment.

In this embodiment, phosphorus and boron are ion-implanted after the P-type silicon layer 35 is single-crystallized by laser irradiation. However, laser irradiation is performed after phosphorus and boron ion implantation. Is also possible. In this way, the damage of the P-type silicon layer 35 due to the ion implantation is compensated by the subsequent single crystallization process of the P-type silicon layer 35 by laser irradiation.

Although phosphorus or arsenic and boron are ion-implanted into the separation silicon dioxide films 2 and 32 in each of the above-described embodiments, even when only phosphorus or arsenic is ion-implanted, the separation silicon dioxide film 2 and It is possible to prevent the threshold voltage of the insulated gate field effect transistor on 32 from being changed by the alkali ions in the silicon dioxide films 2 and 32 for isolation.

As described above, the semiconductor device of the present invention has the intermediate insulating film doped with boron and phosphorus or arsenic under the melt-recrystallized P-type silicon layer, and the boron Since it has a P-type auto-doped region formed by auto-doping, it is possible to prevent the threshold voltage of the N-type channel insulated gate field effect transistor on the intermediate insulating film from fluctuating due to alkali ions in the intermediate insulating film. The back channel of the N-type channel insulated gate field effect transistor can be prevented.

Further, according to the present invention, the deterioration of the crystallinity of the P-type silicon layer due to the ion implantation can be prevented as compared with the conventional ion implantation method for preventing back channel.

It is preferable that the boron is injected into the upper layer portion of the intermediate insulating film rather than the phosphorus or arsenic.

[Brief description of drawings]

FIG. 1 is a partial sectional view of a MOS integrated circuit device according to an embodiment of the present invention. 2, FIG. 3, FIG. 4, and FIG. 5 are sectional views for explaining the manufacturing process of the MOS integrated circuit device of FIG. FIGS. 6, 7, 8, and 9 are cross-sectional views for explaining another manufacturing process of the MOS integrated circuit device of FIG. FIG. 10 and FIG. 11 are graphs showing variations in the threshold voltage of the insulated gate field effect transistor of this example. 1 ... Silicon substrate 2 ... Separation silicon dioxide film (intermediate insulating film) 5 ... P-type silicon layer 7 ... Gate insulating film 8 ... Gate electrode 9A ... N-type source region 9B ... N-type drain region

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 29/78 618E (56) Reference JP-A-1-175262 (JP, A) JP-A-63 -258063 (JP, A) JP 60-126866 (JP, A) JP 60-64438 (JP, A) JP 58-143571 (JP, U)

Claims (1)

(57) [Claims] 1. A silicon substrate, an intermediate insulating film formed on the silicon substrate and ion-implanted with boron and phosphorus or arsenic, and a P-type silicon layer formed on the intermediate insulating film and melted and recrystallized. A P-type auto-doped region formed in the P-type silicon layer by auto-doping of boron from the intermediate insulating film to the P-type silicon layer; and a gate insulating film formed on the surface of the P-type silicon layer. A gate electrode formed on the gate insulating film, and an N-type source region and an N-type drain region which are formed on the surface of the P-type silicon layer and whose conduction is controlled by the gate electrode. A semiconductor device characterized by: