JPH0683787A - Parallel processor - Google Patents

Abstract

(57) [Abstract] [Purpose] The switch control circuit of the shift register enables the switches to be turned on even at intervals of two, so that the position of the memory where the vertical image data are stored is close to each other. , It is possible to calculate image data in the vertical direction. [Configuration] Flip-flops 22 _{1 to} 22 _{M / 2} and 24 _{1 to} 24 _{M / 2} which form a switch control circuit are provided,
The signals from these flip-flops are the selectors 25 ₁
Taken through ~ 25 _M. When a signal is input from the switch-on signal input terminal 21, the flip-flop 22
_{Since 1 to} 22 _{M / 2} are cascade-connected, the flip-flop 22 ₁ outputs the switch control signal for turning on the _first switch 2 _{1 first,} and the flip-flop 2 2 next.
A switch control signal for turning on the second switch 2 ₃ from 2 ₂ is output, ... Finally, the flip-flop 22
A switch control signal for turning on the _M- 1th switch 2 _M-1 from _{M / 2} is output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel processor used for digital processing of video signals.

[0002]

2. Description of the Related Art As a device for digitally processing a video signal, for example, "SVP: SERIAL VIDEO PR
OCESSOR / Proceedings of the
eIEEE 1990 CUSTOM INTEGRA
TED CIRCUITS CONFERENCE / P.
The devices shown in "17.3.1-4" are known.

This device is specifically composed of a parallel processor as shown in FIG. 7, for example.

That is, in the figure, for example, a video signal in which each pixel is composed of a plurality of bits is a word (pixel).
It is serially supplied to the input terminal 1 for one horizontal period (1H)
M number of registers (R) 3 _{1 in the} input shift register (serial / parallel converter) having a capacity (M) of minutes
Respectively 3 _M is stored via the switch 2 ₁ to 2 _M. Registers 3 _{1 to} 3 _M in this input shift register
There is connected to the M input-side memory 4 ₁ to 4 _M, respectively.

Further, M arithmetic circuits 6₁~ 6_MIn it
Input side memory 4₁~ 4 _MAnd the inputs on both sides
The data from the side memory is the selector (SEL) 5₁~ 5_M
M-side output memory 8₁~
8_MOutput side memory 8 corresponding to₁~ 8_MToso
The data from the output side memory on both sides of
L) 7₁~ 7_MIs supplied via.

Further, the output results from the arithmetic circuits 6 _{1 to} 6 _M are the input side memories 4 ₁ to 4 _M or the output side memory 8 respectively.
It is written in _{1 ~8 M.}

Further, each output side memory 8₁~ 8_MRespectively
In the output shift register (parallel / serial converter)
M registers (R) 9 of₁~ 9_MIt is connected to the.
And the register 9 in this output shift register₁~ 9
_MFrom each switch 10 ₁-10_MThrough
For example, each pixel is composed of multiple bits.
The output video signal is a word (pixel) serial output terminal 11
Is output to.

Therefore, in this device, the input is performed every horizontal period.
Register 3 in the power shift register ₁~ 3_MIs supplied to
The data of each pixel of the video signal is
Input side memory 4 within₁~ 4_MWritten in.
This input side memory 4₁~ 4_MThe data written to
Operation circuit 6 during one horizontal period₁~ 6_MSupplied and acted on
The calculated value is output side memory 8₁~ 8_MWritten in
It And within the horizontal blanking period after that, the output side
Memory 8₁~ 8_MData in the output shift register
Register 9₁~ 9_MWritten in and calculated every horizontal period
The processed video signal is taken out. Thus an example
For example, digital processing of the video signal is performed.

Further, in this device, the input side memory 4 ₁
.About.4 _M and address side memories 8 ₁ to 8 _M , address decoder 12 for controlling addresses, and arithmetic circuits 6 _{1 to} 6 _M
To control the calculation at and selectors 5 _{1 to} 5 _M , 7 ₁
There is only one arithmetic control circuit 13 for controlling each of .about.7 _M , which is common to all M input-side memories, output-side memories and arithmetic circuits.

That is, the device shown in FIG.
gle Instruction Multiple D
ata) method. In video signal processing, the same arithmetic processing is often performed on all pixels, so that the SIMD method of giving the same processing instruction to all arithmetic circuits can be sufficiently applied and there is no inconvenience. The SIMD method has an advantage that only one control circuit is required and the circuit scale is reduced.

In this device, the selectors 5 _{1 to} 5 _M ,
By the control of 7 _{1 to} 7 _M , the m-th arithmetic circuit 6 _m is
In addition to the calculation of the data (m-th pixel data of the video signal for one horizontal period (1H)) stored in the 4th input side memory 4 _m and the output side memory 8 _m , the data of both sides ( It is also possible to calculate m-1st and m + 1th pixel data).

The m-2th input side memory 4 _m-2 and the output side memory 8 _m-2, and the m + 2nd input side memory 4 _{m + 2}
Both the output side memory 8 _{m + 2} and the output side memory 8 _{m + 2} are supplied to the m-th arithmetic circuit 6 _m through the selectors 5 _m and 7 _m , so that m−2
It is also possible to calculate the pixel data of the 2nd pixel and the m + 2nd pixel data.

Therefore, in this device, the m-3rd or mth
If the + 3rd access can also be performed via the selector, the processing capability of the digital signal processing LSI is increased. However, for that reason, the selector becomes complicated, and the number of wirings increases, which is not possible in view of the circuit scale.

That is, in the conventional apparatus, as shown in FIG. 7, it is possible to access only the m−1th, mth and m + 1th input side memories and output side memories, or m
Only the configuration in which only the -2nd, m-1st, mth, m + 1th, and m + 2nd input side memories and output side memories can be accessed can be realized.

By the way, in the above-mentioned conventional apparatus, the operation of the input and output shift registers is performed as follows. That is, the switch-on signal input terminal 14 in the figure
Input a signal from the flip-flop (FF)
Since 15 ₁ to 15 _M are connected in cascade, first the flip-flop 15 ₁ outputs a switch control signal for turning on the _first switch 2 ₁ , and then the flip-flop 15 ₂ outputs the second switch switch 2. A switch control signal for turning on ₂ is output, and ... Finally, a switch control signal for turning on the _Mth switch 2 _M from the flip-flop 15 _M is output.

Then, for example, the video signal (A
₁ , A ₂ , A ₃ , ..., A _M ) are serially supplied. At the same time, a switch control circuit (flip-flops 15 ₁ to 15
_M ) switches from 1st to Mth in turn, switches 2 ₁ to 2
_M is gradually turned on, one horizontal period, which is supplied to a serial (1H) of data (video _{signal: A 1, A 2, A} 3, ...,
A _M in total of M M) are stored in order from the _first register 3 ₁ . Therefore, in the subsequent horizontal blanking period,
Data (A ₁ , A ₂ , A ₃ , ..., A _M ) is stored in each of the registers 3 _{1 to} 3 _M as shown in A of FIG.

These data are for this horizontal blanking period.
Input side memory 4 corresponding to each₁~ 4_MMoved to
It 1H worth of data supplied to the next serial
(B ₁, B₂, B₃, ..., B_M) Is the first register 3₁Or
They are stored in order. Therefore, the subsequent horizontal blanking period
In between, each register 3₁~ 3_MAs shown in Figure 8B
Data (B₁, B₂, B₃, ..., B_M) Is stored
It becomes a state. These data are for this horizontal blanking period
Input side memory 4₁~ 4_MMoved to
It

Therefore, for example, vertical 2-tap filter calculation is performed as follows. That is, m (m =
1 to M) -th input side memory 4 _m
m and B _m are stored. These data are supplied to the m-th arithmetic circuit 6 _m through the m-th selector 5 _m , and the filter calculation (X _m = a × A _m + b × B _m : a, b is a filter coefficient) is calculated, The calculation result X _m is stored in the m-th output side memory 8 _m .

The result X _m is the m-th register 9 _m in the output shift register during the subsequent horizontal blanking period.
The switch control circuit (flip-flop (FF) 17 _{1 to} 17 _M ) sequentially turns on the switches 10 ₁ to 10 _M from the _1st to the _{Mth in the} next horizontal period. X ₁ to result X _M are serially output in order. In this way, the vertical 2-tap filter calculation is performed.

The point to be noted here is that
Switch control circuit (flip-flop 15₁~ 15_M, 17
₁~ 17_M) Is switch 2 one by one in order₁~ 2_M,
10 ₁-10_MIn that you can only turn on
It

In the above description, the data for one horizontal period (1H) is exactly equal to the number M of processor elements, but consider the case of lower quality image data.

That is, consider the case where the data for one horizontal period (1H) is M / 2. Video signals (C _1, C _2, C ₃ , ..., C _{M / 2} ) are serially supplied from the input terminal 1. At the same time, the switch control circuit (flip-flop 1
5 ₁ to 15 _M ) sequentially turn on the switches 2 ₁ to 2 _{M / 2 from the 1st} to _{M /} 2th, and the data (video signal: 1H) for one horizontal period (1H) serially supplied.
C _1, C _2, C _3, ..., the total M / 2 pieces of C _{M / 2)} is gradually stored from the first register 3 ₁ in order. Therefore, in the subsequent horizontal blanking period, data is stored in each of the registers 3 _{1 to} 3 _M as shown in C of FIG.

The data (D _1, D _2, D ₃ , ..., D _{M / 2} ) for 1H supplied to the next serial is (M / 2) +
The data is stored in order from the first register 3 _{(M / 2) +1} .
Therefore, in the subsequent horizontal blanking period, each register 3
Data is stored in _{1 to} 3 _M as shown in D of FIG. These data are transferred to the input side memory 4 ₁ to 4 _M corresponding respectively with the horizontal blanking period.

At this time, it is impossible to perform a filter calculation with two taps in the vertical direction. This is because the calculation using the _m -th (m = 1 to (M / 2)) th data (Ym = a * _Cm + b * _Dm )
In order to perform m-th arithmetic circuit, [1] m + (M
/ 2) Data D stored in the second input memory
_m is once the m + (M / 2) -1st selector and m + (M
/ 2) -1st arithmetic circuit, m + (M / 2) -1st input side memory or output side memory,
[2] Then, the data D _m stored in the m + (M / 2) -1th input-side memory or the output-side memory is converted into m + (M /
2) -the second selector and m + (M / 2) -the second arithmetic circuit, m + (M / 2) -the second input side memory or the output side memory, and [3] and , M +
(M / 2) -The data D _m stored in the second input memory or the output memory is passed through the m + (M / 2) -3rd selector and the m + (M / 2) -3rd arithmetic circuit. M + (M /
2) Store in the -3rd input-side memory or output-side memory, and then:: [(M / 2) -1] Furthermore, m + the data D _m stored in the 2nd input-side memory or output-side memory is m + 1 Through the m-th selector and the m + 1-th arithmetic circuit, m +
The data is stored in the first input-side memory or the output-side memory, and [M / 2] After that, the data D _m stored in the m + 1-th input-side memory or the output-side memory is transferred to the m-th selector through the m-th selector. This is because it has to be processed by supplying it to the arithmetic circuit, and the number of instructions increases, which is unrealistic. That is, [1] to [(M / 2)
This is because there is an instruction for moving the data of [-1].

[0025]

The problem to be solved is that, when the data for one horizontal period (1H) is less than the number M of processor elements, the memory for storing image data in the vertical direction is stored. Since the positions are not close to each other, it is impossible to calculate the image data in the vertical direction (which requires an unrealistic number of instructions).

[0026]

A first means of the present invention is to input a plurality of data serially input from an input terminal 1 to a serial / parallel converter and to output parallel output of the serial / parallel converter. Are supplied in parallel to a plurality of processor elements, these data are arithmetically processed by the processor element, and a plurality of arithmetically processed data output in parallel from the processor element are input in parallel to a parallel / serial converter. Then, in the parallel processor that outputs the output of the parallel / serial converter from the output terminal 11, the parallel output of the serial / parallel converter that is supplied in parallel to the processor element is output in a specific order, and the processor element outputs the parallel output. Serial output of the parallel / serial converters supplied in parallel Which is a parallel processor and outputs a particular order.

The second means according to the present invention is, as one of a specific order of parallel outputs of the serial / parallel converters to be supplied to the processor elements in parallel,
The parallel processor according to the first means is characterized in that a plurality of intervals are provided.

The third means according to the present invention is characterized in that a plurality of intervals are provided as one of the specific orders of the serial outputs of the parallel / serial converters supplied in parallel from the processor elements. The parallel processor according to the first means.

According to a fourth means of the present invention, a plurality of data serially input from the input terminal 1 is input to a serial input terminal of a shift register having a serial input terminal, a parallel input terminal, a serial output terminal and a parallel output terminal. Input, supply the output from the parallel output terminal of the shift register to a plurality of processor elements in parallel,
These data are arithmetically processed by the processor element, a plurality of arithmetically processed data output in parallel from the processor element are input in parallel to the parallel input terminals of the shift register, and the serial output terminal of the shift register is input. Output from the parallel output terminal of the shift register in a specific order, and output from the serial output terminal of the shift register in a specific order. Is a parallel processor characterized by.

The fifth means according to the present invention is, in one of the specific orders of the outputs from the parallel output terminals of the shift register, the order of outputting at a plurality of intervals with respect to the input order from the serial input terminals. Is a parallel processor according to the fourth means.

According to a sixth aspect of the present invention, as one of the specific orders of the outputs from the parallel output terminals of the shift register, the order of outputting at a plurality of intervals with respect to the input order from the serial input terminals. Is a parallel processor according to the fourth means.

[0032]

According to this, the switch control circuit of the shift register can turn on the switch at intervals of two, even when the data for one horizontal period (1H) is less than the number M of processor elements. The positions of the memories storing the image data in the vertical direction can be close to each other, and the calculation of the image data in the vertical direction can be performed.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In FIG. 1, according to the present invention, for example, an input shift register (serial / parallel converter) can output at two intervals, and an output shift register (parallel / serial converter). It is also possible to output at two intervals. Therefore, even when the data for one horizontal period (1H) is M / 2, it is possible to perform a filter calculation with two taps in the vertical direction.

That is, the free circuit that constitutes the switch control circuit is
Flip-flop 15₁~ 15_M, 17 ₁~ 17_MIn addition to
Flip-flop (FF) 22₁~ 22_{M / 2}Over
24 ₁~ 24_{M / 2}, 27₁~ 27_{M / 2}And 29₁~ 2
9_{M / 2}Is provided and the signal from these flip-flops is
No. is selector 25₁~ 25_M, 30₁~ 30_MThrough
Taken out.

Therefore, in this figure, the selectors 25 ₁ ...
25 _M and 30 ₁ to 30 _M are placed on the left side as shown in the figure, so that switches 2 ₁ to 2 _M and 10 ₁ to 10 _M are arranged at two intervals.
Can be turned on. That is, when a signal is input from the switch-on signal input terminals 21 and 26, the flip-flops 22 _{1 to} 22 _{M / 2} and 27 _{1 to} 27 _{M / 2} are cascade-connected, so that the flip-flops 22 ₁ and 27 _{1 are first connected.}
Outputs a switch control signal for turning on the _first switches 2 ₁ and 10 ₁ , and then the flip-flops 22 ₂ and 2
A switch control signal for turning on the _third switches 2 ₃ and 10 ₃ from 7 ₂ is output ... Finally, the flip-flops 22 _{M / 2} and 27 _{M / 2} to the M−1th switch 2 _M−1 , A switch control signal for turning on 10 _M-1 is output.

Further, switch-on signal input terminals 23, 2
When a signal is input from 8, flip-flops 24 ₁ to 2
Since _{4 M / 2, 29 1 ~29} M / 2 are cascaded,
First, a switch control signal for turning on the _second switches 2 ₂ and 10 ₂ is output from the flip-flops 24 ₁ and 29 ₁ , and then the fourth switch 2 ₄ from the flip-flops 24 ₂ and 29 ₂ (not shown). A switch control signal for turning on 10 ₄ is output, ... Finally, the flip-flops 24 _{M / 2} , 29 _{M / 2} to the M-th switch 2 _M , 10
A switch control signal for turning on _M is output.

[0037] The selector 25 21 _to in FIG.
By setting 5 _M and 30 ₁ to 30 _M to the side opposite to the figure (to the right), the switches 2 ₁ to
2 _M, 10 ₁ ~10 _M it is possible to turn on. That is, when a signal is input from the switch-on signal input terminals 14 and 16, the flip-flops 15 ₁ to 15 _M and 17 ₁ to 1
Since 7 _M are cascade-connected, first the flip-flops 15 ₁ and 17 ₁ output a switch control signal for turning on the _first switches 2 ₁ and 10 ₁ , and then the flip-flops 15 ₂ and 17 ₂ 2nd switch A switch control signal for turning on the switches 2 ₂ and 10 ₂ is output, ... Finally, a switch control for turning on the M-th switch switches 2 _M and 10 _M from the flip-flops 15 _M and 17 _M. The signal is output.

Therefore, according to this apparatus, for example, it is possible to output two shift registers for input (serial / parallel converter) at intervals, and two shift registers for output (parallel / serial converter). It is possible to output at intervals. Therefore, even when the data for one horizontal period (1H) is M / 2, it is possible to perform a filter calculation with two taps in the vertical direction.

The description will be given below. Video signals (C _1, C _2, C ₃ , ..., C _{M / 2} ) are serially supplied from the input terminal 1. At the same time, the switch control circuit (flip-flop 2
2 _{1 to} 22 _{M / 2} ), the switches 2 ₁ to 2 _M-1 are turned on from the _first to the _M- 1th at an interval of two, and the data for one horizontal period (1H) serially supplied. (video _{signal: C 1, C 2, C} 3, ..., the total M / 2 pieces of C _{M / 2)} is,
The first register 3 ₁ is sequentially stored at two intervals. Therefore, during the subsequent horizontal blanking period, the data is stored in each register as shown in A of FIG.

The next 1H data (D _1, D _2, D ₃ , ..., D _{M / 2} ) supplied serially is converted into a switch control circuit (flip-flops 24 _{1 to} 24 _{M / 2).} ), The switches 2 ₂ to 2 _M are turned on from the second register to the _{Mth at} intervals of two, and are stored at intervals of _two from the second register 3 ₂ . Therefore, in the subsequent horizontal blanking period,
Data is stored in each register as shown in FIG. 2B. These data are transferred to the input side memory 4 ₁ to 4 _M corresponding respectively with the horizontal blanking period.

At this time, the filter calculation of the vertical two taps
Is possible. Because data C_m(M = 1 to (M / 2))
Is the 2m-1th input side memory 4_2m-1Stored in
And then the data D_mIs the 2mth input side memory 4_2m
It is stored in. That is, first, 2m-1
Th selector 5_2m-1Via the 2m-1st input side
Memory 4_2m-1Data C stored in_m2m-1
Eye arithmetic circuit 6_2m-1To the 2m-1st cell
Kuta 5_2m-1Via the 2mth input side memory 4 _2mThe case
Stored data D_m2m−1th arithmetic circuit 6
_2m-1Calculation using m-th data
(Y_m= AxC_m+ B × D_m) Is the 2m-1st calculation time
Road 6_2m-1Can be done at.

This calculation result Y _m is stored in the _2m− 1th output side memory 8 _2m−1 . The result Y _m is then _m in the output shift register during the subsequent horizontal blanking period.
It is stored in the 9th register 9 _m (A in FIG. 3), and the switches 10 ₁ to 10 _M-1 are sequentially turned on from the _1st to the _M- 1th at intervals of two switches in the next horizontal period by the switch control circuit. And output serially from X ₁ to X _{M / 2} . In this way, the vertical 2-tap filter calculation is performed.

Thus, according to the above-mentioned device, the switch control circuit (flip-flops 22 ₁ to 2 of the shift register).
2 _{M / 2} , 24 _{1 to} 24 _{M / 2} , 27 _{1 to} 27 _{M / 2} , 29 ₁
〜 29 _{M / 2} ), switch 2 ₁ 〜 2 _M , even at intervals of 2
It is possible to turn on 10 ₁ to 10 _M, and even when the data for one horizontal period (1H) is less than the number of processor elements: M, the positions of the memory where the image data in the vertical direction are stored are close to each other. Therefore, it is possible to calculate the image data in the vertical direction.

Further, FIG. 4 shows another configuration example of the parallel processor according to the present invention. In this figure, the selector 34
_{1 ~34 M-1, 38 1} ~38 by like figure _M-1, switch 2 ₁ ~2 _M, 10 ₁ ~10 with two intervals
_M can be turned on. That is, when a signal is input from the switch-on signal input terminals 31 and 35, the flip-flops 33 _{1 to} 33 _M and 37 _{1 to} 37 _M are cascade-connected in units of two, so that the flip-flop 3 is first connected.
A switch control signal for turning on the _first switches 2 ₁ , 10 ₁ is output from 3 ₁ , 37 ₁ , and then a switch control signal for turning on the _third switches 2 ₃ , 10 ₃ from the flip-flops 33 ₃ , 37 _3. Is output, and finally a switch control signal for turning on the _M- 1th switches 2 _M-1 and 10 _M-1 is output from the flip-flops 33 _M-1 and 37 _M-11 .

Further, switch-on signal input terminals 32, 3
When a signal is input from 6, flip-flops 33 ₂ , 3
The switch control signal for turning on the _second switches 2 ₂ and 10 ₂ from 7 ₂ is output, and then the flip-flop 3
The third switch 2 ₄ from 3 ₄ , 37 ₄ (not shown),
A switch control signal for turning on 10 ₄ is output,
Finally, the flip-flops 33 _M and 37 _M output switch control signals for turning on the M-th switches 2 _M and 10 _M.

Further, the selectors 34 _{1 to} 34 _M-1 , 38 ₁ to
By setting 38 _M-1 on the opposite side to the figure, the normal order (1
It is possible to turn on the switches 2 ₁ to 2 _M and 10 ₁ to 10 _M at intervals of one piece. That is, switch-on signal input 3
When a signal is input from the flip-flops 33 and 37, a switch control signal for turning on the _first switches 2 ₁ and 10 ₁ is _first output from the flip-flops 33 ₁ and 37 ₁ and then from the flip-flops 33 ₂ and 37 ₂ to the second switch control signal. Switches 2 ₂ and 10
A switch control signal for turning on ₂ is output ... Finally, a switch control signal for turning on the _Mth switches 2 _M and 10 _M is output from the flip-flops 33 _M and 37 _M.

Further, the inventor of the present application improved the parallel processor in advance and has a circuit configuration in which the input shift register (serial / parallel converter) and the output shift register (parallel / serial converter) are combined (see FIG. 5). (See Japanese Patent Application No. 4-32249).

In the configuration of FIG. 5, instead of the input shift register and the output shift register, a shift register having a serial input terminal, a parallel input terminal, a serial output terminal, and a parallel output terminal (see FIG. 6) is used. There is.

In FIG. 6, for the image data for one horizontal period (1H) input from the serial input terminal, the switches of the switch A group are sequentially turned on from the first switch to the Mth switch by the switch control circuit. It is stored in order from the register of. Then, after these data are stored, each data is output from the parallel output terminal and stored in the corresponding input side memory.

Then, each data after processing which has been calculated in each arithmetic circuit by the data before the image data for 1H is loaded by the parallel load signal from the parallel input terminal, and the switch B group by the switch control circuit. The switches are sequentially turned on from the 1st to the Mth, and each processed data is serially output from the serial output terminal.

The present invention can be applied to this circuit as well. That is, the signal from the switch control circuit in FIG. 6 may be turned on at two intervals using the circuit shown in FIG. 1 or FIG.

[0052]

According to the present invention, the switch control circuit of the shift register can turn on the switch at intervals of two, and the data for one horizontal period (1H) is larger than the number M of processor elements. Even when the number of images is small, the positions of the memories storing the image data in the vertical direction can be close to each other, and the calculation of the image data in the vertical direction can be performed.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an example of a parallel processor according to the present invention.

FIG. 2 is a diagram for explaining the explanation.

FIG. 3 is a diagram for explaining the explanation.

FIG. 4 is a configuration diagram of another example of the parallel processor according to the present invention.

FIG. 5 is a configuration diagram of another example of the parallel processor according to the present invention.

FIG. 6 is a diagram for explaining the explanation.

FIG. 7 is a configuration diagram of a conventional parallel processor.

FIG. 8 is a diagram for explaining the explanation.

[Explanation of symbols]

1 input terminal 2 _{1 to} 2 _M , 10 ₁ to 10 _M switch 3 _{1 to} 3 _M , 9 _{1 to} 9 _M register (R) 4 ₁ to 4 _M input side memory 5 _{1 to} 5 _M , 7 _{1 to} 7 _M selector (SEL) 6 _{1 to} 6 _M arithmetic circuit 8 ₁ to 8 _M output side memory 11 output terminal 12 address decoder 13 arithmetic control circuit 14, 16, 21, 23, 26, 28 switch-on signal input terminal 15 ₁ to 15 _M , 17 _{1 to} 17 _M , 22 _{1 to} 22 _{M / 2} ,
24 _{1 to} 24 _{M / 2} , 27 _{1 to} 27 _{M / 2} , 29 _{1 to} 29
_{M / 2} flip-flop

Claims (6)

[Claims] 1. A plurality of data serially input from an input terminal are input to a serial / parallel converter, and parallel outputs of the serial / parallel converter are supplied in parallel to a plurality of processor elements, and these data are output. Is arithmetically processed by the processor element, a plurality of arithmetically processed data output in parallel from the processor element is input in parallel to a parallel / serial converter, and the output of the parallel / serial converter is output from an output terminal. In the parallel processor for outputting, the parallel outputs of the serial / parallel converters supplied in parallel to the processor elements are output in a specific order, and the serial outputs of the parallel / serial converters supplied in parallel from the processor elements are output. Parallel processing characterized by outputting in a specific order Processor. 2. The parallel processor according to claim 1, wherein a plurality of intervals are provided as one of the specific orders of the parallel outputs of the serial / parallel converters supplied in parallel to the processor elements. . 3. The parallel according to claim 1, wherein a plurality of intervals are provided as one of the specific orders of the serial outputs of the parallel / serial converters supplied in parallel from the processor elements. Processor. 4. A serial input terminal, a parallel input terminal, a plurality of data serially input from the input terminal,
It is input to the serial input terminal of a shift register having a serial output terminal and a parallel output terminal, the output from the parallel output terminal of the shift register is supplied in parallel to a plurality of processor elements, and these data are calculated by the processor element. Parallel processing in which a plurality of data processed and output in parallel from the processor element are input in parallel to the parallel input terminal of the shift register, and the output from the serial output terminal of the shift register is output from the output terminal. A parallel processor, wherein in the processor, outputs from the parallel output terminals of the shift register are output in a specific order, and outputs from the serial output terminals of the shift register are output in a specific order. 5. One of the specific orders of the outputs from the parallel output terminals of the shift register is the order of outputting at a plurality of intervals with respect to the input order from the serial input terminals. The parallel processor according to claim 4. 6. One of the specific orders of output from the parallel output terminals of the shift register is the order of outputting at a plurality of intervals with respect to the input order from the serial input terminals. The parallel processor according to claim 4.