JPH09223012A - Arithmetic unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an arithmetic unit which unnecessitates instruction access and enables high-speed processing. SOLUTION: This unit is provided with plural ALU aij arranged in the shape of matrix, logic setting memory cells bij respectively connected to the ALU aij , adjacent wires 5 and 6 for mutually connecting the adjacent ALU aij , buses Xi and Yj provided between the matrixes of ALU aij , arbiters connected to the terminal parts of respective buses Xi and Yj for controlling the permission of outputs from the ALU aij to the buses Xi and Yj, and schedule memories connected to these arbiters. Then, one of the ALU aij is connected to an external input part 2, the other ALU is connected to an external output part 3, and the respective ALU aij are connected through the adjacent wires 5 and 6 and the buses Xi and Yj to all the ALU aij . Besides, these schedule memories are serially connected, and teaching schedules showing the timing of output permissions to the buses Xi and Yj are successively inputted to these schedule memories. Then, the logic setting memory cells bij set individual functions corresponding to a flow graph code, which is inputted as a signal for setting up the partial charge and connection function of individual functions, to the ALU aij and while using the ALU aij storing the individual functions and the arbiters, a logic circuit for any specified purpose is constructed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic unit capable of high-speed arithmetic processing, and more particularly to a specific-purpose logical arithmetic unit.

[0002]

2. Description of the Related Art A general arithmetic unit having a conventional CPU processes a program stepwise, and at the stage of processing the program, a program stored in an external schedule memory is required for the arithmetic processing. I had to read the instructions. For example, when an attempt is made to accumulate in a conventional arithmetic unit, the execution results in a step situation as shown in FIG. That is, in the conventional device, the instruction access, the input 1, the instruction access, the result input 1, the instruction access, the addition 1, the instruction access, the result storage 1, the instruction access, and the result output 1 are performed in one accumulation. 10 steps were required, and an instruction access was required for each step. Therefore, in order to obtain five operation result outputs by this device, processing of 50 steps is necessary.

[0003]

In such a conventional arithmetic unit as described above, necessary instructions must be read during the processing of the program, and all the arithmetic processing is performed stepwise in series. There is a problem that the processing speed becomes slow. An object of the present invention is to provide an arithmetic unit that does not require instruction access and can perform high-speed processing.

[0004]

According to the present invention, there is provided an arithmetic unit comprising: ALUs arranged in a matrix on a substrate; logic setting storage elements connected to each ALU; adjacent wirings connecting adjacent ALUs to each other; A bus provided between the queues of the ALUs, an arbiter connected to an end of each bus for controlling output permission from the ALU to the bus, and a schedule memory connected to each arbiter; Is connected to the external input unit, the other ALU is connected to the external output unit, each ALU is connected to all ALUs via the adjacent wiring and bus, and the schedule memory is connected in series and the schedule memory is connected. A teaching schedule indicating an output permission timing from the ALU to the bus is sequentially input from the outside to the memory, and the logic setting storage element is externally input to the memory. An individual function according to a flow graph code input as a signal for hardening a program for setting up the sharing of functions and connection relations of another function is set in each ALU, and each ALU storing the individual function and an arbiter for output permission control are set. It is characterized by organizing logic circuits for specific applications.

[0005] With the above configuration, a flow graph code is input from an external input unit as a means for hardening a program for setting individual functions and connecting relations (setup) according to processing to be executed by the arithmetic unit. if,
Since the logic setting storage element sets an individual function for each ALU, the ALU stores and holds its own arithmetic processing content corresponding to the flow graph code. In this state, each ALU becomes an arithmetic element having an individual function. Further, the teaching schedule is sequentially input to the schedule memory connected to the arbiter from the external input unit. Thus, this device is set, that is, set up as an arithmetic device dedicated to processing according to the flow graph code. Therefore,
Next, when predetermined data is input from the external input unit, each ALU executes an arithmetic process according to the set individual function without instruction access. At this time, the arbiter operates quickly according to the input teaching schedule. The buses provided between the matrices may be set according to the number of connected ALUs and the arbiter's capability, and it is not always necessary to provide buses between all rows and between columns.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a first embodiment of the present invention, and FIGS. 2 and 3 are a block diagram of the ALU knitted structure of FIG. 1 and an enlarged view of an arbiter connection portion, respectively.
In the first embodiment shown in FIGS. 1 to 4, the ALU knitted structure 4 having one ALU a _ij as a main element is arranged in an N × N matrix on the substrate 1 (where i and j are , 1 ≦ i, j ≦ N
Integer). As a result, N ² ALUa _ij can be arranged on the substrate 1. Then, the ALUa ₁₁ is connected to the external input unit 2
ALUa _N1 is connected to the external output unit 3.
As shown in FIG. 2, each ALUa _ij of the ALU organization 4 has
The logic setting storage elements b _ij are respectively connected by a channel 9, and the ALUs adjacent to each other vertically and horizontally are connected to each other via a pair of adjacent wirings 5 and 6 for input and output. Buses x _i and y _j are provided between the ALU matrices, and each ALU a _ij
Is connected to the nearest bus x _i , y _j via a pair of bus connection channels 7 and 8 for input and output. As described above, the ALU knitted structure 4 includes an ALU a _ij , a logic setting storage element b _ij , a pair of adjacent wirings 5 for connecting to left and right ALUs, and a pair of adjacent wirings for connecting to ALUs located above and below. The wiring 6, the buses x _i , y _j, and the buses x _i , y _j
Channels 7 and 8 for connecting Ua _ij , channel 10 for connecting logic setting storage element b _ij to left and right adjacent logic setting storage elements bi _(j-1) and bi _{(j + 1),} and logic setting storage Elements b _ij and AL
Ua _ij and a channel 9 for connecting Ua _ij . Incidentally, FIG. 1, in FIG. 2, the bus x _i, y _j indicated in each single line is to use a transmission path in both directions of the signal.

When the ALU assemblies 4 are arranged in a matrix, adjacent wirings and respective channels are inevitably connected as shown in FIG. However, the logic setting storage elements b _{21 to} b _2N
The direction of the signal of the channel 10 is opposite to that of FIG.
Hereinafter, the same applies to b _4j , b _6j . In order to connect all the logic setting storage elements b _ij in series,
External wirings 11 and 12 are provided. This external wiring 1
1 and 12, the logic setting storage elements b located at both ends
_ij , for example, b _1N and b _2N , b ₂₁ and b ₃₁ can be connected. The bus x ₀ is a bath set to connect two buses in the vertical direction, ALU is not connected. The buses x _i and y _j provided between ALUa _ij matrices are AL
The bus x _i , y _j provided next to the Ua _ij matrix
Those provided outside the matrix such as ₀ , x _N , and y _N are also included. Buses x _{0 to} x _N provided in the horizontal direction and buses y _{1 in the} vertical direction
Each end of ~y _N, arbiter 13 and 14 to control the timing of the output permission from the ALU to the bus are connected.

[0010] As shown in FIG. 3, the arbiter 14 has a schedule memory 18 and can store a teaching schedule input from the external input unit 2. With this teaching schedule, the arbiter
This is data for giving an output permission in the order determined by the ALU. Since each ALUa _ij is set with an individual function by each logic setting storage element b _ij , the specific use of the arithmetic unit is set, so that the output permission timing of each arbiter can be predetermined. The arbiter 13 also has a similar schedule memory 18. Switches S _{1 to} S _N are connected between the buses y _{1 to} y _N in the vertical direction and the bus x ₀ to switch the connection of the vertical and horizontal buses. The switch S ₁ to S _N is for performing switching in conjunction with the timing of the arbiter 13a connected to the bus x _0. For example, when transmitting signals from non-adjacent ALUa ₃₁ to ALUa ₂₃ , both ALUs must be connected via a bus.
First, the output permission of the arbiter 14a connected to the bus y _1, ALUA ₃₁ outputs a signal to the bus y _1. By the control of the arbiter 13a connected to the bus x _0, closes switch S _1, the connected bus y1 and bus x _0, closes S _3, bus x ₀ and bus y ₃ is to connect. As a result, the signal is input to the ALUa ₂₃ via the bus y ₁ → bus x ₀ → bus y ₃ .

Next, the operation of the first embodiment will be described.
First, a function sharing code which is a flow graph code for sharing the individual functions of the ALU a _ij of each ALU organization 4 is input from the external input unit 2 to the logic setting storage element b _ij . At this time, the function sharing code from the external input unit 2 is:
The data is input from the channel 10 to the logic setting storage element _bij .
Logic setting memory element b _ij is the channel 10 and the external wiring _{11,12, b 11 → b 12 →} , ..., → → b 1N → wiring 11 → b _2N, ..., and so on → b _N1, connected in series Have been. Therefore, the function sharing code input by the flow graph code from the external input unit 2 to the logic setting storage element b ₁₁ is transmitted by the channel 10 to the logic setting storage element b ₁₂ ,
Logic setting storage elements b ₁₃ ...
As a result, the function sharing code is inversely input from the N ² -th logical setting storage element b _N1 and finally input to the logical setting storage element b ₁₁ . This completes the input of the function assignment code, and the logic setting storage element b _ij receiving each function assignment code
Stores the entered code content and the AL
An individual function is set in Ua _ij . This individual function means that each A
It includes not only the function of calculating LUa _ij but also the function of switching connections with other ALUs.

From the external input unit 2, the schedule memory 1 of the arbiters 13 and 14 is provided separately from the function sharing code.
The teaching schedule, which is the switching timing of the switch S, is input to 8. Arbiter 13 and Arbiter 14
Are connected in series in the vertical and horizontal directions by the wirings 15 and 16, respectively, so that the teaching schedule can be changed from the arbiters 13 and 14 directly connected to the external input unit 2 as in the case of the logic setting storage element. It can be entered sequentially. When the setting of the individual functions of the ALU _ij and the input of the teaching module are completed in this way, the logic circuit of the arithmetic unit is formed, and the setup is completed as a logic circuit for a specific application. That is, the hardware of the flow graph code for a specific use is completed. When changing the use of the device, the external input unit 2
The logic setting storage element bij and the arbiters 13 and 14
Then, a flow graph code corresponding to the intended use may be input, and resetting may be performed. In this state, if data is input to the ALUa ₁₁ set as the input unit, the data is repeatedly sent to another ALUa _ij according to the set logic circuit and subjected to arithmetic processing. The ALUa _N1 to which the function is set is output to the external output unit 3.

[0011] Of the data input to ALU a _ij and processed, it is transmitted to adjacent ALUs via channels 5 and 6, and to other ALUs via buses x _i and y _j. . A plurality of ALUs are connected to each bus x _i , y _j . For example, the bus x _1, ALUA from above
₁₁ ~a _1N is connected. That is, N ALUs are connected to one bus. These ALU arbiter 13b so as not to output a signal to the bus x ₁ is adjusted at the same time. The arbiter 13b is so stored in the schedule memory 18 the timing for providing an output permission to the ALU connected to the bus x ₁ as teaching schedule, according to the schedule, may be given the output permission. If the schedule memory 18 does not store the teaching schedule, each arbiter 1
3, 3 must operate at very high frequencies, since they need to constantly monitor all ALUs connected to buses x _i , y _j .

If such an arithmetic device is set up by itself, it becomes a special-purpose arithmetic device specified for the purpose of performing necessary arithmetic processing, and the access to the memory unlike the conventional device is unnecessary. Even when obtaining the same calculation result as in the conventional example, instruction access is not required, so that the number of processing steps for obtaining one output is reduced by half. In the apparatus of the present embodiment, since each ALU _ij is set with an individual function in order to perform each processing, when obtaining a plurality of outputs, each step can be performed simultaneously. For example, FIG. 4 shows the processing status when performing accumulation. As shown in FIG. 4, according to this embodiment, input → result input → addition → result storage → result output can be performed simultaneously by shifting one step. In order to obtain five result outputs, 50 steps were required in the conventional apparatus, but in the present invention, 9 steps are sufficient. Therefore, there is an effect that the operation time is greatly reduced. Then, as the processing becomes more complicated and the number of steps increases, the difference increases.

The second embodiment shown in FIG. 5 is the same as the first embodiment except that all the arbiters 13 and 14 are connected in series by one wiring 16. In the first embodiment, FIG.
As described above, the arbiter 14 is connected to the external input unit 2 serially in the horizontal direction by using the wiring 16 and the arbiter 13 is serially connected in the vertical direction by using the wiring 15 in the present embodiment. Since the teaching schedules for all the arbiters 13 and 14 are sequentially input from one side, the number of input ports can be reduced. In the first and second embodiments, all the logic setting storage elements b _ij are connected in series,
Although the input code is configured to be sequentially forwarded, the code corresponding to each logic setting storage element b _ij may be directly input. However, when inputting individually, N ² input ports are required. Also, the buses x _i and y _j need not be provided between all the matrices.
By increasing the number of buses, more information can be transmitted, so that the processing time can be shortened, but on the other hand, a connection space is required. Direct connection, such as adjacent wiring, has a higher transmission speed than connection via a bus.However, since the connection is still complicated, the optimal pattern must be selected in consideration of processing speed and space. You can choose.

[0014]

According to the arithmetic unit of the present invention, during the processing of a program, there is no need to access an instruction for processing the program, so that the calculation speed is increased accordingly. In addition, when the result output can be repeated, the processing can be performed in parallel by shifting the steps, so that high-speed processing has become possible. In particular, the arbiter sets the output permission timing according to the input teaching schedule for each specific-purpose flow graph code.
The transmission and reception of signals for arbitration with the LU become unnecessary, and the system operates quickly. Therefore, the entire calculation processing time is significantly reduced.

[Brief description of drawings]

FIG. 1 is a lock diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of the ALU knitted body of FIG. 1;

FIG. 3 is an enlarged view of an arbiter connection part of FIG. 1;

FIG. 4 is a diagram shown to explain the accumulation processing status of the first embodiment;

FIG. 5 is a block diagram of a second embodiment of the present invention.

FIG. 6 is a diagram shown to explain an accumulation processing state in a conventional example.

[Explanation of symbols]

1 substrate 2 external input unit 3 external output unit 5, 6 adjacent lines 13 and 14 the arbiter x _i, y _j bus a _ij ALU b _ij logic setting storage device 18 scheduled memory

Claims (1)

[Claims] An ALU arranged in a matrix on a substrate, a logic setting storage element connected to each ALU, an adjacent wiring connecting adjacent ALUs to each other, a bus provided between a matrix of ALUs, An arbiter connected to the end of the bus for controlling output permission from the ALU to the bus, and a schedule memory connected to each arbiter, wherein one of the ALUs is connected to an external input unit, and the other is connected to an external input unit. AL
U is connected to an external output unit, each ALU is connected to all ALUs via the adjacent wiring and bus, the schedule memory is connected in series, and the schedule memory has an output permission timing from the ALU to the bus. Input the teaching schedule indicating
The logic setting storage element sets, in each ALU, an individual function corresponding to a flow graph code which is input as a signal for hardening a program for setting up the assignment of the individual functions and the connection relationship from the outside, and stores each of the ALUs storing the individual functions. And a arbiter for controlling output permission to form a logic circuit for a specific use.