[go: up one dir, main page]

JPH0677484A - Thin-film transistor and its manufacture - Google Patents

Thin-film transistor and its manufacture

Info

Publication number
JPH0677484A
JPH0677484A JP22868392A JP22868392A JPH0677484A JP H0677484 A JPH0677484 A JP H0677484A JP 22868392 A JP22868392 A JP 22868392A JP 22868392 A JP22868392 A JP 22868392A JP H0677484 A JPH0677484 A JP H0677484A
Authority
JP
Japan
Prior art keywords
film
hydrogen
plasma
polycrystalline
silicon nitride
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22868392A
Other languages
Japanese (ja)
Inventor
Takashi Itoga
隆志 糸賀
Yoshifumi Yaoi
善史 矢追
Tatsuo Morita
達夫 森田
Shuhei Tsuchimoto
修平 土本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP22868392A priority Critical patent/JPH0677484A/en
Publication of JPH0677484A publication Critical patent/JPH0677484A/en
Pending legal-status Critical Current

Links

Landscapes

  • Formation Of Insulating Films (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To efficiently and surely perform a hydrogenation operation in order to terminate a dangling bond near the interface between an Si film and a gate insulating film. CONSTITUTION:A hydrogen supply source for a hydrogenation operation is installed near the interface between an Si film and a gate insulating film by means of a manufacturing method including a process wherein an Si layer to be used as a channel is formed as a two-layer structure and a lower-layer channel poly-Si film 31 is formed, a process wherein a plasma SiN film 2 containing hydrogen in large quantities is formed by a PCVD method and a process wherein an upper-layer channel poly-Si film 32 is formed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は多結晶シリコン薄膜トラ
ンジスタの製造方法に係り、特に液晶表示装置などに利
用されるガラスや石英等の透明非晶質絶縁体基板上に多
結晶シリコン薄膜トランジスタを製造する方法に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a polycrystalline silicon thin film transistor, and more particularly to manufacturing a polycrystalline silicon thin film transistor on a transparent amorphous insulator substrate such as glass or quartz used for liquid crystal display devices. Regarding the method.

【0002】[0002]

【従来の技術】従来より、多結晶Si(シリコン)薄膜
トランジスタ(以下薄膜トランジスタをTFTと略す)
液晶表示装置の製造においては、無アルカリガラスや石
英等の透明非晶質絶縁体基板上に化学気相成長(CV
D)法等で非晶質Siを堆積し、これを電気炉により6
00℃程度で1〜100時間程度熱アニ−ルしたり、あ
るいは、レ−ザビ−ムやランプを照射して10nsec
〜数sec程度の間、800〜1200℃程度に昇温し
たりして多結晶化している。
2. Description of the Related Art Conventionally, a polycrystalline Si (silicon) thin film transistor (hereinafter, the thin film transistor is abbreviated as TFT)
In the manufacture of liquid crystal display devices, chemical vapor deposition (CV) is performed on a transparent amorphous insulator substrate such as alkali-free glass or quartz.
D) method or the like is used to deposit amorphous Si, and the amorphous Si is deposited by an electric furnace.
Heat anneal at about 00 ° C. for about 1 to 100 hours, or irradiation with a laser beam or a lamp for 10 nsec.
The temperature is raised to about 800 to 1200 ° C. for about several seconds to polycrystallize.

【0003】こうして作られた多結晶Si膜を所望の形
状、サイズにエッチングした後に、絶縁膜や多結晶Si
膜やメタル膜を形成してパタ−ニングする。そして通常
TFT形成工程の最後に、多結晶Si膜とゲ−ト絶縁膜
界面付近に存在するダングリングボンド(1019〜10
22cm-3)を水素で埋めて終端化させる水素化が行われ
ている。この水素化により、電界効果移動度の増加や閾
値電圧の低減等のトランジスタ特性を向上させている。
水素化までのプロセス最高温度は基板となるガラスの歪
点以下の約600℃以下である。
After etching the polycrystalline Si film thus formed into a desired shape and size, an insulating film or polycrystalline Si film is formed.
A film or metal film is formed and patterned. Then, at the end of the normal TFT formation process, dangling bonds (10 19 to 10 19) existing near the interface between the polycrystalline Si film and the gate insulating film are formed.
Hydrogenation is carried out in which 22 cm −3 ) is filled with hydrogen to be terminated. This hydrogenation improves transistor characteristics such as an increase in field effect mobility and a decrease in threshold voltage.
The maximum process temperature up to hydrogenation is about 600 ° C. or lower, which is lower than the strain point of the glass used as the substrate.

【0004】従来、水素化の方法はプラズマ水素化又は
SiN膜による水素化が行われて来た。プラズマ水素化
はプラズマ化学気相成長(PCVD)装置内で200〜
400℃で水素プラズマ下にTFTを晒して水素化する
方法であり、SiN膜による水素化は、パッシベ−ショ
ン膜として水素を多く含むSiN膜を成膜し、この膜中
の水素を300〜450℃程度の熱により拡散させて水
素化を行う方法である。
Conventionally, plasma hydrogenation or SiN film hydrogenation has been used as the hydrogenation method. Plasma hydrogenation is performed in a plasma-enhanced chemical vapor deposition (PCVD) apparatus at 200-
This is a method of hydrogenating a TFT exposed to hydrogen plasma at 400 ° C. Hydrogenation by a SiN film forms a SiN film containing a large amount of hydrogen as a passivation film, and hydrogen in the film is 300 to 450. It is a method of hydrogenating by diffusing by heat of about ℃.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、図2の
断面図に示すように従来のプレーナ型多結晶SiTFT
においては、水素が入り始める面とチャネルの多結晶S
i表面が1μm程度離れており、さらに厚さが200n
m程度以上あるSiゲート電極5の中は水素が拡散しに
くいことから、水素は層間絶縁膜を経てゲート電極周囲
から横方向にゲート絶縁膜4を通ってSi−ゲート絶縁
膜界面に到達する。
However, as shown in the sectional view of FIG. 2, the conventional planar type polycrystalline Si TFT is used.
In, the polycrystalline S of the surface and the channel where hydrogen begins to enter
i surface is about 1 μm apart, and the thickness is 200n
Since hydrogen hardly diffuses into the Si gate electrode 5 having a thickness of about m or more, hydrogen reaches the Si-gate insulating film interface from the periphery of the gate electrode through the gate insulating film 4 in the lateral direction through the interlayer insulating film.

【0006】このように拡散距離が長いことと、プラズ
マ水素化の場合にはPCVD装置内の水素濃度が109
cm-3程度と低いために、十分な水素化が成されるまで
に数時間程度の時間がかかるという問題点がある。
In this way, the diffusion distance is long, and in the case of plasma hydrogenation, the hydrogen concentration in the PCVD apparatus is 10 9
Since it is as low as cm -3, there is a problem that it takes about several hours until sufficient hydrogenation is completed.

【0007】また、SiN膜による水素化においては、
水素の濃度が1022cm-3程度あり、プラズマ水素化よ
りも密度が高いことから30分程度と短時間で水素化が
行われるものの、やはりパッシベーションのSiN膜と
多結晶Si−ゲート絶縁膜界面との距離が1μm程度離
れているため、大きいサイズのTFTは水素化されにく
く、移動度の増加や閾値電圧の減少等の特性改善がおこ
なわれないという問題点がある。
In addition, in hydrogenation using a SiN film,
Since the hydrogen concentration is about 10 22 cm -3 and the density is higher than that of plasma hydrogenation, hydrogenation is performed in a short time of about 30 minutes. However, the passivation SiN film and the polycrystalline Si-gate insulating film interface are still present. Since there is a distance of about 1 μm from each other, a large-sized TFT is less likely to be hydrogenated, and there is a problem that characteristics such as an increase in mobility and a decrease in threshold voltage are not performed.

【0008】またいずれの水素化においても、多結晶S
i内の水素拡散が遅いことからゲート電極周囲からゲー
ト絶縁膜4の中を横方向にのみ水素が拡散するという事
もあって、あらゆるサイズのTFTのSi−ゲート絶縁
膜界面全域に水素が拡散せず、TFTの特性がばらつく
という問題点もある。
Further, in any hydrogenation, polycrystalline S
Since hydrogen diffusion in i is slow, hydrogen is diffused from the periphery of the gate electrode only in the lateral direction in the gate insulating film 4, so that hydrogen is diffused in the entire Si-gate insulating film interface of TFTs of any size. However, there is also a problem that the characteristics of the TFT vary.

【0009】また別の水素化の方法として、チャネルS
i膜の下層全面にSiN膜を堆積して、水素供給源とS
i−SiO2界面との距離を短くするという方法がある
が、これはプラズマシリコン窒化膜自身がもつ大きい内
部応力と熱処理により生じる急激な温度変化のために、
レーザやランプで熱処理した後に、膜中にクラックが生
じてTFTが動作しなくなる等の問題が生じる。
As another hydrogenation method, the channel S
A SiN film is deposited on the entire lower layer of the i film, and a hydrogen supply source and S
There is a method of shortening the distance to the i-SiO 2 interface, but this is because of the large internal stress of the plasma silicon nitride film itself and the rapid temperature change caused by heat treatment.
After heat treatment with a laser or a lamp, a crack occurs in the film, which causes a problem that the TFT does not operate.

【0010】このほかに、ゲート絶縁膜にSiO2膜の
代わりにSiN膜を使用して水素化を不要にすることも
考えられるが、SiN膜自身がストイキオメトリーから
ずれ易いため抵抗率が109Ωcm程度と低かったり、
膜厚が100nm程度と薄かったりする場合には、絶縁
膜の伝導やピンホール等によりゲート・ソース間或いは
ゲート・ドレイン間がリークしやすくなるため200n
m程度以上に膜厚を厚くしなければならない。膜厚を厚
くすれば電界効果移動度が高くてもTFTの相互コンダ
クタンスが小さくなって、高速の動作が不可能となり、
ドライバ回路も透明ガラス基板に作り込むという多結晶
SiTFTの目的が達成されないことになる。
In addition to this, it is possible to use a SiN film as the gate insulating film instead of the SiO 2 film to eliminate the need for hydrogenation. However, since the SiN film itself tends to deviate from stoichiometry, the resistivity is 10%. As low as 9 Ωcm,
If the film thickness is as thin as about 100 nm, it is easy to leak between the gate and the source or between the gate and the drain due to conduction of the insulating film, pinholes, etc.
The film thickness must be thicker than about m. If the film thickness is increased, the mutual conductance of the TFT becomes small even if the field effect mobility is high, and high-speed operation becomes impossible,
This means that the purpose of the polycrystalline SiTFT, in which the driver circuit is also formed on the transparent glass substrate, cannot be achieved.

【0011】そこで本発明の課題は、レーザビームやラ
ンプによるアニールによって非晶質Siを多結晶化する
プレーナ型多結晶SiTFTにおいて、TFTのサイズ
にかかわらず多結晶Si−ゲート絶縁膜界面のダングリ
ングボンドを終端化させるための水素化を効率的かつ確
実に行い、SiTFTの電界効果移動度や閾値電圧など
の電気特性を一様に改善することにある。
Therefore, an object of the present invention is to provide a dangling at the interface between the polycrystalline Si and the gate insulating film in a planar type polycrystalline Si TFT in which amorphous Si is polycrystallized by annealing with a laser beam or a lamp, regardless of the size of the TFT. Hydrogenation for terminating the bonds is to be carried out efficiently and surely, and electric characteristics such as field effect mobility and threshold voltage of the SiTFT are uniformly improved.

【0012】[0012]

【課題を解決するための手段】本発明の多結晶シリコン
薄膜トランジスタは、チャネル部のポリシリコン膜を2
層とし、その層間に水素を多量に含むプラズマシリコン
窒化物からなる層を封じ込めることにより、前記課題を
解決するものである。また、本発明においては、基板上
に下層のチャネルポリシリコンを堆積する工程と、水素
を多量に含むプラズマシリコン窒化物をプラズマ化学気
相法で堆積する工程と、前記プラズマシリコン窒化物の
不要部分を食刻する工程と、上層のチャネルポリシリコ
ンを堆積する工程とを含む方法により多結晶シリコン薄
膜トランジスタを製造することができる。
In the polycrystalline silicon thin film transistor of the present invention, the polysilicon film of the channel portion is formed by two layers.
The problem is solved by forming a layer and enclosing a layer made of plasma silicon nitride containing a large amount of hydrogen between the layers. Further, in the present invention, a step of depositing a lower layer channel polysilicon on a substrate, a step of depositing a plasma silicon nitride containing a large amount of hydrogen by a plasma chemical vapor deposition method, and an unnecessary portion of the plasma silicon nitride. A polycrystalline silicon thin film transistor can be manufactured by a method including a step of etching and a step of depositing an upper layer channel polysilicon.

【0013】[0013]

【作用】本発明においては、多結晶SiTFTの製造プ
ロセスにおいて、チャネル部のポリSi膜を2層構造と
し、その層間に水素多量に含むプラズマシリコン窒化膜
を封じ込めることにより、SiTFT製造の最終工程で
のSi−ゲート絶縁膜界面のダングリングボンドの水素
化の水素源を前記プラズマシリコン窒化膜とすることが
できる。
According to the present invention, in the manufacturing process of the polycrystalline SiTFT, the polySi film of the channel portion has a two-layer structure, and the plasma silicon nitride film containing a large amount of hydrogen is confined between the layers, thereby making The plasma silicon nitride film may be used as a hydrogen source for hydrogenating dangling bonds at the Si-gate insulating film interface.

【0014】これにより、水素を必要とするダングリン
グボンドから水素供給源までの距離が非常に短くなり、
水素化のための熱アニール処理時間を短くすることがで
きる。また、チャネル部分に対して均一に水素が供給さ
れるため、同一基板上の画素用TFTやドライバ用TF
Tなどの異なる形状や寸法の多結晶SiTFTも均一に
水素化される。
As a result, the distance from the dangling bond that requires hydrogen to the hydrogen supply source becomes very short,
The thermal annealing process time for hydrogenation can be shortened. Further, since hydrogen is uniformly supplied to the channel portion, pixel TFTs and driver TFs on the same substrate.
Polycrystalline Si TFTs having different shapes and sizes such as T are also uniformly hydrogenated.

【0015】[0015]

【実施例】以下、図面を参照して本発明を詳細に説明す
る。図1は本発明の多結晶SiTFTでチャネルポリS
i膜を2層とし、その層間に水素を多量に含むプラズマ
シリコン窒化膜を挟んだ構造を有するものの断面図であ
る。このプラズマシリコン窒化膜は平行平板型プラズマ
気相成長(PCVD)装置によって堆積する。堆積条件
の一例は、原料の流量が、SiH4;30SCCM、N
3;100SCCM、圧力0.6Torr、RFパワ
ー0.16W/cm2、温度300℃である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the drawings. FIG. 1 shows a poly-Si TFT of the present invention with a channel poly S.
FIG. 3 is a cross-sectional view of a structure having two i films and a plasma silicon nitride film containing a large amount of hydrogen sandwiched between the i films. This plasma silicon nitride film is deposited by a parallel plate type plasma vapor deposition (PCVD) apparatus. An example of the deposition conditions is that the flow rate of the raw material is SiH 4 ; 30SCCM, N
H 3 ; 100 SCCM, pressure 0.6 Torr, RF power 0.16 W / cm 2 , temperature 300 ° C.

【0016】このようなプラズマシリコン窒化膜中の水
素はランプやレーザ等が加える短時間の熱では逃散せ
ず、TFTプロセスの後に行う保護膜の形成を終えても
プラズマシリコン窒化膜中には水素が1022cm-3程度
と十分な量が残っており、水素化の供給源となりうるも
のである。またSi膜は約200nm以下と薄いため、
膜の垂直方向にも水素は拡散することが可能である。
The hydrogen in the plasma silicon nitride film does not escape by the heat applied by a lamp, a laser or the like for a short time, and the hydrogen remains in the plasma silicon nitride film even after the formation of the protective film after the TFT process is completed. Is about 10 22 cm -3, which is a sufficient amount, and can serve as a hydrogenation supply source. Also, since the Si film is as thin as about 200 nm or less,
Hydrogen can also diffuse in the vertical direction of the film.

【0017】この構造のTFTの膜厚・膜種の一例は次
の通りである。プラズマシリコン窒化膜2は200nm
である。チャネルSi膜31および32は100nm程
度である。これはPCVD法等で非晶質Si膜を形成
し、ランプやレーザ光で多結晶化する。ゲート絶縁膜4
は熱CVD法等でSiO2膜を100〜200nm成膜
する。ゲート電極5は熱CVD法等で形成したポリSi
膜で200〜400nmの厚さである。層間絶縁膜6は
熱CVD法によるSiO2膜で300〜700nm形成
する。電極7はスパッタ法によって成膜したAl等のメ
タルで300〜1000nm成膜する。透明電極8はス
パッタ法等によるITO(indiumtin oxi
de)膜で、50〜300nm形成する。パッシベーシ
ョン膜9はPCVD法等によるSiN膜等で200〜5
00nm形成する。水素の拡散は図1の構造まで形成し
た後、電気炉において300〜450℃の熱アニールを
行う。
An example of the film thickness and film type of the TFT having this structure is as follows. Plasma silicon nitride film 2 is 200 nm
Is. The channel Si films 31 and 32 have a thickness of about 100 nm. In this, an amorphous Si film is formed by the PCVD method or the like and is polycrystallized by a lamp or laser light. Gate insulating film 4
Forms a SiO 2 film of 100 to 200 nm by a thermal CVD method or the like. The gate electrode 5 is poly-Si formed by a thermal CVD method or the like.
The film is 200-400 nm thick. The interlayer insulating film 6 is a SiO 2 film formed by the thermal CVD method to a thickness of 300 to 700 nm. The electrode 7 is formed of a metal such as Al formed by a sputtering method to a thickness of 300 to 1000 nm. The transparent electrode 8 is made of ITO (indium tin oxide) formed by a sputtering method or the like.
de) film with a thickness of 50 to 300 nm. The passivation film 9 is a SiN film or the like formed by the PCVD method, etc.
00 nm is formed. For the diffusion of hydrogen, after forming up to the structure of FIG. 1, thermal annealing is performed at 300 to 450 ° C. in an electric furnace.

【0018】図3はチャネルポリSiを2層としてプラ
ズマシリコン窒化膜を封じ込める構造を形成する過程の
一例を示す図である。Si膜は化学気相成長法で行えば
段差の部分も被覆でき、プラズマSiN膜を密封できる
ものである。そのプロセス例を以下に説明する。図3
(a)においてまず下層のチャネルポリSi31を堆積
する。図3(b)において挟み込むプラズマSiN膜2
を堆積した後、図3(c)においてSiN膜をパターニ
ングする。次に図3(d)において上層のチャネルポリ
Si32を堆積する。そして図3(e)においてチャネ
ル部ポリSi膜を一括してパターニングする。その後の
プロセスは従来法と同じである。
FIG. 3 is a diagram showing an example of a process of forming a structure for confining a plasma silicon nitride film with two layers of channel poly Si. If the Si film is formed by the chemical vapor deposition method, the step portion can be covered and the plasma SiN film can be sealed. An example of the process will be described below. Figure 3
In (a), the lower layer channel poly Si31 is first deposited. The plasma SiN film 2 sandwiched in FIG.
After depositing, the SiN film is patterned in FIG. Next, in FIG. 3D, the upper layer channel poly Si 32 is deposited. Then, in FIG. 3E, the channel portion poly-Si film is patterned at a time. The subsequent process is the same as the conventional method.

【0019】また、本実施例のTFT構造では、シリコ
ン窒化膜はSiより抵抗が十分に高いために、ソース・
ドレイン間のリークも起こらず、またシリコン窒化膜は
パターニングされているために、シリコン窒化膜自身の
持つ内部応力もトランジスタ周辺で緩和されて、膜中に
クラックが生じることもない。この構造を有するTFT
プロセスにおいて、非晶質Si膜の多結晶化及びソース
・ドレイン領域の活性化は短時間で行えるレーザやラン
プによるアニールが適当で、ソース・ドレインの活性化
もレーザやランプで行う方が望ましい。
In the TFT structure of this embodiment, the silicon nitride film has a sufficiently higher resistance than Si, so that
Leakage between drains does not occur, and since the silicon nitride film is patterned, the internal stress of the silicon nitride film itself is relaxed in the vicinity of the transistor, and cracks do not occur in the film. TFT having this structure
In the process, polycrystallization of the amorphous Si film and activation of the source / drain regions are preferably performed by laser or lamp annealing that can be performed in a short time, and it is more preferable to activate the source / drain by laser or lamp.

【0020】[0020]

【発明の効果】以上説明したとおり、本発明において
は、多結晶SiTFTの製造プロセスにおいて、チャネ
ル部のポリSi膜を2層構造とし、その層間に水素を多
量に含むプラズマシリコン窒化膜を封じ込めることによ
り、SiTFT製造の最終工程でのSi−ゲート絶縁膜
界面のダングリングボンドを終端する水素化の水素供給
源を界面近くに持つことになり、水素化のための熱アニ
ール時間が短くなり生産効率が高まるという効果があ
る。
As described above, in the present invention, in the manufacturing process of the polycrystalline Si TFT, the poly-Si film of the channel portion has a two-layer structure, and the plasma silicon nitride film containing a large amount of hydrogen is confined between the layers. As a result, a hydrogen supply source for hydrogenation that terminates the dangling bond at the Si-gate insulating film interface in the final step of SiTFT production is provided near the interface, and the thermal annealing time for hydrogenation is shortened, resulting in a production efficiency. Has the effect of increasing.

【0021】また、同一基板上の画素用TFTやドライ
バ用TFTなどのあらゆる形状や寸法の多結晶SiTF
Tも均一に水素化され、これらの電界効果移動度や閾値
電圧などの電気特性を一様に改善することができるとい
う効果がある。
In addition, polycrystalline SiTF of any shape and size such as pixel TFTs and driver TFTs on the same substrate.
T is also hydrogenated uniformly, and there is an effect that electric characteristics such as field effect mobility and threshold voltage can be improved uniformly.

【図面の簡単な説明】[Brief description of drawings]

【図1】図1は、本発明の多結晶SiTFTの断面図で
ある。
FIG. 1 is a cross-sectional view of a polycrystalline SiTFT of the present invention.

【図2】図2は、従来方式のプレーナ型多結晶SiTF
Tの断面図である。
FIG. 2 is a conventional planar type polycrystalline SiTF.
It is sectional drawing of T.

【図3】図3は、チャネルポリSiを2層としてプラズ
マシリコン窒化膜を封じ込める構造を形成する過程の一
例を示す断面図である。
FIG. 3 is a cross-sectional view showing an example of a process of forming a structure for confining a plasma silicon nitride film with two layers of channel poly Si.

【符号の説明】[Explanation of symbols]

1 無アルカリガラスや石英等の透明ガラス基板 2 プラズマシリコン窒化膜 3 チャネル部多結晶Si膜 4 ゲート絶縁膜 5 ゲート電極 6 層間絶縁膜 7 ソース・ドレイン電極 8 透明電極膜 9 パッシベーション膜 31 下層チャネル部多結晶Si膜 32 上層チャネル部多結晶Si膜 1 transparent glass substrate such as non-alkali glass or quartz 2 plasma silicon nitride film 3 channel part polycrystalline Si film 4 gate insulating film 5 gate electrode 6 interlayer insulating film 7 source / drain electrode 8 transparent electrode film 9 passivation film 31 lower layer channel part Polycrystalline Si film 32 Upper channel Polycrystalline Si film

フロントページの続き (72)発明者 土本 修平 大阪府大阪市阿倍野区長池町22番22号 シ ャープ株式会社内Front page continuation (72) Inventor Shuhei Tsuchimoto 22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 多結晶シリコン薄膜トランジスタにおい
て、チャネル部のポリシリコン膜を2層とし、その層間
に水素を多量に含むプラズマシリコン窒化物からなる層
を封じ込めることを特徴とする多結晶シリコン薄膜トラ
ンジスタ。
1. A polycrystalline silicon thin film transistor, comprising a polysilicon film of a channel portion having two layers, and enclosing a layer made of plasma silicon nitride containing a large amount of hydrogen between the layers.
【請求項2】 多結晶シリコン薄膜トランジスタの製造
方法において、基板上に下層のチャネルポリシリコンを
堆積する工程と、水素を多量に含むプラズマシリコン窒
化物をプラズマ化学気相法で堆積する工程と、前記プラ
ズマシリコン窒化物の不要部分を食刻する工程と、上層
のチャネルポリシリコンを堆積する工程とを含むことを
特徴とする多結晶シリコン薄膜トランジスタの製造方
法。
2. A method of manufacturing a polycrystalline silicon thin film transistor, the step of depositing an underlying channel polysilicon on a substrate, the step of depositing plasma silicon nitride containing a large amount of hydrogen by a plasma chemical vapor deposition method, and A method of manufacturing a polycrystalline silicon thin film transistor, comprising: a step of etching an unnecessary portion of plasma silicon nitride; and a step of depositing an upper layer channel polysilicon.
JP22868392A 1992-08-27 1992-08-27 Thin-film transistor and its manufacture Pending JPH0677484A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22868392A JPH0677484A (en) 1992-08-27 1992-08-27 Thin-film transistor and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22868392A JPH0677484A (en) 1992-08-27 1992-08-27 Thin-film transistor and its manufacture

Publications (1)

Publication Number Publication Date
JPH0677484A true JPH0677484A (en) 1994-03-18

Family

ID=16880176

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22868392A Pending JPH0677484A (en) 1992-08-27 1992-08-27 Thin-film transistor and its manufacture

Country Status (1)

Country Link
JP (1) JPH0677484A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6118139A (en) * 1997-12-09 2000-09-12 Nec Corporation Thin film transistor with reduced hydrogen passivation process time
US6200837B1 (en) 1998-06-30 2001-03-13 Hyundai Electronics Industries Co., Ltd. Method of manufacturing thin film transistor
JP2002057166A (en) * 2000-06-02 2002-02-22 Semiconductor Energy Lab Co Ltd Manufacturing method of semiconductor device
WO2006117900A1 (en) * 2005-04-26 2006-11-09 Sharp Kabushiki Kaisha Process for producing semiconductor device and semiconductor device
US7300829B2 (en) * 2003-06-02 2007-11-27 Applied Materials, Inc. Low temperature process for TFT fabrication
US7781775B2 (en) 2006-01-25 2010-08-24 Sharp Kabushiki Kaisha Production method of semiconductor device and semiconductor device
US8183135B2 (en) 2003-03-13 2012-05-22 Nec Corporation Method for manufacturing thin film transistor having hydrogen feeding layer formed between a metal gate and a gate insulating film
CN105009297A (en) * 2013-03-12 2015-10-28 应用材料公司 Pinhole evaluation method of dielectric films for metal oxide semiconductor TFT

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6118139A (en) * 1997-12-09 2000-09-12 Nec Corporation Thin film transistor with reduced hydrogen passivation process time
US6281053B1 (en) 1997-12-09 2001-08-28 Nec Corporation Thin film transistor with reduced hydrogen passivation process time
US6200837B1 (en) 1998-06-30 2001-03-13 Hyundai Electronics Industries Co., Ltd. Method of manufacturing thin film transistor
JP2002057166A (en) * 2000-06-02 2002-02-22 Semiconductor Energy Lab Co Ltd Manufacturing method of semiconductor device
US8183135B2 (en) 2003-03-13 2012-05-22 Nec Corporation Method for manufacturing thin film transistor having hydrogen feeding layer formed between a metal gate and a gate insulating film
US7300829B2 (en) * 2003-06-02 2007-11-27 Applied Materials, Inc. Low temperature process for TFT fabrication
JPWO2006117900A1 (en) * 2005-04-26 2008-12-18 シャープ株式会社 Semiconductor device manufacturing method and semiconductor device
US7897443B2 (en) 2005-04-26 2011-03-01 Sharp Kabushiki Kaisha Production method of semiconductor device and semiconductor device
WO2006117900A1 (en) * 2005-04-26 2006-11-09 Sharp Kabushiki Kaisha Process for producing semiconductor device and semiconductor device
US7781775B2 (en) 2006-01-25 2010-08-24 Sharp Kabushiki Kaisha Production method of semiconductor device and semiconductor device
CN105009297A (en) * 2013-03-12 2015-10-28 应用材料公司 Pinhole evaluation method of dielectric films for metal oxide semiconductor TFT
JP2016514372A (en) * 2013-03-12 2016-05-19 アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated Pinhole evaluation method of dielectric film for metal oxide semiconductor TFT
CN105009297B (en) * 2013-03-12 2019-06-14 应用材料公司 The pin hole appraisal procedure of dielectric film for metal oxide semiconductor films transistor

Similar Documents

Publication Publication Date Title
JP4802364B2 (en) Semiconductor layer doping method, thin film semiconductor device manufacturing method, and semiconductor layer resistance control method
US5834071A (en) Method for forming a thin film transistor
TW465113B (en) Thin film transistor, liquid crystal display device and method of fabricating the thin film transistor
WO2015123903A1 (en) Low-temperature polycrystalline silicon thin-film transistor, array substrate and manufacturing method therefor
KR20010093264A (en) Top gate thin-film transistor and method of producing the same
WO2018152875A1 (en) Method for manufacturing thin film transistor, thin film transistor and display
US6596572B1 (en) Method of fabricating a thin-film transistor having a plurality of island-like regions
EP1547140A1 (en) Method of manufacturing an electronic device comprising a thin film transistor
JPH0677484A (en) Thin-film transistor and its manufacture
CN100487878C (en) Method of fabricating semiconductor device and semiconductor fabricated by the same method
US20040023446A1 (en) Method of manufacturing thin film transistor, method of manufacturing flat panel display, thin film transistor, and flat panel display
KR100666563B1 (en) Method for manufacturing semiconductor device and semiconductor device manufactured by this method
KR100525436B1 (en) Process for crystallizing amorphous silicon and its application - fabricating method of TFT-LCD
TW200412673A (en) Buffer layer capable of increasing electron mobility and thin film transistor having the buffer layer
JP3817279B2 (en) Top gate type thin film transistor and manufacturing method thereof
JPH11354441A (en) Method for manufacturing semiconductor device
KR100489167B1 (en) Thin film transistor and its manufacturing method
KR100421907B1 (en) Process for crystallizing amorphous silicon and its application - fabricating method of TFT-LCD
US20060088961A1 (en) Method of fabricating poly crystalline silicon TFT
JPS62172761A (en) Amorphous silicon thin film transistor and its manufacturing method
KR100425156B1 (en) Process for crystallizing amorphous silicon and its application - fabricating method of TFT-LCD
JPH0462174B2 (en)
JPH05315360A (en) Manufacture of thin film transistor
JP2002368009A (en) Thin film transistor and liquid crystal display
KR100442289B1 (en) Process for crystallizing amorphous silicon and fabricating method of liquid crystal display device