KR100421907B1 - Process for crystallizing amorphous silicon and its application - fabricating method of TFT-LCD - Google Patents

Abstract

The present invention relates to a polycrystallization method required for a high quality thin film transistor element and a method of manufacturing a liquid crystal display device using the same. The polycrystallization method of the present invention comprises the steps of forming a first buffer layer on a substrate; Forming an amorphous silicon layer on the substrate, forming a second buffer layer at a predetermined interval on the amorphous silicon layer, forming a metal thin film layer on the entire surface of the substrate including the second buffer layer, and Forming an electrode at both ends, and applying an electric field to the metal thin film layer through the electrode and heat treating the substrate to crystallize the amorphous silicon layer.

Description

Process for crystallizing amorphous silicon and its application-fabricating method of TFT-LCD}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a polycrystalline silicon thin film transistor, and more particularly, to a polycrystallization method using an electric field applied metal induction crystallization method and a method of manufacturing a liquid crystal display device using the same.

Although TFT-LCDs have high density and large area, and display and driving circuits are fabricated on the same substrate, there is an urgent need for increasing mobility of thin film transistors, which are switching elements. It is difficult to satisfy this advantage with a thin film transistor (a-Si: H TFT).

Recently, polycrystalline silicon TFTs (Poly-Si TFTs) have attracted much attention as a method for effectively solving these problems. Since polycrystalline silicon TFTs have high mobility, they have the advantage of allowing peripheral circuits to be integrated on glass substrates, thus attracting much attention in terms of reducing production costs.

In addition, polycrystalline silicon TFTs have higher mobility than amorphous silicon TFTs, and are advantageous as switching elements of high-resolution panels, and are suitable for projection panels in which a lot of light is emitted due to less photocurrent compared to amorphous silicon TFTs.

There have been many reports on the method of fabricating polycrystalline silicon, and there are largely a method of directly depositing polycrystalline silicon and a method of forming polycrystalline silicon by depositing amorphous silicon and then crystallizing.

The former methods include Low Pressure Chemical Vapor Deposition (LPCVD) and Plasma Enhanced Chemical Vapor Deposition (PECVD). Among them, the LPCVD method has a substrate temperature of 550 ° C. or higher. Because of the use of expensive silica or quartz, the manufacturing cost is high and not suitable for mass production. In the case of PECVD, the SiF ₄ / SiH ₄ / H ₂ mixed gas can be deposited at 400 ° C. or lower, but it is difficult to suppress the grains. It is known to have serious problems.

The latter method, that is, a method of depositing and crystallizing amorphous silicon includes a solid phase crystallization (SPC) method and an excimer laser annealing (ELA) method.

The ELA method is a method of crystallizing a thin film in an instant by administering an excimer laser having a strong energy in an amorphous silicon thin film to form a polycrystalline silicon thin film having a large crystal grain size and excellent crystallinity. This is possible. However, the ELA method requires an expensive accessory equipment, such as an excimer laser, and thus can be said to have a limitation in mass production and large area LCD driving TFTs.

Solid phase crystallization is mainly a method of crystallizing an amorphous silicon thin film by using a furnace heating method in a furnace. Likewise, it is possible to prepare a polycrystalline silicon thin film having excellent crystallinity. Due to the slow reaction rate, a long crystallization time of several tens of hours or more is required at a high temperature of 600 ° C. or more.

In addition to the above methods, a lot of researches have recently been conducted to lower the crystallization temperature in order to use polycrystalline silicon in the manufacture of large-area liquid crystal displays, among which metal induced crystallization and metal induced side crystallization are performed. (Metal Induced Lateral Crystallization) has recently been in the spotlight.

According to these methods, when a specific type of metal is contacted with amorphous silicon, the crystallization temperature of the amorphous silicon can be lowered to 500 ° C. or lower, and the metal induction crystallization effect is known to occur in various kinds of metals.

Metal-induced crystallization differs in causing crystallization depending on the type of metal. That is, the crystallization phenomenon may vary depending on the type of metal in contact with the hydrogenated amorphous silicon (a-Si: H).

For example, metals such as aluminum (Al), gold (Au), and silver (Ag) are governed by the diffusion of silicon (Si) at the interface with amorphous silicon. In other words, at the interface between the metal and the silicon, a metastable silicide phase is formed by diffusion of silicon, and the silicide lowers the crystallization energy to promote the crystallization of silicon.

In contrast, in metals such as nickel (Ni) and titanium (Ti), diffusion of metals by annealing is dominant. That is, a silicide phase is formed by metal diffusion from the metal and silicon interface in the direction of the silicon layer, and the silicide promotes crystallization and lowers the crystallization temperature.

Hereinafter, a polycrystallization method according to the prior art will be described with reference to the accompanying drawings.

1A to 1C are cross-sectional views illustrating a method of crystallizing an amorphous silicon thin film according to the prior art.

As shown in FIG. 1A, the first buffer layer 102 and the amorphous silicon layer 103 are sequentially formed on the insulating substrate 101 by using chemical vapor deposition. In this case, a silicon oxide film (SiO ₂ ) is used as the material of the first buffer layer 102.

As illustrated in FIG. 1B, after depositing the second buffer layer 102a made of silicon oxide film on the amorphous silicon layer 103, the pattern is formed to have a predetermined interval.

Thereafter, a metal thin film layer 104 serving as a crystallization catalyst is formed on the entire surface of the substrate including the patterned second buffer layer 102a by sputtering. Nickel (Ni) or the like is used as the metal thin film layer 104.

Subsequently, when the substrate is heat-treated at 550 ° C. or higher, as shown in FIG. 1C, a silicide phase (NiSi ₂ ) is formed by diffusion of nickel (Ni) in the amorphous silicon layer direction. This silicide (NiSi ₂ ) is laterally diffused into the amorphous silicon layer below the second buffer layer to promote crystallization. For reference, the arrow direction of FIG. 1C indicates the crystallization progress direction.

However, the conventional polycrystallization method as described above has the following problems.

That is, the conventional method of polycrystallization of metal-induced crystallization has the advantage of obtaining device characteristics close to a single crystal when manufacturing a thin film transistor device, but the temperature required for the polycrystallization process is 550 ° C. or higher, and the above-mentioned high temperature is Because of the maintenance and polycrystallization, there is a disadvantage that the heat resistance has considerable limitations in applying ordinary glass.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a polycrystallization method that can secure the channel layer of a high quality stable thin film transistor and a method of manufacturing a liquid crystal display device using the same.

1A to 1C are cross-sectional views for explaining a polycrystallization method according to the related art.

2A to 2D are cross-sectional views illustrating a polycrystallization method according to a first embodiment of the present invention.

3A to 3D are cross-sectional views illustrating a polycrystallization method according to a second embodiment of the present invention.

4A to 4E are cross-sectional views illustrating a method of manufacturing a thin film transistor using the polycrystallization method of the present invention.

5A through 5F are cross-sectional views illustrating a method of manufacturing a liquid crystal display device using the polycrystallization method of the present invention.

Explanation of symbols for the main parts of the drawings

201: insulating substrate 202: first buffer layer

202a: second buffer layer 203: amorphous silicon layer

204: metal thin film layer 205: electrode

In accordance with an aspect of the present invention, there is provided a polycrystallization method, including forming a first buffer layer on an insulating substrate, forming an amorphous silicon layer on the first buffer layer, and forming the amorphous silicon layer. Forming a second buffer layer on the layer at a predetermined interval, forming a metal thin film layer on the entire surface of the substrate including the second buffer layer, forming electrodes on both ends of the metal thin film layer, and through the electrode And applying an electric field to the metal thin film layer and simultaneously heat-treating the substrate to crystallize the amorphous silicon layer. According to a second embodiment of the present invention, a polycrystallization method includes forming a first buffer layer on an insulating substrate. Forming a surface resistive heating material on the first buffer layer, and forming an amorphous silicon layer on the surface resistive heating material Forming a metal thin film layer on the amorphous silicon layer, forming an electrode on the surface resistance heating material, and applying an electric field to the surface resistance heating material through the electrode and simultaneously heat treating the substrate. And crystallizing the amorphous silicon layer.

The method of manufacturing a thin film transistor using the polycrystallization method as described above includes forming a first buffer layer on an insulating substrate, forming an amorphous silicon layer on the first buffer layer, and a predetermined interval on the amorphous silicon layer. Forming a second buffer layer over the substrate; forming a metal thin film layer on the entire surface of the substrate including the second buffer layer; and applying an electric field to a predetermined portion of the insulating substrate on which the metal thin film layer is formed. Forming a island-like semiconductor layer after crystallizing the silicon layer, forming a gate insulating film on the entire surface of the substrate including the semiconductor layer, forming a gate electrode on a predetermined portion of the gate insulating film, and the semiconductor Ion doping regions in the layer that do not overlap with the gate electrode to form source / drain regions And a process of activating the semiconductor layer, forming an interlayer insulating film on the semiconductor layer and the gate electrode, exposing a portion of the source / drain region, and connecting the exposed source / drain region. Forming a source electrode and a drain electrode.

In addition, a method of manufacturing a liquid crystal display device using the polycrystallization method as described above may include preparing a first substrate and a second substrate, forming a first buffer layer on the first substrate, and forming a first buffer layer on the first buffer layer. Forming an amorphous silicon layer, forming a second buffer layer at regular intervals on the amorphous silicon layer, forming a metal thin film layer on the entire surface of the substrate including the second buffer layer, and forming the metal thin film layer. Forming an island-like semiconductor layer after crystallizing the amorphous silicon layer by applying an electric field to a predetermined portion of the first substrate and crystallizing the amorphous silicon layer; forming a gate insulating film on the entire surface including the semiconductor layer; Forming a gate electrode and gate lines at a predetermined portion on the gate insulating layer, and overlapping the gate electrode in the semiconductor layer Forming a source / drain region by doping an undoped region, activating the semiconductor layer, forming a first insulating film on the semiconductor layer and the gate electrode, and then exposing the source / drain region; Forming a source / drain electrode and data lines so as to be connected to the exposed source / drain regions, forming a pixel electrode electrically connected to the drain electrode, and a liquid crystal between the first substrate and the second substrate. It is characterized by comprising a step of forming a layer.

Hereinafter, a polycrystallization method and a method of manufacturing a liquid crystal display using the same according to the present invention will be described in detail with reference to the drawings.

2A to 2D are cross-sectional views illustrating a polycrystallization method according to a first embodiment of the present invention, and FIGS. 3A to 3D are cross-sectional views illustrating a polycrystallization method according to a second embodiment of the present invention.

As shown in FIG. 2A, the first buffer layer 202 and the amorphous silicon layer (a-Si) made of silicon oxide (SiO ₂ ) material are formed on the insulating substrate 201 by chemical vapor deposition on the insulating substrate 201. : H) 203 is laminated sequentially. Here, the first buffer layer 202 prevents the impurity component of the insulating substrate 201 from diffusing into the amorphous silicon layer 203 and blocks heat flow into the substrate during the crystallization process.

The amorphous silicon layer 203 forms an amorphous silicon (a-Si: H) layer 203 using SiH ₄ and H ₂ mixed gas using plasma enhanced chemical vapor deposition.

Subsequently, as shown in FIG. 2B, the second buffer layer 202a of silicon oxide film is deposited on the amorphous silicon layer 203, and then patterned to be formed at a predetermined interval.

The metal thin film layer 204 is formed on the entire surface of the substrate including the second buffer layer 202a by sputtering. In this case, chromium (Cr), palladium (Pd), nickel (Ni), platinum (Pt) and the like are used as the metal thin film layer 204, and the deposition surface density is not increased in order not to adversely affect the operation characteristics of the device after completion of the device. Limited to extremely small amounts of 5 × 10 ¹² / cm 2 to 1 × 10 ¹⁸ / cm 2.

Subsequently, an electrode 205 for applying an electric field to left and right predetermined regions on the metal thin film layer 204 is added. At this time, as the material for the electrode 205, molybdenum (Mo), graphite (Graphite) and the like are used.

Thereafter, an electric field having a predetermined condition is applied to the electrode 205 and the substrate is heat-treated at the same time to crystallize the amorphous silicon layer. At this time, it is preferable that the applied voltage is set to 10 to 500 V / cm, the application time is 15 to 300 minutes, and the heat treatment temperature of the substrate is set to 400 to 600 ° C.

Through this process, as shown in FIG. 2C, the amorphous silicon layer 203 is crystallized into the polycrystalline silicon layer 206. The crystallization process is as follows.

The metal thin film layer is solid phase diffused to an amorphous silicon layer to form metal silicide. For example, nickel (Ni) forms nickel silicide (NiSi ₂ ).

The metal silicide serves as a catalyst for crystallization of amorphous silicon, that is, a crystallization nucleus, and later crystallizes by lateral diffusion into the amorphous silicon layer under the second buffer layer 202a.

In addition, since the amount of heat generated by electric field application and heat treatment is blocked by the first and second buffer layers having low thermal conductivity, the crystallization reaction rate can be further increased.

The lateral diffusion crystallization method as described above has an advantage of controlling the position of the crystal lines compared to the vertical diffusion crystallization method.

As shown in FIG. 2D, the unreacted metal (not shown) and the second buffer layer on the polycrystalline silicon layer 206 are removed. At this time, the removal method is using dry etching or wet etching, dry etching is an anisotropic etching by flowing an etching gas (Etching gas) in the plasma, wet etching is isotropic etching using an etching solution.

The polycrystallization method according to the second embodiment of the present invention is as follows.

First, as shown in FIG. 3A, a buffer layer 202 made of silicon oxide film (SiO ₂ ) or silicon nitride film (SiN _x ) is formed on an insulating substrate 201 by chemical vapor deposition, and then the first The surface resistance heating material 204a is formed on the buffer layer 202.

The surface resistance heating material 204a is formed for the future crystallization of the amorphous silicon layer, and the material may be formed of amorphous silicon doped with phosphorus (P) or boron (B), or microcrystalline silicon. This is used.

Thereafter, an amorphous silicon (a-Si: H) layer 203 is formed on the surface resistance heating material 204a by using a plasma enhanced chemical vapor deposition (SiH ₄₎ and H ₂ mixed gas. do.

As shown in FIG. 3B, the second buffer layer 202a made of silicon oxide is formed at a predetermined interval on the amorphous silicon layer 203.

Subsequently, the left and right predetermined regions of the amorphous silicon layer are etched to expose a surface resistance heating material, and then a metal thin film layer 204 is formed on the entire surface of the substrate including the second buffer layer 202a by sputtering. In this case, as the material of the metal thin film layer 204, chromium (Cr), palladium (Pd), nickel (Ni), platinum (Pt) and the like are used, and deposited in order not to adversely affect the operation characteristics of the device after completion of the device The surface density is limited to a very small amount of 5 × 10 ¹² / cm 2 to 1 × 10 ¹⁸ / cm 2.

Subsequently, an electrode 205 for applying an electric field to left and right predetermined regions on the surface resistance heating material 204a is added. At this time, as the material for the electrode 205, molybdenum (Mo), graphite (Graphite) and the like are used.

Thereafter, an electric field having a predetermined condition is applied to the electrode 205 and the substrate is heat-treated at the same time to crystallize the amorphous silicon layer. At this time, it is preferable that the applied voltage is set to 10 to 500 V / cm, the application time is 15 to 300 minutes, and the heat treatment temperature of the substrate is set to 400 to 600 ° C.

Through this process, as shown in FIG. 3C, the amorphous silicon layer 203 is crystallized into the polycrystalline silicon layer 206, and the crystallization reaction proceeds rapidly by the surface resistance heating material.

As in the first embodiment of the present invention, as shown in FIG. 3D, the second buffer layer and the unreacted metal on the polycrystalline silicon layer are removed.

Referring to the thin film transistor manufacturing process using the polycrystallization method as follows.

4A through 4E are cross-sectional views illustrating a method of manufacturing a thin film transistor using the polycrystallization method of the present invention.

First, as shown in FIG. 4A, the first buffer layer 202 and the amorphous silicon layer (a-Si: H) 203 of silicon oxide (SiO ₂ ) material are formed on the insulating substrate 201 using chemical vapor deposition. ) Are formed sequentially. The buffer layer 202 prevents the impurity component of the glass substrate from diffusing into the amorphous silicon layer 203.

As shown in FIG. 4B, a second buffer layer of silicon oxide is formed on the amorphous silicon layer 203 at predetermined intervals. Subsequently, the metal thin film layer 204 is formed on the entire substrate including the second buffer layer by sputtering. In this case, as the material of the metal thin film layer 204, chromium (Cr), palladium (Pd), nickel (Ni), platinum (Pt), or the like is used.

An electrode 205 for applying an electric field to left and right predetermined regions on the metal thin film layer 204 is added. In this case, as the material of the electrode 205, molybdenum (Mo), graphite, or the like is used.

Meanwhile, a surface resistance heating material (not shown) may be formed between the first buffer layer 202 and the amorphous silicon layer 203 as in the second embodiment of the present invention, and a surface resistance heating material may be formed. At one time, the electrode is added onto the surface resistance heating material.

Thereafter, an electric field having a predetermined condition is applied to the electrode 205, and at the same time, the insulating substrate is heat-treated to crystallize the amorphous silicon layer 203. At this time, it is preferable that the applied voltage is set to 10 to 500 V / cm, the application time is 15 to 300 minutes, and the heat treatment temperature of the substrate is set to 400 to 600 ° C.

After the crystallization of the amorphous silicon layer 203 to the polycrystalline silicon layer 206 through this process, the second buffer layer 202a and the unreacted metal are removed, and as shown in FIG. 4C, the polycrystalline silicon layer ( After the 206 is patterned to form an island, a gate insulating film 207 made of silicon oxide or silicon nitride is formed on the entire surface of the substrate including the polycrystalline silicon layer 206. Subsequently, a double metal layer of AlNd and Mo is sequentially stacked on the gate insulating layer 207 by sputtering, and then patterned to form a gate electrode 208 having a double layer structure.

4D, n + ions are implanted into the polycrystalline silicon layer 206 on both sides of the gate electrode 208 through an ion implantation process using the gate electrode 208 as a mask to form a source / drain region. After the formation and activation at a temperature lower than the crystallization temperature, an interlayer insulating film 209 is formed on the entire surface of the substrate including the gate electrode 208.

Next, as shown in FIG. 4E, the interlayer insulating film 209 and the gate insulating film 207 are etched to expose predetermined portions of the source / drain regions of the n + ion-doped polycrystalline silicon layer 206. Via holes), a stack of AlNd and Mo double metal layers are sequentially stacked so that the via holes are sufficiently filled, and then patterned to form source / drain electrodes 210 and 211, thereby obtaining a polycrystallization method according to the present invention. The thin film transistor manufacturing process is completed.

Hereinafter, a method of manufacturing a liquid crystal display using the polycrystallization method as described above will be described.

5A through 5F are cross-sectional views illustrating a method of manufacturing a liquid crystal display device using the polycrystallization method of the present invention.

As shown in FIG. 5A, after forming the first buffer layer 202 made of silicon oxide film on the first substrate 201a, a plasma using SiH ₄ and H ₂ mixed gas is formed on the first buffer layer 202. An amorphous silicon layer 203 is formed by chemical vapor deposition.

Thereafter, as shown in FIG. 5B, the amorphous silicon layer 203 is crystallized through the aforementioned crystallization process, and then, as shown in FIG. 5C, the amorphous silicon layer 203 may be used as a channel layer of a thin film transistor. Pattern it into island shapes so that it Thereafter, after forming the gate insulating film 207 made of silicon nitride film or silicon oxide film on the entire surface including the island-shaped polycrystalline silicon layer 206, after laminating a double metal layer of AlNd and Mo on the gate insulating film, Patterning forms a gate electrode 208 and a gate line (not shown) of the thin film transistor.

Thereafter, as shown in FIG. 5D, n + ions are implanted into the polycrystalline silicon layer 206 using the gate electrode 208 as a mask to form and activate a source / drain region, and then the gate electrode 208 and An interlayer insulating film 209 is formed on the entire surface including the gate line.

Subsequently, as shown in FIG. 5E, the interlayer insulating film 209 and the gate insulating film 207 are sequentially removed so that a predetermined portion of the source / drain region of the polycrystalline silicon layer 206 implanted with the n + ion is exposed. After the formation, the AlNd and Mo double metal films are formed to sufficiently fill the via holes, and then patterned to form the source electrode 210 and the drain electrode 211 of the thin film transistor.

Subsequently, as shown in FIG. 5F, the first passivation layer 212 made of silicon nitride and the second passivation layer 213 made of benzocyclobutene (BCB) are sequentially stacked on the entire surface including the source / drain electrodes 210 and 211. After that, a contact hole is formed to expose the drain electrode 211.

Thereafter, a transparent conductive film such as indium tin oxide (ITO) is formed on the entire surface of the substrate including the contact hole, and then patterned to form a pixel electrode 214 electrically connected to the drain electrode 211 through the contact hole.

Subsequently, although not shown in the drawings, a liquid crystal layer is formed between the first substrate 201a and the second substrate opposite to the manufacturing process of the liquid crystal display device according to the present invention.

Here, a color filter layer for expressing color is formed on the second substrate, and a black matrix pattern is formed to prevent light from being transmitted to the thin film transistor, the gate line, and the data line formed on the first substrate 201a. The common electrode for applying an electrical signal to the liquid crystal layer is formed together with the pixel electrode 214.

As described above, the polycrystallization method of the present invention and the manufacturing method of the liquid crystal display device using the same have the following effects.

Despite the low temperature process, there is an advantage in that a polycrystalline silicon layer having characteristics close to that of a high temperature polycrystalline silicon thin film can be manufactured, and polycrystallization is performed by applying an electric field to the metal thin film layer, thereby replacing the existing excimer laser method. By reducing equipment investment costs in the TFT-LCD field, price competitiveness in related fields can be improved.

Claims (22)

Forming a first buffer layer on the substrate; Forming an amorphous silicon layer on the first buffer layer; Forming a second buffer layer at regular intervals on the amorphous silicon layer; Forming a metal thin film layer on an entire surface of the substrate including the second buffer layer; Forming electrodes at both ends of the metal thin film layer; And crystallizing the amorphous silicon layer by applying an electric field to the metal thin film layer through the electrode and heat treating the substrate. The polycrystallization method according to claim 1, wherein the deposition surface density of the metal thin film layer is about 5 × 10 ¹² / cm 2 to about 1 × 10 ¹⁸ / cm 2. The polycrystallization method according to claim 1, wherein the metal thin film layer is formed of any one of chromium (Cr), palladium (Pd), nickel (Ni), and platinum (Pt). The polycrystallization method of claim 1, wherein the electrode applying an electric field to the metal thin film layer is formed of one of molybdenum (Mo) and graphite. The method of claim 1, wherein crystallizing the amorphous silicon, The voltage applied to the metal thin film layer is about 10 to 500V / cm, the time to apply is about 15 to 300 minutes, the heat treatment temperature is in the range of 400 to 600 ℃ polycrystalline crystal method. Forming a first buffer layer on the substrate; Forming a surface resistance heating material on the first buffer layer; Forming an amorphous silicon layer on the surface resistance heating material; Forming a second buffer layer at regular intervals on the amorphous silicon layer; Forming a metal thin film layer on the second buffer layer; Forming an electrode on the surface resistance heating material; And crystallizing the amorphous silicon layer by applying an electric field to the surface resistance heating material through the electrode and simultaneously heat-treating the substrate. 7. The polycrystallization method according to claim 6, wherein the deposition surface density of the metal thin film layer is about 5 × 10 ¹² / cm 2 to 1 × 10 ¹⁸ / cm 2. The polycrystallization method of claim 6, wherein the metal thin film layer is formed of any one of chromium (Cr), palladium (Pd), nickel (Ni), and platinum (Pt). The polycrystallization method of claim 6, wherein the electrode applying the electric field to the surface resistance heating material is formed of one of molybdenum (Mo) and graphite. 7. The method of claim 6, wherein the surface resistance heating material is formed of a conductive material. The polycrystallization method according to claim 10, wherein the conductive material is an amorphous silicon thin film doped with phosphorus (P) or boron (B) or a microcrystalline silicon thin film. The method of claim 6, wherein crystallizing the amorphous silicon, The voltage applied to the surface resistance heating material is about 10 to 500V / cm, the time to apply is about 15 to 300 minutes, the heat treatment temperature is in the range of 400 to 600 ℃. Preparing a first substrate and a second substrate, Forming a first buffer layer on the first substrate, Forming an amorphous silicon layer on the first buffer layer; Forming a second buffer layer at regular intervals on the amorphous silicon layer; Forming a metal thin film layer on the entire surface of the first substrate including the second buffer layer; Forming an island-like semiconductor layer after crystallizing the amorphous silicon layer by applying an electric field to a predetermined portion of the first substrate on which the metal thin film layer is formed, and then thermally treating the amorphous silicon layer; Forming a gate insulating film on the entire surface including the semiconductor layer; Forming gate electrodes and gate lines at predetermined portions on the gate insulating film; Forming a source / drain region by doping ions in the semiconductor layer; Activating the semiconductor layer; Forming an interlayer insulating film on the semiconductor layer and the gate electrode, and then exposing a portion of the source / drain region; Forming a first insulating film on the gate insulating film, and then exposing the semiconductor layers on both sides of the gate electrode; Forming source / drain electrodes and data lines to be connected to the exposed semiconductor layer; Forming a pixel electrode electrically connected to the drain electrode; And forming a liquid crystal layer between the first substrate and the second substrate. The method of claim 13, further comprising forming a surface resistance heating material on the first buffer layer. 15. The method of claim 14, wherein the surface resistance heating material is formed of a conductive material. The method of claim 15, wherein the conductive material is an amorphous silicon thin film doped with phosphorus (P) or boron (B) or a microcrystalline silicon thin film. 15. The method of claim 14, wherein the crystallizing of the amorphous silicon layer comprises applying an electric field to the surface resistance heating material and heat treating the first substrate. The method of claim 13, wherein the metal thin film layer is formed of any one of chromium (Cr), palladium (Pd), nickel (Ni), and platinum (Pt). The method of claim 13, wherein the step of crystallizing the amorphous silicon is characterized in that the metal thin film layer within a voltage of 10 to 500V / cm, an application time of 15 to 300 minutes, and a heat treatment temperature range of 400 to 600 ℃. Liquid crystal display device manufacturing method. The method of claim 13, wherein the source / drain electrodes are formed of a double layer of AlNd and Mo. The method of claim 13, wherein the deposition surface density of the metal thin film layer is about 5 × 10 ¹² / cm 2 to about 1 × 10 ¹⁸ / cm 2. The method of claim 13, Forming a silicon nitride film and a double insulating film of BCB on the entire surface including the source / drain electrodes; And electrically connecting the double insulation layer to the pixel electrode by exposing a portion of the etch-type drain electrode.