JPH0646519B2 - Sample-hold circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample and hold circuit, and more particularly to reducing switching noise generated when switching between a sample mode and a hold mode and improving a sampling speed. It relates to a sample and hold circuit.

[Conventional Example] A conventional sample and hold circuit is shown in FIG. First, the configuration will be described. Q ₁ , Q ₂ , and Q ₃ are NPN.
Is the type of transistor, the collector terminal of the transistor Q _1, Q ₂ which forms a differential pair is connected between the base and emitter of the transistor Q ₃ and the collector of the transistor Q ₃ are the power supply terminal Vcc, the transistors Q _1, Q _{The two} common emitters are connected to the ground terminal via the constant current source circuit 1.

The bases of the transistors Q ₁ and Q ₂ are connected to control signal input terminals 2 and 3 for applying the sample and hold signal φ, respectively, and the base of the transistor Q ₃ is connected to the emitter of the PNP transistor Q ₅ . The emitter of the PNP transistor Q5 is connected to the power supply terminal Vcc via the constant current source circuit 4, the collector is connected to the ground terminal, and the input signal V _sig is supplied to the base.

The base of the NPN transistor Q ₃ is connected to the emitter of the NPN transistor Q ₄ as shown in the figure, and the base of the transistor Q ₄ is always biased with a constant voltage V _B. Therefore, the base voltage of the NPN transistor Q ₄ is clamped without dropping below a predetermined voltage, and the transistor Q ₂ is prevented from being saturated.

Further, the emitter of the transistor Q ₃ are connected to the ground terminal through the hold capacitor C, NPN transistor constitutes a part of the output buffer amplifier Q
It is connected to the base of ₆ . That is, the constant current source 5 is connected to the emitter of NPN transistor Q _6, and is adapted to generate the V _BE6 voltage lower than the voltage of the hold capacitor C to the output terminal 6 connected to the emitter. Next, the operation of the sample and hold circuit having such a configuration will be described.

The control signal φ supplied to the control signal input terminals 2 and 3 sets the sampling mode period and the hold mode period. As shown in FIG. 3, the control signal φ has a predetermined voltage amplitude V _{H which} does not become the same level at the same time. Is a square wave signal,
As shown in the following table, when the control signal is at the “L” level and the control signal φ is at the “H” level, the sampling mode period T _S , the control signal is at the “H” level and the control signal φ is
There is set to the hold mode period T _H when the the "L" level.

That is, in the sampling mode period T _S , the transistor Q ₂ is turned off by the “L” level control signal and the transistor Q ₁ is turned on by the “H” level control signal φ, so that the transistor Q ₃ is also turned on and therefore the input When the signal V _sig is applied, the hold capacitor C
A voltage that is approximately equal to the input signal V _sig is held on both sides of.

On the other hand, in the hold mode period _TH , on the contrary, the transistor Q ₂ is turned on and the transistor Q ₁ is turned off, so that the current I _b from the constant current source circuit 4 is applied to the transistor Q ₂
To turn off the transistor Q ₃ . As described above, since the transistors Q ₁ and Q ₃ are turned off at the same time, the voltage generated in the hold capacitor C during the sampling mode period T _S becomes a constant hold voltage V _HD without being charged or discharged. An output voltage that is held and is lower than this hold voltage V _HD by V _be6 is output terminal 6
Is output to.

[Problems to be Solved by the Invention] However, in such a sample and hold circuit, the transistors Q ₁ and Q are controlled by the control signal φ.
_{When 2} switches from the sample mode to the hold mode or from the hold mode to the sample mode, switching noise occurs at the base terminal of the NPN transistor Q ₃ , and this noise is held through the base-emitter capacitance C _{be of the} transistor Q _{3 and} the like. -Since it jumps into the capacitor C, there is a problem that the accuracy of the holding voltage V _HD is lowered.

Further, the constant current I _a flowing through the transistors Q ₁ and Q ₂ that perform so-called switching operation cannot be made a large current due to the reduction of current consumption and the like, so that the charge of the hold capacitor C is charged and discharged. Therefore, it takes a long time to hold a predetermined charge corresponding to the input signal V _sig , and discharge has _a drawback that the sampling rate is slow because it is limited by I _a .

[Means for Solving Problems] The present invention has been made in view of the above problems, and includes a pair of complementary-connected drive transistors and a signal connected to the emitters of the pair of drive transistors. A holding capacitor, a drive circuit including an emitter-follower type transistor for converting an input signal into an inverted signal and supplying the inverted signal to the bases of the pair of drive transistors, and a collector for each base of the pair of drive transistors. Hold a potential of the base terminal of the pair of drive transistors, and a transistor differential pair for connecting a control signal for controlling conduction / non-conduction of the pair of drive transistors to the base while connecting the emitters in common. A voltage holding circuit for holding a predetermined voltage higher than the saturation voltage of the differential pair during a period It is characterized by

[Embodiment] An embodiment of the sample and hold circuit according to the present invention will be described below with reference to FIG. In the figure, the same or corresponding parts as those in FIG. 2 are designated by the same reference numerals.

First, the difference between the structure and FIG. 2 will be described.

The collector of _one NPN transistor Q ₁ forming a differential pair is connected to the base of a PNP transistor Q ₇ ,
The emitter of the P-transistor Q ₇ is the NPN transistor Q
_A so-called complementary circuit is formed by connecting to the emitter of PNP transistor _{3, and} the emitter of PNP transistor Q ₇ is connected to one end of hold capacitor C and the collector thereof is connected to the ground terminal. The base of the PNP transistor Q ₇ is connected to the power supply terminal Vcc via the constant current source circuit 7 and also connected to the emitter of the PNP transistor Q ₈ .
The PNP transistor Q ₈ has a collector connected to the ground terminal and a base biased to a constant DC voltage V _R.

Furthermore, the emitter of the PNP transistor Q ₈ is connected to the ground terminal via a separate constant current source circuit 8, and
Connected to the emitter of NPN transistor Q ₉
The collector of the transistor Q ₉ is connected to the power supply terminal Vcc, the base thereof is connected to the input signal source together with the base of the PNP transistor Q ₅ , and the input signal V _sig is supplied.

Here, the bias voltage V _B of the NPN transistor Q ₄ and the bias voltage V _R of the NPN transistor Q ₈ are determined based on the following relationship. First, the base-emitter voltage of the NPN transistor Q ₄ is V _be4 , the “H” level voltage of the control signal φ for conducting the transistor Q ₁ is V _H , and the minimum voltage of the input signal V _sig is V _{sig (MIN )}
Then, the voltage V _B is set to the condition of V _{sig (MIN)} + V _be4 ≧ V _B ≧ V _H + V _be4 (1), that is, by satisfying the condition of the above formula (1), sampling is performed. In the mode, the NPN transistor Q _{4 is set} to the reverse bias state, and the input signal V _sig
Can always be supplied to the NPN transistor Q ₃ . Next, the base-emitter voltage V _BE8 of PNP transistor _{Q 8,} when the maximum voltage of the input signal V _sig and V _{sig (MAX),} the voltage _{V R is, V R ≧ V sig (MAX} ) -V be8 ... It is set to the condition of (2). That is, by satisfying the condition of the above expression (2), the PNP transistor Q ₇ can always be turned off in the hold mode. Further, supposing that the currents of the constant current source circuits 4 and 8 are I _B and the currents of the constant current source circuits 7 and 1 are I _A , I _B <I _A is set.

Next, the operation of the sample and hold circuit having such a configuration will be described.

During the sampling mode period T _S in which the control signal is at the “L” level and the control signal φ is at the “H” level, the transistor Q1 is conductive and the transistor Q ₂ is non-conductive, so that the PNP transistor Q ₈ supplies a bias current. The current I _A from the constant current source 7 being absorbed is absorbed by the collector of the transistor Q ₁ and becomes non-conductive. Therefore, the input signal V _sig is supplied to the base of the NPN transistor Q ₃ via the PNP transistor Q ₅ and also to the base of the PNP transistor Q ₇ via the NPN transistor Q ₉ . At this time, the NPN transistor Q ₃ acts to charge the hold capacitor C and the PNP transistor Q ₇ to discharge the input signal V
A charge corresponding to _sig is accumulated in the hold capacitor C.

Next, the control signal is "H" level and the control signal φ is "L".
In the hold period _TH that is at the level, the transistor Q ₂ is conductive and the transistor Q ₁ is non-conductive. Accordingly, the transistor _{Q 4} is turned by the collector current of the transistor _{Q 2,} NPN transistor _{Q 3} are base potential becomes non-conductive drop to _V B -V _be4. Also, PNP transistor _{Q 7} becomes transistor Q8 is in a conducting state by the constant current source 7 is the base potential _V R +
_Since it goes up to V _be8 , it becomes non-conductive, and the voltage V _HD across the hold capacitor C is held.

Here, when switching noise occurs in the bases of the transistors Q ₃ and Q _{4 due to} the switching operation of the NPN transistors Q ₁ and Q ₂ at the time of switching between the sample mode and the hold mode, the base-emitter of the NPN transistor Q ₃ is generated. Inter-capacitance C _be3 and PNP transistor Q
_This is offset by the base-emitter capacitance C _{be7 of 7} , and the adverse effect on the hold capacitor C can be reduced extremely effectively.

Further, as described above, in the sample mode, the discharge of the hold capacitor C is performed by the PNP transistor Q _7, so that the sample is discharged more than the case where the discharge is performed within the current range of the constant current source circuit 1 as in the conventional example. The time can be shortened.

Greatly dive noise to the hold capacitor C by offset by the base-emitter capacitance of the transistor Q _3, Q ₇ of the switching noise is complementary connections occurring in mode switching according to this embodiment as described above To the transistor Q ₃ ,
Since the charge corresponding to the input signal V _sig is accumulated in the hold capacitor C by driving Q _7, the sampling speed can be improved.

As described above, according to the sample and hold circuit of the present invention, the switching noise generated by the switching operation of the differential pair is canceled by the base-emitter capacitance of the pair of complementary driving transistors. Further, since the hold capacitor is charged and discharged by the complementary connected transistors, switching noise can be greatly reduced and the sampling speed can be improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a sample and hold circuit according to the present invention, FIG. 2 is a circuit diagram showing a conventional sample and hold circuit, and FIG. 3 is a circuit diagram for explaining the circuit operation of FIG. It is a waveform diagram of a control signal. _{Q 1, Q 2, Q 3} , Q 4, Q 6, Q 9 ...... NPN transistors _{Q 5, Q 7, Q 8} ...... PNP transistor 1,4,5,7,8 ...... constant current source 6 ...... Output terminal C: Hold capacitor

Claims (1)

[Claims] 1. A pair of complementary connected drive transistors, a signal hold capacitor connected to the emitters of the pair of drive transistors, and a base of the pair of drive transistors by converting input signals into mutually inverted signals. A drive circuit composed of an emitter follower type transistor for supplying to each of the transistors, a collector of each of the bases of the pair of drive transistors, a common connection of the emitters, and conduction / non-conduction of the pair of drive transistors to the base. And a voltage holding circuit for holding the potential of the base terminals of the pair of drive transistors at a predetermined voltage equal to or higher than the saturation voltage of the differential pair during the hold period. A sample and hold circuit characterized in that