JPH0445199Y2 - - Google Patents

Description

[Detailed explanation of the idea] [Industrial application field] This invention relates to a sample and hold circuit.

[Summary of the idea]

This idea is based on the sample and hold circuit.
The first transistor and the second transistor are differentially connected, an input signal is applied to the base of the first transistor, and an input signal is connected between the collector of the first transistor and the collector of the second transistor, respectively, and one end of the power supply. A current mirror circuit is connected and the second
The collector of the transistor and the base of the second transistor are connected, this connection point is connected to the other end of the power supply via a hold capacitor, and the terminal voltage of the hold capacitor is connected to the base of the second transistor for buffering. the first transistor and the second transistor are turned on during the sample period, the collector of the first transistor is connected to the base of the fourth transistor, and the base current of the third transistor and the fourth transistor are connected. The base currents are made approximately equal, and the droop (signal level drop due to leakage) due to the base current of the third transistor constituting the output buffer of the sample and hold circuit is compensated for.

[Conventional technology]

As a conventional sample and hold circuit, there is one shown in FIG. 3, for example. In the example shown in FIG. 3, transistor 31 and transistor 32 are differentially connected, and an input signal is applied to the base of transistor 31 from terminal 33, and the base of transistor 32 and transistor 3
2 collectors are connected. The collector of the transistor 31 is connected to the cathode of the diode 34, and the anode of the diode 34 is connected to the resistive element 3.
5 to a power supply terminal 36 of voltage Vcc. The collector of transistor 32 is connected to the collector of PNP transistor 37, and the emitter of transistor 37 is connected via resistor element 38 to power supply element 36 at voltage level Vcc. The base of transistor 37 is connected to the cathode of diode 34, and a current mirror circuit is formed as a load for transistor 31 and transistor 32 forming a comparator.

A sample and hold pulse is supplied from a terminal 40 to the base of a transistor 39 that switches transistors 31 and 32.
The emitter of transistor 39 is transistor 31
and the emitter of the transistor 32, and the collector of the transistor 39 is connected to the power supply terminal 36.

The base of transistor 32 is grounded via hold capacitor 41. The base of transistor 32 is connected to the base of emitter follower transistor 42 forming a buffer, and the collector of transistor 42 is connected to power supply terminal 36. The emitter of the transistor 42 is grounded via a constant current source, and a sample and hold output signal is derived from the emitter of the transistor 42 to an output terminal 43.

In this conventional example, when a signal of a predetermined level shown in FIG. 4A is supplied to the input terminal 33, and the sample and hold pulse (see FIG. 4C) is low level "0" and the transistor 39 is turned off, the current mirror circuit is activated. Current flows and the hold capacitor 41 is charged and discharged so that the terminal voltage of the hold capacitor 41 becomes equal to the input voltage. A sample and hold output is obtained from the emitter of the emitter follower transistor 42 forming the buffer.

[Problem that the invention attempts to solve]

In the conventional sample and hold circuit shown in FIG. 3, the sample and hold output droops during the hold period due to the base current of transistor 42 as a buffer. That is, during the hold period in which the sample-and-hold pulse (FIG. 4C) is at a high level "1", the sample-and-hold output signal obtained from the emitter of the transistor 42 ( In FIG. 4B), the voltage drops due to leakage current (base current of the transistor 42), resulting in a so-called droop. This droop amount is determined by the hold time _Δt , the capacitance C of the hold capacitor 41, and the transistor 4.
Base current I _B of 2 (depends on emitter current of transistor 42 and current amplification factor h _FE of transistor 42)
Depends on.

Droop will not occur if the output buffer is of high input impedance such as a field effect transistor, but droop will inevitably occur in a transistor buffer, and when the capacitance C is small or the base current I _B is large, the droop will be considerable. becomes.

An object of this invention is to provide a sample and hold circuit in which droop is prevented from occurring during the hold period.

[Means for solving problems]

In this invention, a first transistor 1 and a second transistor 2 are differentially connected, an input signal is applied to the base of the first transistor 1, and the input signal is applied to the collector of the first transistor 1 and the second transistor 2. A current mirror circuit is connected between each of the collectors and one end 3 of the power supply, the collector of the second transistor 2 is connected to the base of the second transistor 2, and this connection point is connected to the other end of the power supply via the hold capacitor 8. The terminal voltage of the hold capacitor 8 is derived through the third buffer transistor 11, and the first transistor 1 and the second transistor 2 are turned on during the sample period. The collector of the transistor 13 is connected to the base of the fourth transistor 13, and the collector of the third
The base current of the fourth transistor 11 and the base current of the fourth transistor 13 are made approximately equal.

[Effect]

In this invention, during the hold period, the current flowing to the base of the third transistor 11 serving as an output buffer and the current flowing to the base of the fourth transistor 13 are made to be approximately equal.
Even if the base current of the transistor 11 flows during the hold period, current flows through the current mirror circuit so that the amount of charge charged in the hold capacitor 8 does not change, and droop due to the output buffer of the sample and hold circuit during the hold period is prevented. Prevented.

〔Example〕

An embodiment of this invention will be described below with reference to FIG.

Transistor 1 and transistor 2 are differentially connected, and an input signal is applied to the base of transistor 1 from input terminal 17 . The collector of transistor 1 is connected to the cathode of diode 4, and the anode of diode 4 is connected to power supply terminal 3 via resistance element 5. The collector of transistor 2 is
It is connected to the collector of a PNP transistor 6, and the emitter of the transistor 6 is connected to the power supply terminal 3 via a resistor element 7. The base of transistor 2 and the collector of transistor 2 are connected, and the base of transistor 2 is grounded via hold capacitor 8 . The emitter of transistor 9 is connected to the connection point between the emitter of transistor 1 and the emitter of transistor 2, a sample and hold pulse is applied to the base of transistor 9 from terminal 10, and the collector of transistor 9 is connected to power supply terminal 3.

When the sample and hold pulse becomes high level "1", transistor 9 is turned on and transistors 1 and 2 are turned off, resulting in a hold period. When the sample and hold pulse becomes low level "0", transistor 9 is turned off and the input signal is Current flows through the diode 4, resistance element 5, transistor 6, and resistance element 7 that constitute the current mirror circuit according to the difference between the signal and the hold voltage. Reference numeral 11 indicates an emitter follower transistor forming an output buffer, and the output terminal 12 is connected from the emitter of this transistor 11.
A sample and hold output signal is derived at , and the collector of transistor 11 is connected to power supply terminal 3 .

The transistor 13 is a transistor for causing a base current equal to that of the transistor 11 to flow through its base.The transistor 13 has a constant base connected in common so that the emitter current of the transistor 13 and the emitter current of the transistor 11 are constant currents and are equal to each other. Current transistors 14 and 15 are provided. The base of the transistor 14 is connected to the power supply terminal 3 via a resistance element, and is grounded via a diode and a resistance element.
The collector of transistor 4 is connected to the emitter of transistor 13, and the emitter of transistor 14 is grounded via a resistive element, thereby forming a constant current circuit 16. The collector of the transistor 15 is connected to the emitter of the transistor 11, and the emitter of the transistor 15 is grounded via a resistive element.
A constant current circuit 19 is configured.

In this embodiment, when the sample and hold pulse becomes low level "0", the transistor 9
is turned off, a current flows through the current mirror circuit according to the input signal applied to the base of the transistor 1, and the hold voltage, and a sample period begins in which the hold capacitor 8 is charged and discharged.

Further, when the sample hold pulse becomes high level "1", transistor 9 is turned on, transistor 1 and transistor 2 are turned off, and a hold period begins. At this time, the base current of the transistor 13 flows through the resistance element 5 and the diode 4. Correspondingly, a current equal to the base current of transistor 13 flows through the resistive element 7 and the emitter-collector path of transistor 6 into the base of transistor 11 due to the current mirror circuit. Therefore, unlike a conventional sample and hold circuit, even if a current flows into the base of the transistor 11 during the hold period, a current corresponding to this base current flows into the hold capacitor 8. Therefore, the leakage of charge from the hold capacitor 8 is compensated for,
Even if the base current of transistor 11 flows, the level of the emitter voltage of transistor 11 is kept constant. Therefore, no droop occurs in the sample-and-hold output signal during the hold period.

Moreover, FIG. 2 shows another embodiment of this invention.
In FIG. 2, the same parts as in FIG. 1 are given the same reference numerals, and detailed explanation thereof will be omitted.

In the example shown in FIG. 2, 18 indicates an NPN transistor, and this NPN transistor 18 is differentially connected to the transistor 9 to which the sample-and-hold pulse is supplied. A DC power supply 20 is connected to the base of the transistor 18 . transistor 18
The collectors of transistor 1 and transistor 2
Transistor 18 is connected to the emitter of transistor 18, and switches the current flowing through transistor 1 and transistor 2. The other parts are constructed in the same manner as in the above-mentioned embodiment.

In this embodiment, a current mirror circuit is formed by a diode 4 and a resistance element 5, a transistor 6 and a resistance element 7, a comparator is formed by a transistor 1 and a transistor 2, and a comparator is formed by a transistor 18 and a transistor 9. A current switch is formed.

When the base voltage of transistor 9 falls below the base voltage of transistor 18 due to the sample and hold pulse, transistor 9 is turned off and transistor 18 is turned on, current flows through the current mirror circuit, and transistor 6 is turned off according to the input signal. A sample period is reached in which the collector current follows and the charge in the hold capacitor 8 is charged and discharged. Further, when the base voltage of transistor 9 becomes higher than the base voltage of transistor 18, transistor 9 is turned on and transistor 18 is turned off, resulting in a hold period.

In this embodiment, in addition to the effects of the above-described embodiment, the level of the DC signal applied to the base of the transistor 18 can be selected to be small regardless of the sample-and-hold voltage, so even if the amplitude of the sample-and-hold pulse is small, the There is an advantage that the sample and hold operation can be performed well by switching on and off of the transistor 18 and the transistor 9.

[Effect of idea]

According to this invention, since the base current of the third transistor 11 and the base current of the fourth transistor 13 are made approximately equal, the third
The drop in the voltage level of the hold capacitor 8 due to the flow of the base current of the transistor 11 is compensated for. Therefore, there is an advantage that droop due to the output buffer of the sample and hold circuit is eliminated, and a good sample and hold output can be obtained.

[Brief explanation of the drawing]

Figure 1 is a connection diagram showing one embodiment of this invention, Figure 2 is a connection diagram showing another embodiment of this invention, and Figure 3 is a connection diagram showing another embodiment of this invention.
The figure is a connection diagram showing an example of a conventional sample-and-hold circuit, and FIG. 4 is a waveform diagram of each part of the conventional sample-and-hold circuit. Explanation of main symbols in the drawings: 1...first transistor, 2...second transistor, 3...
...Power supply terminal, 8...Hold capacitor, 11...
...Third transistor, 13...Fourth transistor.

Claims (1)

[Claims for Utility Model Registration] A first transistor and a second transistor are differentially connected, an input signal is applied to the base of the first transistor, and the collector of the first transistor and the second transistor are connected differentially. A current mirror circuit is connected between each of the collectors of the transistors and one end of the power supply such that the collector of the second transistor serves as an output, and the collector of the second transistor is connected to the base of the second transistor. a differential amplifier, the differentially connected first transistor and the second transistor;
a first current source connected to the emitter of the transistor; and a first terminal connected to the output terminal of the differential amplifier (the connection point between the collector of the second transistor and the base of the second transistor). and a hold capacitor whose second terminal is connected to the other end of the first current source; the emitters of the differentially connected first transistor and second transistor; The circuit is connected between the current sources, switches the current path of the first current source to another terminal during the hold period, disables sampling of the input signal by the differential amplifier, and holds the sampled input signal. a current changeover switch circuit held by a capacitor; a third transistor connected to the first terminal of the hold capacitor for deriving the voltage at the first terminal of the hold capacitor; and a third transistor connected to the emitter of the third transistor. a fourth transistor whose base is connected to the collector of the first transistor; and a fourth transistor whose base is connected to the emitter of the fourth transistor, and whose base current is connected to the collector of the fourth transistor. and a third current source whose current value is set to be approximately equal to the base current of the third transistor.