JPH11154863A - Sample/hold circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a sample-and-hold(S/H) circuit, with which input/output characteristics are made satisfactory by eliminating the phase error of switching timing at the time of S/H, based on an output voltage. SOLUTION: This S/H circuit is constituted of a switching circuit 2 of diode bridge connection, first and second pulse control current sources 11 and 12 connected to the first and second control input terminals of the switching circuit, first and second reference voltage sources 4 and 6 respectively connecting reference current sources to the first and second control input terminals, a first transistor connecting its emitter via a level shift circuit 7 to the first control input terminal, connecting its collector to the first reference voltage source and connecting its base to an output terminal 10, a second transistor connecting its emitter through a level shift circuit 8 to the second control input terminal, connecting its collector to the second reference voltage source and connecting its base to the output terminal, a holding capacitor C1 connected between the output terminal of the switching circuit and the output terminal, and high-input impedance buffer amplifier 9.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample-and-hold circuit having a high sampling frequency, for example, a high-speed and high-accuracy operation used for sampling a video band signal.

[0002]

2. Description of the Related Art Conventionally, as a sample-and-hold circuit capable of high-speed and high-accuracy operation, a circuit shown in FIG. Published by Radio Technology Co. on November 15, 1985, page 138).
In FIG. 4, reference numeral 101 denotes an input signal.
Are input to the input terminal A of the switching circuit 102. The switching circuit 102 includes a diode D
One of the control input terminals B of the switching circuit 102 is connected to a first reference voltage source 104 via a first reference current source 103, and is connected to a switching circuit 102. The other control input terminal C is connected to a second reference voltage source 106 via a second reference current source 105. The control input terminal B is connected to a first pulse control voltage source 107 via a diode D5,
The control input terminal C is connected to a second pulse control voltage source 108 via a diode D6. Here, the output of the first pulse control voltage source 107 and the second pulse control voltage source 10
The output of No. 8 is in a relation of inverted voltage output. The output terminal D of the switching circuit 102 is connected to a voltage holding (hold) capacitor C1 and a high input impedance buffer amplifier 109. The output terminal of the high input impedance buffer amplifier 109 is connected to an output terminal 110. ing.

[0003] The sample-and-hold circuit configured as described above comprises the first and second pulse control voltage sources 107,
The diodes D5 and D6 are switched by the output voltage of 108, and the switching circuit 102 composed of the diode bridge is turned ON (conducting state) and OFF (non-conducting state) in response to these pulse control voltages, and the input signal 101 Is sampled and held. That is, when the switching circuit 102 is conducting, the sample and hold circuit charges and discharges the hold capacitor C1 connected to the output terminal D of the switching circuit 102 in response to the input signal 101, and The charge voltage of the hold capacitor C1 is output by following the change of the signal voltage and when the switching circuit 102 is in a non-conductive state.

In the sample and hold circuit configured as described above, when the relative accuracy of each diode and each current source is good, the linearity of the input / output voltage in the sample state is good. Even if the middle input signal 101 changes, the control signals B and C of the switching circuit 102 are fixed at the reference voltage (pulse control voltage) by the diodes D5 and D6, so that the input signal due to the junction capacitance of the diode is output. The effect of leakage is small.

[0005]

By the way, in the conventional sample and hold circuit shown in FIG. 4, the control inputs B and C of the switching circuit 102 are connected to the reference voltage (D) by the diodes D5 and D6 as described above. Since the input signal is fixed at the pulse control voltage, the influence of the input signal leaking to the output is small. However, the level of the charge voltage (output voltage) of the hold capacitor C1 causes a time difference between the conduction and non-conduction of the diodes D5 and D6, that is, the control timing is shifted, so that the diode constituting the switching circuit 102 composed of a diode bridge is formed. The timing of conduction and non-conduction of D3 and D4 is shifted.

Next, this embodiment will be described in more detail with reference to the timing chart of FIG. First, the voltage generated across the diodes D3 and D4 in the hold state is represented by VD3
Assuming that VD4, it is expressed by the following equations (1) and (2). VD3 = VD5-VOUT + VA (1) VD4 = VD6-VB + VOUT (2) where VA is the first pulse control voltage source 107. The control voltage, VB, is the control voltage of the second pulse control voltage source 108, V
D5 and VD6 are voltages across the diodes D5 and D6.

Assuming that the conduction and non-conduction voltage (switching voltage) level of each diode is constant, the diode D3
And D5 switch at the same timing, and diodes D4 and D6 switch at the same timing. The switching timing of each diode is such that the level of each control voltage VA, VB is expressed by the following equation (3).
Switching is performed when (4) is established. VA = VOUT (3) VB = VOUT (4) Explaining this in correspondence with FIG. 5, the switching timing of the diodes D3 and D4 It can be seen that when the output voltage VOUT deviates from the midpoint voltage between VA and VB, a time difference ΔT (switching phase error) occurs.

As a result, when the output voltage level is other than the midpoint of the control voltage levels of the pulse control voltage sources 107 and 108,
In the case of the sampling state, the diodes D3 and D3
4 keeps track of the change in the input signal 101 to the hold capacitor C1 in a transient manner, and in the hold state, the offset between the conduction and non-conduction state of the diodes D3 and D4 causes an offset current. Flows into the hold capacitor C1, and an offset voltage is generated at the input / output voltage level.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem in the conventional sample and hold circuit, and eliminates a phase error in switching timing due to an output voltage, thereby providing a sample with good input / output characteristics at the time of sample and hold. It is an object of the present invention to provide a hold circuit.

[0010]

In order to solve the above-mentioned problems, the present invention provides a switching circuit comprising a bridge-connected diode and a common anode which is a first control input terminal of the switching circuit. A first pulse control current source, a second pulse control current source connected to a common cathode side which is a second control input terminal of the switching circuit, and a first pulse control current source connected to a first control input terminal of the switching circuit.
A first reference voltage source connected via a second reference current source via a second reference current source to a second control input terminal of the switching circuit; A first transistor having an emitter connected to a first control input terminal of the switching device via a first level shift circuit, a collector connected to the first reference voltage source, and a base connected to an output terminal; A second transistor having an emitter connected to a second control input terminal of the circuit via a second level shift circuit, a collector connected to the second reference voltage source, and a base connected to an output terminal; A voltage holding capacitor connected to the output terminal of the switching circuit, and a high input impedance buffer amplifier connected between the output terminal and the output terminal of the switching circuit;
A sample-and-hold circuit is configured by using an input terminal of the switching circuit as an input terminal of an input signal.

In the sample hold circuit configured as described above, in the hold state, the first and second transistors cause the first and second transistors of the switching circuit to operate.
By fixing the control input terminal of the control circuit at the hold output voltage, the switching timing phase error can be eliminated, and the output offset at the time of sample-hold switching can be improved.

[0012]

Next, an embodiment will be described. FIG. 1 shows a first example of a sample and hold circuit according to the present invention.
FIG. 2 is a circuit configuration diagram showing the embodiment. In FIG.
Reference numeral 1 denotes an input signal. The input signal 1 is input to an input terminal A of the switching circuit 2. This switching circuit 2
Is constituted by a bridge circuit composed of diodes D1 to D4, and one control input terminal B of the switching circuit 2 is
The other control input terminal C of the switching circuit 2 is connected to the first reference voltage source 4 via the first reference current source 3 and is connected to the second reference voltage source 6 via the second reference current source 5. Connected to. The control input terminal B is connected to the emitter of the first transistor Q1 via the first level shift circuit 7, and the control input terminal C is connected to the second level shift circuit 8
And the base of the first transistor Q1 and the base of the second transistor Q2 are connected to the emitter of the second transistor Q2.
Input impedance buffer amplifier 9 for outputting the output voltage of hold capacitor C1 connected to output terminal D of
The output terminal of the high input impedance buffer amplifier 9 is connected to the output terminal 10. The collector of the first transistor Q1 is connected to the first reference voltage source 4, and the collector of the second transistor Q2 is connected to the second reference voltage source 6. A first pulse control current source 11 is connected to the control input terminal B, and a second pulse control current source 12 is connected to the control input terminal C.

The sample and hold circuit thus configured conducts the first and second transistors Q1 and Q2 by the currents IA and IB from the first and second pulse control current sources 11 and 12, respectively. The diodes D3 and D4 constituting the switching circuit 2 are switched in a holding state) and a non-conducting state (sample state). Here, the diode D3 in the hold state
The voltages VD3 and VD4 at both ends of D4 are expressed by the following equations (5),
It is represented by (6). VD3 = VBEQ1 + Z1 × I (5) VD4 = VBEQ2 + Z2 × I (6) Note that VBEQ1 and VBEQ2 are transistors Q1 and Q
2, Z1 and Z2 are impedances of the level shift circuit.

Here, first and second pulse-controlled current sources
The pulse control currents of 11 and 12 are IA and IB, respectively, and the reference currents of the first and second reference current sources 3 and 5 are IREF.
VBEQ1 = VBEQ2, Z1 = Z2, I = IA-IR
If EF = IB-IREF and IA = IB> IREF, the diode D3
The voltages VD3 and VD4 across D4 are equal, and the switching diodes D3 and D4 and the transistors Q1 and Q4
2 is turned on or off at the output voltage (VOU
T) is not affected by the level and is simultaneous, that is, since the switching phase error is eliminated, no offset occurs during the sample and hold control. In the hold state, even if the input signal 1 changes during the hold period, the control input terminals B and C of the switching circuit 2 are fixed at the output voltage by the transistors Q1 and Q2. Also has no effect of output leakage. The level shift circuits 7 and 8 are provided because the level shift circuits 7 and 8 generate voltage drops due to the pulse control currents IA and IB.
This is to prevent the diodes D1 and D2 of the switching circuit 2 from conducting in the hold state when the input voltage level largely changes.

FIG. 2 is a circuit diagram showing a second embodiment of the sample and hold circuit according to the present invention. In this embodiment, the first and second level shift circuits in the first embodiment are respectively constituted by resistors R1 and R2, and a pulse control current is supplied to transistors Q3 and Q4, a resistor R3 and a pulse control voltage source. A first and second current mirror circuit generated by a voltage-current conversion circuit 14 comprising
It is configured to supply to control terminals B and C of the switching circuit 2 via 15 and 16.

In the sample / hold circuit thus configured, the pulse control currents IA and IB supplied via the first and second current mirror circuits 15 and 16 are represented by the following equation (7). IA = IB = (VA−2VBE) / R3> IREF (7) where VA is a pulse control voltage of the pulse control voltage source 13,
VBE is a base-emitter voltage of the transistors Q3 and Q4. In this embodiment, the same operation and effect as those of the first embodiment can be obtained.

FIG. 3 is a circuit diagram showing a third embodiment of the sample and hold circuit according to the present invention. In this embodiment, the resistors R1 and R2 constituting the first and second level shift circuits in the second embodiment are replaced with diodes D5 and D6, and the pulse control current in the second embodiment is changed. The voltage-current conversion circuit to be generated is composed of resistors R4, R5, R6, R7 and capacitors C2, C3.
And first and second pulse control voltage sources 17 and 18, and the first and second current mirror circuits are specifically formed by transistors Q5 and Q6 and transistors Q7 and Q
8. The same operation and effect as in the first embodiment can be obtained in the sample and hold circuit configured as described above.

[0018]

As described above with reference to the embodiments, according to the present invention, it is possible to eliminate a phase error in switching timing due to an output voltage and to provide a sample-hold circuit having good input / output characteristics at the time of sample-hold. Can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram showing a first embodiment of a sample hold circuit according to the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit configuration diagram showing a third embodiment of the present invention.

FIG. 4 is a circuit configuration diagram showing a configuration example of a conventional sample and hold circuit.

FIG. 5 is an operation explanatory diagram for explaining the operation of the conventional example shown in FIG. 4;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input signal 2 Switching circuit 3 1st reference current source 4 1st reference voltage source 5 2nd reference current source 6 2nd reference voltage source 7 1st level shift circuit 8 2nd level shift circuit 9 high Input impedance buffer amplifier 10 Output terminal 11 First pulse control current source 12 Second pulse control current source 13 Pulse control voltage source 14 Voltage-current conversion circuit 15 First current mirror circuit 16 Second current mirror circuit 17 First Pulse control voltage source 18 Second pulse control voltage source

Claims (1)

[Claims] 1. A switching circuit comprising a bridge-connected diode, a first pulse control current source connected to a common anode side as a first control input terminal of the switching circuit, and a second pulse control current source of the switching circuit. A second pulse control current source connected to the common cathode, which is a control input terminal, and a first pulse control current source connected to a first control input terminal of the switching circuit.
A first reference voltage source connected via a second reference current source via a second reference current source to a second control input terminal of the switching circuit; A first transistor having an emitter connected to a first control input terminal of the switching device via a first level shift circuit, a collector connected to the first reference voltage source, and a base connected to an output terminal; A second transistor having an emitter connected to a second control input terminal of the circuit via a second level shift circuit, a collector connected to the second reference voltage source, and a base connected to an output terminal; A voltage holding capacitor connected to the output terminal of the switching circuit, and a high input impedance buffer amplifier connected between the output terminal and the output terminal of the switching circuit;
A sample-and-hold circuit, wherein an input terminal of the switching circuit is an input terminal of an input signal.