JP3768595B2 - Sample hold circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a sample and hold circuit, and more particularly to a sample and hold circuit suitable for video equipment such as an electronic still camera.
[0002]
[Prior art]
The sample and hold circuit is a circuit that takes out (sampling) the amplitude value of the input analog signal at a specified time, and outputs the held signal while holding (holding) it for a required time. The sample hold circuit is used in, for example, a circuit in front of an AD converter that digitizes an analog signal and a correlated double sampling circuit (CDS circuit) that is a signal readout circuit of a solid-state imaging device using a CCD.
[0003]
In the sample and hold circuit, a capacitor is used to hold the output signal constant during the hold period, and the capacitor is charged and discharged during the sampling period. In this way, the output signal of the sample and hold circuit is maintained at a constant value during the hold period.
[0004]
Incidentally, as a sample hold circuit for the purpose of reducing noise generated when switching between the sampling mode and the hold mode and increasing the sampling operation speed, the sample hold circuit described in Japanese Patent Publication No. 6-46519 is disclosed. is there. Hereinafter, a sample and hold circuit according to this prior art will be described with reference to FIG.
[0005]
In this circuit, the transistors Q1, Q2, Q3, and Q4 operate as a single buffer as a whole, and during sampling, all of the transistors Q1, Q2, Q3, and Q4 are in a conductive state (ON, that is, the transistor A state in which a voltage in the forward direction and a predetermined value or more is applied between the base and the emitter). At this time, an input signal VIN from a CCD (Charge Coupled Device) or the like is faithfully output as an output VOUT as it is. The hold capacitor C is charged / discharged by the voltage VOUT. A method for making all of the transistors Q1, Q2, Q3, and Q4 conductive will be described later.
[0006]
When holding, all transistors Q1, Q2, Q3, Q4 are in non-conducting state (off, that is, a reverse voltage or a voltage that is forward but less than a predetermined value is applied between the base and emitter of the transistor) State). In particular, since the transistors Q3 and Q4 are off, the charge stored in the hold capacitor C is not discharged through the transistors Q3 and Q4, and the voltage of the hold capacitor C is maintained. A method for turning off all the transistors Q1, Q2, Q3, and Q4 will be described later.
[0007]
In addition, a push-pull circuit is configured by the transistors Q3 and Q4, so that a large current output can be taken out with a small bias current, so this circuit has low power consumption. Furthermore, for reasons described later, this circuit can operate at high speed during sampling.
[0008]
Transistors Q5, Q6, Q7, and Q8 are circuits for turning on transistors Q1, Q2, Q3, and Q4 during sampling and turning them off during holding. In the following, we will first explain the operation of transistors Q1, Q2, Q3, Q4, and then how transistors Q5, Q6, Q7, Q8 turn on / off transistors Q1, Q2, Q3, Q4 Will be described.
[0009]
During sampling, transistors Q1, Q2, Q3, and Q4 are all conducting. Then, transistors having different conductivity types are combined so that the input signal VIN is faithfully output to the signal line VOUT. That is, transistors Q1 and Q2, transistors Q1 and Q3, and transistors Q2 and Q4 have different conductivity types. Here, the different conductivity types means that one transistor is a PNP transistor and the other transistor is an NPN transistor. The hold capacitor C is charged / discharged according to the signal voltage VOUT.
[0010]
The reason why high speed operation is possible during sampling will be described. The hold capacitor charges and discharges according to the magnitude relationship between the voltage VOUT of the hold capacitor C at the start of sampling (the input voltage VIN at the previous sampling) and the input voltage VIN at the time of the current sampling. That is, when the voltage VOUT of the hold capacitor C at the start of sampling is smaller than the input voltage VIN at the time of this sampling, the hold capacitor C is charged by the transistor Q3. Conversely, when the voltage VOUT of the hold capacitor C at the start of sampling is larger than the input voltage VIN at the time of the current sampling, the hold capacitor C is discharged by the transistor Q4. This discharge current flows directly from the collector of the transistor Q4 to the ground (earth). In this circuit, since no circuit element such as a transistor or a resistance element is provided between the collector of the transistor Q4 and the ground, the discharge current is not limited and the discharge is performed at high speed. Therefore, sampling is performed at high speed.
[0011]
Next, the operation of the transistors Q5, Q6, Q7, Q8 will be described. Transistors Q5, Q6, Q7, and Q8 are transistors for turning on / off the transistors Q1, Q2, Q3, and Q4. Constant voltages VB1 and VB2 from constant voltage sources VB1 and VB2 are applied to the bases of the transistors Q5 and Q6, respectively.
[0012]
Transistors Q5 and Q6 are turned on only during holding (the method of turning on will be described later). When turned on, the voltages at points 600 and 602 in FIG. The size shown on the left side.
[0013]
The voltages VB1 and VB2 of the constant voltage sources VB1 and VB2 are set as follows.
[0014]
[Expression 1]
VINMIN ≧ VB1-VBE
[0015]
[Expression 2]
VB2 + VBE ≧ VINMAX
Here, the maximum voltage and minimum voltage of the input signal VIN are VINMAX, VINMIN, and the base-emitter forward voltage drop when the transistors Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8 are conducting is VBE. It is said. Since the change range of the output signal VOUT voltage is the same as the change range of the input signal VIN voltage, VOUTMAX = VINMAX, VOUTMIN = VINMIN when the maximum voltage and the minimum voltage of the output signal VIN are VOUTMAX and VOUTMIN. is there.
[0016]
The reason why the transistors Q1, Q2, Q3, and Q4 are turned off when the constant voltages VB1 and VB2 are set as described above will be described. The right side of Equation 1 indicates the voltage at point 600 shown in FIG. Since the base voltage of the transistor Q1 and the emitter voltage of the transistor Q3 are always higher than VINMIN (= VOUTMIN), the voltage in the reverse direction is applied between the base and emitter of the transistors Q1 and Q3 from Equation 1 when holding. Thus, the transistors Q1 and Q3 are turned off.
[0017]
The left side of Equation 2 indicates the voltage at the point 602 shown in FIG. Since the base voltage of the transistor Q2 and the emitter voltage of the transistor Q4 are always lower than VINMAX (= VOUTMAX), the voltage in the reverse direction is applied between the base and emitter of the transistors Q2 and Q4 according to Equation 2 when holding. Thus, the transistors Q2 and Q4 are turned off.
[0018]
When holding, transistors Q5, Q6 are used to turn off transistors Q1, Q2, Q3, Q4 as described above, but at the time of sampling, transistors Q1, Q2, Q3 are turned off by turning off transistors Q5, Q6. The transistors Q1, Q2, Q3, and Q4 are all turned on by applying a forward voltage between the base and emitter of Q4. Next, a method for turning on / off the transistors Q5 and Q6 will be described.
[0019]
Transistors Q7 and Q8 constituting a differential circuit are used to turn on / off the transistors Q5 and Q6. Clock signals CK1 and CK2 are input to the bases of the transistors Q7 and Q8, respectively. At the time of holding, the clock signal CK1 is a high level signal, and the clock signal CK2 is a low level signal. At the time of sampling, the clock signal CK1 is a low level signal, and the clock signal CK2 is a high level signal.
[0020]
As a result, at the time of holding, the transistor Q7 is on and the transistor Q8 is off. At the time of sampling, the transistor Q7 is off and the transistor Q8 is off. Note that when the high-level signal voltage is VC1, the voltage VC1 is set so as to satisfy the following condition for the reason described later.
[0021]
[Equation 3]
VB1 ≧ VC1 + VBE
The reason why the transistors Q5 and Q6 are turned on during holding will be described. At the time of holding, the transistor Q7 is turned on as described above. At this time, the emitter voltage of the transistor Q1 is equal to or higher than VINMIN + VBE, the base voltage of the transistor Q7 is VC1, and from Equations 1 and 3, since VINMIN + VBE ≧ VC1, the transistor Q1 is turned off.
[0022]
Further, the transistor Q5 is turned on. The reason for this will be explained. The base voltage of transistor Q5 is VB1. The emitter voltage of transistor Q5 is equal to the collector voltage of transistor Q7, and the collector voltage of transistor Q7 is considered to be approximately equal to the base voltage of transistor Q7 (= VC1), so the emitter voltage of transistor Q5 is the base voltage of transistor Q7. Is considered to be almost equal. Therefore, the base-emitter voltage of the transistor Q5 is VB1-VC1, but from Equation 3, VB1-VC1 ≧ VBE, and a voltage is applied in the forward direction between the base and emitter of the transistor Q5, and Since the magnitude of the voltage is equal to or greater than the forward voltage drop between the base and the emitter, the transistor Q5 is turned on.
[0023]
Since the transistor Q8 is turned off as described above, the transistor Q6 is turned on by the constant current source 604.
[0024]
Next, the reason why the transistors Q5 and Q6 are turned off during sampling will be described. At the time of sampling, the transistor Q7 is turned off as described above, and the transistor Q1 is turned on by the constant current source 606. At this time, the emitter voltage of the transistor Q1 is VINMIN + VBE. From FIG. 5, since the emitter voltage of the transistor Q1 is equal to the emitter voltage of the transistor Q5, the emitter voltage of the transistor Q5 is higher than the base voltage VB1 of the transistor Q5 from Equation 1. Accordingly, since a reverse voltage is applied between the base and emitter of the transistor Q5, the transistor Q5 is turned off.
[0025]
At the time of sampling, the transistor Q8 is turned on as described above, but at this time, the transistor Q6 is turned off. This is because the emitter voltage of the transistor Q6 needs to be equal to or higher than VR + VBE in order for the transistor Q6 to be on, but the emitter voltage of the transistor Q6 is lower than VR + VBE at the time of sampling. This will be explained.
[0026]
From FIG. 5, it is considered that the emitter voltage of the transistor Q6 is equal to the collector voltage of the transistor Q8, and the collector voltage of the transistor Q8 is substantially equal to the base voltage VC1 of the transistor Q8. Therefore, when comparing the emitter voltage of the transistor Q6, that is, the base voltage VC1 of the transistor Q8 with VR + VBE,
From Equation 2, VR + VBE ≧ VINMAX ≧ VINMIN,
From Equation 1, VINMIN ≧ VB-VBE,
From Equation 3, VB-VBE ≧ VC1.
As a result, VR + VBE ≧ VC1, and it can be seen that the emitter voltage of the transistor Q6 is lower than VR + VBE during sampling.
[0027]
[Problems to be solved by the invention]
In the sample and hold circuit according to the prior art shown in FIG. 5, a differential circuit comprising transistors Q7 and Q8 is used. In this differential circuit, in order to perform switching at high speed, transistors Q7 and Q8 are not connected. It is necessary to operate in saturation. Non-saturated state means that the voltage between the collector and base of the transistor is in the reverse direction.
[0028]
Considering that the base voltage of transistor Q8 that is turned on during sampling is VC1 and that the voltage drop between the base and emitter of transistor Q2 is VBE, the input signal VIN is , VIN ≧ VC1 + VBE must be satisfied.
[0029]
The base voltage VC1 of the transistor Q8 is normally about 1.5V, and it is difficult to lower it. Since VBE is about 0.75V, the lower limit of the input signal VIN that can be processed is about 2.25V in the case of the circuit according to the prior art.
[0030]
An object of the present invention is to solve such drawbacks of the prior art and to provide a sample-and-hold circuit that can handle an input signal at a high speed and a relatively low voltage, that is, has a wide dynamic range.
[0031]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, the present invention samples an input signal, holds the sampled signal for a predetermined time, and outputs the held signal in which emitters are connected to each other. After a pair of complementary drive transistors, a signal hold capacitor connected to the emitters of the pair of drive transistors, and a signal level of the input signal are converted by an emitter follower, one base of the drive transistors is A first input transistor that outputs a signal after conversion, the first input transistor having a conduction type different from the conduction type of the first input transistor and the one of the driving transistor is input. After converting the signal level of the signal by the emitter follower, A second input transistor that outputs a signal after conversion to the other base, the second input transistor being different from the conduction type of the second input transistor and the conduction type of the other driving transistor A first control transistor having the same conductivity type as that of the first input transistor, the emitter of the first control transistor being connected to the emitter of the first input transistor, A first control transistor for inputting a first control signal for controlling on / off of the first input transistor to the base of the first control transistor via the control transistor; and a second input transistor A second control transistor having the same conductivity type as that of the second input transistor, the emitter of the second control transistor being the emitter of the second input transistor. A second control transistor that is connected to the second control transistor and that controls the on / off of the second input transistor via the second control transistor, and is input to the base of the second control transistor; And a control circuit for outputting the first and second control signals. When the input signal is sampled by the control signal, the first and second input transistors are turned on, and the input signal During holding, the first and second input transistors are turned off, and the magnitude relationship between the voltage of the first control signal and the voltage of the second control signal is reversed between sampling and holding. Is.
[0032]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of a sample and hold circuit according to the present invention will now be described in detail with reference to the accompanying drawings. FIG. 1 shows a circuit diagram of a first embodiment of a sample and hold circuit 10 according to the present invention. The sample and hold circuit 10 of the first embodiment is a circuit that receives a signal VIN output from a CCD or the like, charges and discharges the hold capacitor C during sampling, and maintains the voltage of the hold capacitor C during holding.
[0033]
The input signal VIN branches in two, and one of the branched signals is input to the base of the PNP transistor Q1. The other of the branched signals is input to the base of NPN transistor Q2. During sampling, the transistors Q1 and Q2 convert the input signal VIN by an emitter follower and then output it to the bases of the transistors Q3 and Q4 via the signal lines 100 and 102, respectively. Hereinafter, the signal line and the signal flowing through the signal line are referred to by the same reference symbol.
[0034]
The emitters of a pair of complementary transistors Q3 and Q4 are connected by a signal line 104. Here, the transistor Q3 is an NPN transistor, and the transistor Q4 is a PNP transistor.
[0035]
The transistor Q1, Q2, Q3, Q4 connected in this way is called a diamond buffer. A hold capacitor C is connected to an emitter which is a common output terminal of the pair of transistors Q3 and Q4.
[0036]
The emitter of the transistor Q1 is connected to the emitter of a PNP transistor Q9 having the same conductivity type as that of the transistor Q1. The emitter of the transistor Q2 is connected to the emitter of an NPN transistor Q10 having the same conductivity type as that of the transistor Q2.
[0037]
A control pulse 106 for controlling on / off of the transistor Q1 is input to the base of the transistor Q9 via the transistor Q9. A control pulse 108 for controlling on / off of the transistor Q2 is input to the base of the transistor Q10 via the transistor Q10.
[0038]
Although details will be described later, the transistors Q1 and Q2 are turned on by the control pulses 106 and 108 during sampling, and the transistors Q1 and Q2 are turned off during holding. The magnitude relationship between the voltage of the control pulse 106 and the voltage of the control pulse 108 is reversed between sampling and holding.
[0039]
The control pulses 106 and 108 are generated by a control circuit including resistors 12 and 14 and transistors Q7 and Q8 constituting a differential circuit. The resistance values of the resistors 12 and 14 are RL, and a constant voltage VB is applied to the resistors 12 and 14. The clock signal CK1 is input to the transistor Q7, and the clock signal CK2 is input to the transistor Q8. The emitter of the transistor Q7 is connected to the emitter of the transistor Q8, and these emitters are biased by a constant current source IC1 (current value is IC). The clock signals CK1 and CK2 are generated by the clock circuit 18.
[0040]
The constant current source IA1 shown in FIG. 1 is for setting the bias currents of the transistors Q1 and Q9, and the constant current source IB1 is for setting the bias currents of the transistors Q2 and Q10. The output buffer 20 is for taking out the voltage held in the hold capacitor C. In order to prevent the voltage drop of the hold capacitor C during the hold period, the input impedance of the output buffer 20 is set large. The output impedance of the output buffer 20 is set small. A power supply voltage VCC is supplied to the entire sample and hold circuit 10.
[0041]
Next, the operation of this circuit will be described. First, an outline of the operation will be described. In this circuit, the transistors Q1, Q2, Q3, and Q4 operate as one buffer as a whole, and all of the transistors Q1, Q2, Q3, and Q4 are in a conducting state during sampling. At this time, the input signal VIN from the CCD or the like is faithfully output as the output voltage VOUT as it is. The hold capacitor C is charged / discharged by the output voltage VOUT.
[0042]
During hold, all transistors Q1, Q2, Q3, and Q4 are off. In particular, since the transistors Q3 and Q4 are off, the charge stored in the hold capacitor C is not discharged through the transistors Q3 and Q4, and the voltage of the hold capacitor C is maintained.
[0043]
Further, similarly to the prior art shown in FIG. 5, a push-pull circuit is constituted by the transistors Q3 and Q4, so that this circuit has low power consumption. Furthermore, for the reason described for the circuit shown in FIG. 5, this circuit can operate at high speed during sampling.
[0044]
Transistors Q9 and Q10 receive control pulses 106 and 108, turn on transistors Q1, Q2, Q3, and Q4 during sampling, and turn them off during holding.
[0045]
Next, details of the operation of the circuit 10 will be described. The following describes the operation of transistors Q1, Q2, Q3, Q4 during sampling and holding first, and then how transistors Q7, Q8, Q9, Q10 are Whether to turn on / off will be described.
[0046]
During sampling, transistors Q1, Q2, Q3, and Q4 are all conducting. Then, transistors having different conductivity types are combined so that the input signal VIN is faithfully output to the signal line VOUT. That is, transistors Q1 and Q2, transistors Q1 and Q3, and transistors Q2 and Q4 have different conductivity types. The hold capacitor C is charged / discharged according to the signal voltage VOUT.
[0047]
Next, operations of the transistors Q7, Q8, Q9, and Q10 will be described. Transistors Q7, Q8, Q9, and Q10 are transistors for turning on / off the transistors Q1, Q2, Q3, and Q4. Of the transistors Q7, Q8, Q9, Q10, the transistors Q9, Q10 receive the control pulses 106, 108 and turn on / off the transistors Q1, Q2, Q3, Q4. Transistors Q7 and Q8 generate control pulses 106 and 108.
[0048]
First, how the transistors Q1, Q2, Q3, Q4 are turned on / off by the transistors Q9, Q10 and the control pulses 106, 108 will be described. The voltages of the control pulses 106 and 108 are the voltages at the points VP and VN shown in FIG. 1 and will be described in detail later. Is as follows.
[0049]
When sampling,
[0050]
[Expression 4]
VP = VB
[0051]
[Equation 5]
VN = VB-RL × IC
During hold,
[0052]
[Formula 6]
VP = VB-RL × IC
[0053]
[Expression 7]
VN = VB
And these voltages are when the minimum value of the voltage of the input signal VIN is VIL and the maximum value is VIH.
[0054]
[Equation 8]
VB> VIH
[0055]
[Equation 9]
VIL> VB-RL × IC
The constant voltage VB, the resistor RL, and the constant current source IC1 are set so that
[0056]
At the time of sampling, the base voltage of the transistor Q9 is higher than the base voltage of the transistor Q1 from the equations (4) and (8), so that the transistor Q1 is on and the transistor Q9 is off. The reason for this will be described. The bases and emitters of the transistors Q1 and Q9 each constitute a diode. In the diode, when the anodes of the two diodes are connected to each other (with a common potential) and different potentials are applied to the cathodes of the two diodes in the forward direction, the diodes to which a low potential is applied Is turned on, and a diode to which a high potential is applied is turned off.
[0057]
From Equations 5 and 9, since the base voltage of the transistor Q10 is lower than the base voltage of the transistor Q2, the transistor Q2 is on and the transistor Q10 is off. The reason for this will be described. The bases and emitters of the transistors Q2 and Q10 each constitute a diode. In the diode, when the cathodes of the two diodes are connected to each other (with a common potential) and different voltages are applied to the anodes of the two diodes in the forward direction, the diode to which a high potential is applied Is turned on, and a diode to which a low potential is applied is turned off.
[0058]
In holding, since the base voltage of the transistor Q9 is lower than the base voltage of the transistor Q1 from Equations 6 and 9, the transistor Q9 is on and the transistor Q1 is off. Further, from Equations 7 and 8, since the base voltage of the transistor Q10 is higher than the base voltage of the transistor Q2, the transistor Q10 is on and the transistor Q2 is off.
[0059]
The on / off states of the transistors Q3 and Q4 are the same as the on / off states of the transistors Q1 and Q2. This is because the minimum and maximum values of the voltage of the output signal VOUT are the same as the minimum and maximum values of the voltage of the input signal VIN, and the emitter of the transistor Q9 and the base of the transistor Q3 are connected ( Since the anodes of the diodes are connected), the transistor Q3 is turned on / off in the same manner as the transistor Q1. For the same reason, transistor Q4 is turned on / off in the same manner as transistor Q2.
[0060]
Regarding the transistors Q3 and Q4 when the sample mode is switched to the hold mode, the transistors Q3 and Q4 are turned off for the following reason. When switching from sample mode to hold mode, the voltages at points VN and VP first change to the voltages shown in equations 6 and 7. At that time, the emitter voltages (= output voltage VOUT) of the transistors Q3 and Q4 are the last input voltage VIN during the sampling period. Therefore, since the emitter voltage of the transistors Q3 and Q4 at the time of switching is any value between the minimum value and the maximum value of the voltage of the input signal VIN, the transistors Q3 and Q4 are transistors Q3 and Q4 in the hold mode. And the transistors Q3 and Q4 are turned off.
[0061]
Next, a method for generating the control pulses 106 and 108 will be described. The control pulses 106 and 108 are generated by the resistors 12 and 14 and the transistors Q7 and Q8 constituting the differential circuit. The clock signal CK1 is input to the transistor Q7, and the clock signal CK2 is input to the transistor Q8. At the time of sampling, the clock signal CK1 is a high level (voltage = VC1) signal, and the clock signal CK2 is a low level (voltage = VC2) signal. At the time of holding, the clock signal CK1 is a low level (voltage = VC2) signal, and the clock signal CK2 is a high level (voltage = VC1) signal. The timing of the clock signals CK1 and CK2 is shown in FIG. In FIG. 2, the sampling period is indicated by S, and the hold period is indicated by H. 2A shows the timing of the clock signals CK1 and CK2 of the sample and hold circuit according to the prior art shown in FIG.
[0062]
Since the clock signals CK1 and CK2 are set in this way, the transistor Q7 is on and the transistor Q8 is off during sampling. The collector current (current value is IC) of the transistor Q7 flows through the resistor 12. As a result, the voltage at the point VN becomes a voltage VB-IC × RL that is a voltage drop of IC × RL from VB. On the other hand, since no current flows through the resistor 14, the voltage at the point VP is VB. In this way, the control pulses 106 and 108 having the voltages shown in the above-described equations 4 and 5 are generated. Then, the transistors Q1, Q2, Q3, and Q4 are turned on by the control pulses 106 and 108 as described above.
[0063]
Conversely, when holding, the transistor Q7 is off and the transistor Q8 is on. The collector current (current value is IC) of the transistor Q8 flows through the resistor 14. As a result, the voltage at the point VP becomes a voltage VB-IC × RL that is a voltage drop of IC × RL from VB. On the other hand, since no current flows through the resistor 12, the voltage at the point VN is VB. In this way, the control pulses 106 and 108 having the voltages shown in the above-described equations 6 and 7 are generated. The control pulses 106 and 108 turn off the transistors Q1, Q2, Q3, and Q4 as described above.
[0064]
This is the end of the description of the operation of the first embodiment. In this embodiment, the transistors Q7 and Q8 must be operated in a non-saturated state in order to perform the switching operation of the transistors Q7 and Q8, which are differential circuits, at high speed. Since the base voltage of the transistor Q7 that is turned on during sampling and the base voltage of the transistor Q8 that is turned on during holding is VC1, the collector voltage of the transistors Q7 and Q8, that is, the points VN and VP Always between the voltage and the voltage VC1
[0065]
[Expression 10]
VN> VC1, VP> VC1
It is sufficient if the relationship is established.
[0066]
Since the minimum values of voltages VN and VP are VB-IC × RL from Equations 4, 5, 6, and 7,
[0067]
[Expression 11]
VB-IC × RL> VC1
It is sufficient if the relationship is established.
[0068]
In this case, considering “VIL> VB-IC × RL” in Equation 9,
[0069]
[Expression 12]
VIL> VC1
It becomes. Compared with the case of FIG. 5 related to the prior art, the input voltage range is widened by VBE.
[0070]
In FIG. 1, a resistor 16 is provided between the emitters of the transistors Q3 and Q4 and the hold capacitor C. The resistor 16 and the hold capacitor C constitute a low pass filter. This filter cuts high frequency noise. The purpose of cutting the high-frequency component is that the high-frequency component is sampled and held, so that the high-frequency component is folded back to the low-frequency region where the signal to be held exists.
[0071]
The resistance value of the resistor 16 is determined in consideration of the fact that the voltage of the hold capacitor C quickly reaches VIN during sampling and that the high-frequency component that is noise can be sufficiently cut. That is, the smaller the resistance value, the smaller the time constant of the low-pass filter, and the voltage of the hold capacitor C quickly reaches VIN. On the other hand, the cut-off frequency increases as the resistance value decreases. Therefore, the resistance value is determined in consideration of the balance between the two.
[0072]
Note that the addition of the resistor 16 does not affect the voltage of the hold capacitor C when the hold capacitor C reaches a steady voltage during sampling. This is because when the hold capacitor C reaches a steady voltage, no charge / discharge current flows through the hold capacitor C and no current flows through the resistor 16, and the voltage drop due to the resistor 16 is "0 volts".
[0073]
Here, a sample hold circuit obtained by modifying the sample hold circuit of FIG. 5 according to the prior art is shown in FIG. 3, and the circuit shown in FIG. 3 is compared with the sample hold circuit of the first embodiment. In FIG. 3, the same circuit elements as those in FIGS. 1 and 5 are denoted by the same reference numerals, and detailed description thereof is omitted.
[0074]
In this circuit, constant current sources IA2, IB2, and IC2 and constant voltage sources VB3 and VB4 are set as IA2 <IC2, IB2 <IC2, and VB3 <VB4. The clock signals CK1 and CK2 are input to the transistors Q7 and Q8, respectively. At the time of sampling, the clock signal CK1 is low level (VC2) and the clock signal CK2 is high level (VC1). At the time of holding, the clock signal CK1 is high level (VC1) and the clock signal CK2 is low level (VC2).
[0075]
Transistors Q1, Q2, Q3, and Q4 are on during sampling and off during holding.
[0076]
During sampling, transistor Q7 is off and transistor Q8 is on. The transistor Q1 is biased by the constant current source IA2 and is turned on. As for the transistor Q2, by setting VB4 + VBE> VC1 for the voltage VB4 of the constant voltage source VB4, the transistor Q6 is turned off and the transistor Q2 is turned on. Transistor Q2 is biased by the collector current IC2 of transistor Q8.
[0077]
With respect to the transistors Q3 and Q4, forward voltages are applied between the bases and emitters of the transistors Q3 and Q4, so that the transistors Q3 and Q4 are turned on. Therefore, the input signal VIN appears at the emitters of the transistors Q3 and Q4, and charges and discharges the hold capacitor C according to the input signal VIN.
[0078]
During hold, transistor Q7 is on and transistor Q8 is off. As for the transistor Q1, by setting VIL + VBE>VB3-VBE> VC1, the transistor Q1 is turned off and the transistor Q5 is turned on. The collector current IC2 of the transistor Q7 absorbs the current IA2 and supplies a bias current to the transistor Q5.
[0079]
As for the transistor Q2, the transistor Q6 is biased to be turned on by the constant current IB2, and the transistor Q2 is turned off by setting VINMAX−VBE <VB4 + VBE and the voltage VB4. Since VB3 <VB4 is set, the transistors Q3 and Q4 are turned off. As a result, the input signal VIN is held in the hold capacitor C.
[0080]
Also in the sample and hold circuit shown in FIG. 3, in order to switch the transistors Q7 and Q8 at high speed, the transistors Q7 and Q8 must be operated in a non-saturated state. Since the base voltage of the transistor Q8 at the time of sampling is VC1, the input signal VIN is limited by VIN> VC1 + VBE. Accordingly, the input signal range is narrowed by VBE compared to the first embodiment.
[0081]
Next, a second embodiment of the sample and hold circuit according to the present invention will be described. FIG. 4 shows a sample and hold circuit 30 according to the second embodiment. This embodiment is characterized in that the voltage of the control pulse is changed according to the voltage of the output signal VOUT. In the following description, the same circuit elements as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.
[0082]
During sampling, the transistors Q1 and Q2 are turned on by the control pulses 116 and 118, and when held, the transistors Q1 and Q2 are turned off. The magnitude relationship between the voltage of the control pulse 116 and the voltage of the control pulse 118 is reversed between sampling and holding.
[0083]
Control pulses 116, 118 are generated by a control circuit. The control circuit includes resistors 32 and 34, transistors Q7 and Q8 constituting a differential circuit, and transistors Q11 and Q13 and a resistor 36 constituting a circuit for feeding back the output voltage VOUT. The resistance values of the resistors 32 and 34 are RL1. The resistance value RL1 is determined as follows.
[0084]
Transistors Q1-Q4, Q9, Q10 have the same characteristics, and the forward voltage drop between these bases and emitters is almost the same voltage VSW regardless of transistors Q1-Q4, Q9, Q10. To do. VSW is usually around 0.7 volts. The current value of the constant current source IC3 is IC3. At this time,
[0085]
[Formula 13]
VSW = IC3 × RL1
Determine the resistance value RL1 so that
[0086]
A voltage VB1 is applied to the resistors 32 and 34. The voltage VB1 is
[0087]
[Expression 14]
VB1 = VOUT + (VSW / 2)
It becomes. That is, the voltage VB1 changes according to the output voltage VOUT, but is always higher than the output voltage VOUT by VSW / 2. A method for generating the voltage VB1 will be described. The output signal VOUT is output to the outside of the sample hold circuit 30 through the buffer 20, and is fed back through the transistor Q13, the resistor 36, and the transistor Q11 in this order. A constant current ID flows through the resistor 36, and the resistance value RF and current value ID of the resistor 36 are
[0088]
[Expression 15]
RF × ID = VSW / 2
It is decided to become.
[0089]
The transistor Q13 is provided to cancel out the voltage drop between the base and emitter of the transistor Q11. Therefore, the characteristics of the transistor Q13 and the characteristics of the transistor Q11 are aligned, and the voltage drop between the base and emitter of the transistor Q13 is equal to the voltage drop between the base and emitter of the transistor Q11. As described above, the voltage shown in Equation 14 is obtained.
[0090]
The clock signal CK1 is input to the transistor Q7, and the clock signal CK2 is input to the transistor Q8. The emitter of the transistor Q7 is connected to the emitter of the transistor Q8, and these emitters are biased by a constant current source IC3 (current value is IC3). The clock signals CK1 and CK2 are generated by the clock circuit 18.
[0091]
Next, the operation of this circuit will be described. In this circuit, the transistors Q1, Q2, Q3, and Q4 operate as one buffer as a whole, and all of the transistors Q1, Q2, Q3, and Q4 are in a conducting state during sampling. At this time, the input signal VIN from the CCD or the like is faithfully output as the output VOUT as it is. The hold capacitor C is charged / discharged by the voltage VOUT. During hold, all transistors Q1, Q2, Q3, and Q4 are off.
[0092]
Next, operations of the transistors Q7, Q8, Q9, and Q10 will be described. Transistors Q7, Q8, Q9, and Q10 are transistors for turning on / off the transistors Q1, Q2, Q3, and Q4. Of the transistors Q7, Q8, Q9, Q10, the transistors Q9, Q10 receive the control pulses 116, 118 and turn on / off the transistors Q1, Q2, Q3, Q4. Transistors Q7 and Q8 generate control pulses 116 and 118.
[0093]
First, how the transistors Q1, Q2, Q3, Q4 are turned on / off by the transistors Q9, Q10 and the control pulses 116, 118 will be described. The voltages of the control pulses 116 and 118 are the voltages at the points VP and VN shown in FIG. 4. Although details will be described later, the voltages at the points VP and VN (referred to as VP and VN, respectively) are the first embodiment. Is as follows.
[0094]
When sampling,
[0095]
[Expression 16]
VP = VB1 = VOUT + (VSW / 2)
[0096]
[Expression 17]
VN = VB1-RL1 × IC3 = VOUT- (VSW / 2)
During hold,
[0097]
[Formula 18]
VP = VB1-RL1 × IC3 = VOUT- (VSW / 2)
[0098]
[Equation 19]
VN = VB1 = VOUT + (VSW / 2)
And these voltages are relative to the voltage VIN of the input signal VIN.
[0099]
[Expression 20]
VB1 = VOUT + (VSW / 2)> VIN
[0100]
[Expression 21]
VIN> VB1-RL1 × IC3 = VOUT- (VSW / 2)
It becomes. This is because the input voltage VIN and the output voltage VOUT are considered to be substantially equal.
[0101]
However, there are cases where equations 20 and 21 do not hold. When shifting from the hold mode to the sampling mode, the input voltage VIN becomes larger than the voltage of the hold capacitor C (= VOUT: the voltage of the input signal VIN in the previous sampling period), and the difference is VSW / 2 ( = VBE / 2). However, it is rare that the input voltage changes more than VSW / 2 (= VBE / 2) during a short period of one hold period. Therefore, it is considered that Equations 20 and 21 are usually established.
[0102]
At the time of sampling, since the base voltage of the transistor Q9 is higher than the base voltage of the transistor Q1 from Equations 16 and 20, the transistor Q1 is on and the transistor Q9 is off. The reason for this is as described for the first embodiment.
[0103]
Since the base voltage of the transistor Q10 is lower than the base voltage of the transistor Q2 from Equations 17 and 21, the transistor Q2 is on and the transistor Q10 is off. The reason for this is also as described for the first embodiment.
[0104]
At the time of holding, since the base voltage of the transistor Q9 is lower than the base voltage of the transistor Q1 from Equations 18 and 21, the transistor Q9 is on and the transistor Q1 is off. Also, since the base voltage of the transistor Q10 is higher than the base voltage of the transistor Q2 from Equations 19 and 20, the transistor Q10 is on and the transistor Q2 is off.
[0105]
The on / off states of the transistors Q3 and Q4 are the same as the on / off states of the transistors Q1 and Q2. This is because the emitter voltage of the transistors Q3 and Q4 is the emitter voltage = the output signal VOUT, and the output voltage VOUT is clearly an expression corresponding to the above formulas 20 and 21;
[0106]
[Expression 22]
VB1 = VOUT + (VSW / 2)> VOUT
[0107]
[Expression 23]
VOUT> VB1-RL1 × IC3 = VOUT- (VSW / 2)
This is because Therefore, the above description for the transistors Q1 and Q2 is valid for the transistors Q3 and Q4. That is, the transistor Q3 is turned on / off similarly to the transistor Q1. Similarly, the transistor Q4 is turned on / off in the same manner as the transistor Q2.
[0108]
Next, a method for generating the control pulses 116 and 118 will be described. The control pulses 116 and 118 are generated by the resistors 32 and 34 and the transistors Q7 and Q8 constituting the differential circuit. The clock signal CK1 is input to the transistor Q7, and the clock signal CK2 is input to the transistor Q8. At the time of sampling, the clock signal CK1 is a high level (voltage = VC1) signal, and the clock signal CK2 is a low level (voltage = VC2) signal. At the time of holding, the clock signal CK1 is a low level (voltage = VC2) signal, and the clock signal CK2 is a high level (voltage = VC1) signal. The timing of the clock signals CK1 and CK2 is as shown in FIG.
[0109]
As a result, at the time of sampling, the transistor Q7 is on and the transistor Q8 is off. The collector current (current value is IC3) of the transistor Q7 flows through the resistor 32. As a result, the voltage at point VN is the voltage VB1-IC3 x RL1 that is a voltage drop from VB1 by IC3 x RL1. On the other hand, since no current flows through the resistor 34, the voltage at the point VP is VB1. In this way, the control pulses 116 and 118 having the voltages shown in the aforementioned equations 16 and 17 are generated. The transistors Q1, Q2, Q3, and Q4 are turned on by the control pulses 116 and 118 as described above.
[0110]
Conversely, when holding, the transistor Q7 is off and the transistor Q8 is on. The collector current of transistor Q8 (current value is IC3) flows through resistor 34. As a result, the voltage at point VP is the voltage VB1-IC3 x RL1 that is a voltage drop from VB1 by IC3 x RL1. On the other hand, since no current flows through the resistor 32, the voltage at the point VN is VB1. In this way, the control pulses 116 and 118 having the voltages shown in the above-described equations 18 and 19 are generated. Then, as described above, the transistors Q1, Q2, Q3, and Q4 are turned off by the control pulses 116 and 118.
[0111]
In FIG. 4, a resistor 16 is provided between the emitters of the transistors Q3 and Q4 and the hold capacitor C. The resistor 16 and the hold capacitor C constitute a low pass filter.
[0112]
Further, the transistor Q12 in FIG. 4 is a start-up circuit at power-on. Without the transistor Q12, when the power is turned on, no charge is accumulated in the hold capacitor C, so the output signal VOUT is a signal at the GND level. For this reason, VB1 is set lower than the normal voltage, and it is always in the hold state regardless of the values of the clock signals CK1 and CK2.
[0113]
This is because the voltage at the point VP is considerably lower than the input signal VIN, so that the transistor Q1 is turned off, and a voltage 0.7 volts higher than the point VP is applied to the base of the transistor Q3. This is considered to be considerably lower than the input voltage VIN. On the other hand, the transistor Q2 is turned on, and a voltage lower than the input signal VIN by the voltage drop VBE between the base and emitter of the transistor Q2 is input to the base of the transistor Q4. As a result, the base voltage of the transistor Q4 becomes higher than the base voltage of the transistor Q3, and the transistors Q3 and Q4 are turned off.
[0114]
The transistor Q12 serves as a limiter, and VB1 can be prevented from becoming lower than a predetermined voltage by appropriately setting the constant voltage VS applied to the base of the transistor Q12.
[0115]
This is the end of the description of the operation of the second embodiment. In this embodiment, the transistors Q7 and Q8 must be operated in a non-saturated state in order to perform the switching operation of the transistors Q7 and Q8, which are differential circuits, at high speed. Since the base voltage of the transistor Q7 that is turned on during sampling and the base voltage of the transistor Q8 that is turned on during holding is VC1, the collector voltage of the transistors Q7 and Q8, that is, the points VN and VP Always between the voltage and the voltage VC1
[0116]
[Expression 24]
VN> VC1, VP> VC1
It is sufficient if the relationship is established.
[0117]
Since the minimum values of the voltages VN and VP are VB1-IC3 x RL1 from Equations 16, 17, 18, and 19,
[0118]
[Expression 25]
VB1-IC3 × RL1> VC1
As long as the relationship is always established.
[0119]
At this time
[0120]
[Equation 26]
VIN> VOUT- (VSW / 2) = VB1-IC3 × RL1 (= Equation 21)
VSW ≒ VBE
VIN = VOUT
Considering
[0121]
[Expression 27]
VIN> VC1 + (VBE / 2)
It becomes. Compared to the case of FIG. 5 related to the prior art, the input voltage range is widened by (VBE / 2).
[0122]
In the case of the second embodiment, when shifting from the sample mode to the hold mode, less noise is generated due to the difference between the timing when the transistor Q9 changes from OFF to ON and the timing when the transistor Q10 changes from OFF to ON. . The reason why noise occurs when the timing deviation is large is as follows.
[0123]
At the time of sampling, after the hold capacitor C is charged / discharged to a voltage equal to the input voltage, the emitter current IE3 of the transistor Q3 becomes equal to the emitter current IE4 of the transistor Q4, and no charge / discharge current flows through the hold capacitor C. . After that, when shifting to the hold mode, if the timing when the transistor Q9 changes from OFF to ON and the timing when the transistor Q10 changes from OFF to ON, the timing when the transistor Q3 changes from ON to OFF and the transistor Q4 changes from ON to OFF. The timing to change is shifted. The emitter current (IE3 or IE4) of the transistor that was turned off later charges / discharges the hold capacitor C for the time DT, and the charge of IE3 × DT is charged, or the charge of IE4 × DT Will be discharged.
[0124]
In the case of the second embodiment, the reason why the noise is low is that the timing deviation is small. The reason for the small timing deviation is that the base voltages of the transistors Q9 and Q10 change symmetrically around the output voltage VOUT, and the base voltages of the transistors Q9 and Q10 are output when the transistors Q9 and Q10 are turned on. This is because the transistors Q9 and Q10 are turned on almost at the same time because the voltage VOUT is reached.
[0125]
In the first embodiment, the timing deviation may be small or large. This is because when switching from the sampling mode to the hold mode, the voltage at the intermediate point of the base voltage change of the transistors Q9 and Q10 is not always equal to the input voltage VIN, so that the transistors Q9 and Q10 are turned on almost simultaneously. It is not limited.
[0126]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a sample-and-hold circuit having a wide voltage range (dynamic range) of an input signal and a high speed.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a first embodiment of a sample and hold circuit according to the present invention.
FIG. 2 is a timing chart showing the operation timing of the sample and hold circuit shown in FIG. 1 in comparison with the operation timing of the sample and hold circuit according to the prior art.
FIG. 3 is a circuit diagram of a sample and hold circuit obtained by changing the sample and hold circuit according to the prior art.
FIG. 4 is a circuit diagram of a second embodiment of the sample and hold circuit according to the present invention.
FIG. 5 is a circuit diagram of a sample and hold circuit according to the prior art.
[Explanation of symbols]
10 Sample hold circuit
12, 14, 16, 32, 34, 36 resistance
106, 108, 116, 118 Control pulse
CK1, CK2 clock signal
Q1-Q13 transistors

Claims (3)

In a sample and hold circuit that samples an input signal, holds the sampled signal for a predetermined time, and outputs the held signal, the circuit includes:
A pair of complementary drive transistors with their emitters connected,
A signal hold capacitor connected to the emitters of the pair of drive transistors;
A first input transistor that outputs a converted signal to one of the drive transistors after the signal level of the input signal is converted by an emitter follower, the first input transistor A first input transistor different from the conduction type and the conduction type of the one drive transistor;
A second input transistor that outputs the converted signal to the other base of the drive transistors after the signal level of the input signal is converted by an emitter follower; A second input transistor different from the conduction type and the conduction type of the other drive transistor;
A first control transistor having the same conductivity type as that of the first input transistor, the emitter of the first control transistor being connected to the emitter of the first input transistor; A first control transistor for inputting a first control signal for controlling on / off of the first input transistor to the base of the first control transistor via one control transistor;
A second control transistor having the same conductivity type as that of the second input transistor, the emitter of the second control transistor being connected to the emitter of the second input transistor; A second control transistor in which a second control signal for controlling on / off of the second input transistor is input to the base of the second control transistor via two control transistors;
A control circuit for outputting the first and second control signals;
According to the control signal, the first and second input transistors are turned on when the input signal is sampled, and the first and second input transistors are turned off when the input signal is held. become,
The sample-and-hold circuit, wherein the magnitude relationship between the voltage of the first control signal and the voltage of the second control pulse is reversed between sampling and holding. 2. The sample and hold circuit according to claim 1, wherein voltages of the first and second control signals change in accordance with an output voltage of the drive transistor. 3. The sample hold circuit according to claim 2, wherein a difference obtained by subtracting the output voltage of the drive transistor from the voltage of the first control signal subtracts the voltage of the second control signal from the output voltage of the drive transistor. A sample and hold circuit characterized in that the difference and the sign are equal.

Images