JPH0646287A - Video signal feedback clamp circuit - Google Patents

Abstract

PURPOSE:To attain the video signal clamp circuit giving always an accurate and constant DC component to a video signal having no DC component. CONSTITUTION:A subtractor circuit 12 detects an error between a pedestal level of a digital video signal subjected to AD conversion and a specified pedestal level, the obtained error and a corrected potential before a prescribed period of time are added by an adder circuit 13 to obtain a newly corrected potential, which is converted into an analog value by a D/A converter 16, and the analog input video signal is corrected by the newly corrected potential obtained as above-mentioned by a differential amplifier 9. Thus, an accurate clamp voltage is obtained by correcting the dispersion in the characteristics of an A/D converter 10 and the differential amplifier 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal clamp circuit for applying a constant DC component to a video signal having no DC component in a video device.

[0002]

2. Description of the Related Art In recent years, in video equipment, there are increasing opportunities to digitize video signals and handle them as digital signals. When a video signal is digitized and recorded and transmitted, it is necessary to reproduce an accurate DC component having a small error from a video signal having no DC component.

A conventional video signal clamp circuit will be described below with reference to the drawings. FIG. 3 is a block diagram of an example of a conventional video signal clamp circuit, and FIG. 4 is a signal waveform diagram showing its operation. As shown in FIG. 3, 1 is an amplifier, 2 is a clamp pulse generating circuit, 3 is a capacitor, 4 is a resistor, 5 is a switch, 6 is an amplifier, and 7 is a component.
Is an AD converter, and 8 is a reference potential generating circuit.

First, the input video signal having no DC component is amplified by the amplifier 1. The amplified video signal having no DC component is clamp pulse generation circuit 2
And the capacitor 3 are input. When the video signal having no DC component is input to the clamp pulse generation circuit 2, the clamp pulse generation circuit 2 generates a clamp pulse (signal A in FIG. 4A). When the clamp pulse is generated, the switch 5 is closed only during the clamp pulse period shown by the signal A in FIG. When the switch 5 is closed, the capacitor 3 is charged through the resistor 4 by the potential of the reference potential generating circuit 8, the potential at point P in FIG. 3 is fixed to the reference potential, and the DC component of the video signal having no DC component is fixed. It Next, the video signal with the fixed DC component is amplified by the amplifier 6, input to the AD converter 7, digitized, and output.

[0005]

However, in the above configuration, when the switch 5 is closed and the capacitor 3 is charged, the charging current of the capacitor 3 has a time constant due to the resistor 4 and the capacitor 3, so that the capacitor 3 is During the clamp pulse period, the battery cannot be fully charged, the potential at the point P in FIG. 3 changes, an error from the reference potential occurs, and an error from the value that should be originally fixed occurs. (Error shown in signal B of FIG. 4B) Further, similar error occurs even when the characteristics of the amplifier 6 and the AD converter 7 vary or change over time.

As described above, the conventional video signal clamp circuit has a problem that it is not possible to reproduce a highly accurate DC component with a small error. The present invention has been made in view of the above problems, and provides a video signal feedback clamp circuit capable of reproducing a video signal having a high-precision DC component with a small error from a video signal having no DC component. Is.

[0007]

In order to solve the above problems, a video signal feedback clamp circuit according to the present invention provides a differential amplifier for clamping an input video signal to a correction potential and a clamped video signal. An AD converter for digitization, a subtraction circuit for extracting a pedestal level from the clamped video signal and detecting an error from a specified pedestal level, and an addition of the detected error and the correction potential to rewrite the correction potential. It is characterized in that it comprises an adder circuit and a DA converter for analogizing the rewritten new correction potential, and feeds back the rewritten new correction potential to the differential amplifier.

[0008]

In the video signal feedback clamp circuit having the above structure, the correction potential of one horizontal line before is subtracted from the input video signal during the horizontal blanking period of the input video signal. Then, the clamped video signal is clamped, the clamped video signal is digitized by the AD converter, the pedestal level is extracted from the output signal of the AD converter, and the error from the specified pedestal level is obtained. The calculated error is added to the correction potential one horizontal line before to obtain the current correction potential, and the obtained current correction potential is analogized by the DA converter, and during the video signal period of the input video signal, The current correction potential is subtracted from the video signal to reproduce a video signal having a DC component. As a result, the error from the set value is constantly corrected and the new correction potential is used as the current correction potential, so that stable and accurate reproduction of the direct current component can be performed without being affected by variations in characteristics.

[0009]

EXAMPLES Examples of the present invention will be described in detail below. FIG. 1 shows a block diagram in an embodiment of the present invention. FIG. 2 is a signal waveform diagram showing the operation in the embodiment of the present invention. As shown in FIG. 1, as components, 9 is a differential amplifier, 10 is an AD converter, 11 is a first register, 12 is a subtraction circuit, 13 is an addition circuit, 14 is a second register, and 15 is a timing generation circuit. , 16 is DA
It is a converter.

The operation of the video signal feedback clamp circuit configured as described above will be described. The input video signal has no DC component. First, the input video signal having no DC component is input to the differential amplifier 9. The video signal having no DC component input in the differential amplifier 9 is clamped to the signal output from the DA converter 16 (that is, the correction potential) and output.

The clamped video signal is input to the AD converter 10, digitized and output in two directions.
One is output as it is, the other is output to the first register 1
Input to 1. When the clamped video signal is input to the first register 11, a clamp timing signal (a signal input from the timing generation circuit 15 to the first register 11) corresponding to the pedestal timing of the input video signal is input. The pedestal level of the input video signal is extracted, held and output by the signal B) of FIG. 2B.

Next, the output pedestal level is input to the subtraction circuit 12, and the specified pedestal level is subtracted from the pedestal level. The subtraction result of the subtraction circuit 12 becomes error data between the pedestal level of the input video signal and the specified pedestal level (the set value in FIG. 1). Next, this error data is input to the adder circuit 13, added to the correction potential input to the differential amplifier 9, and a new correction potential is output. At this time, when the output from the adder circuit 13 overflows, the maximum value is
If it is negative, a zero value is output.

The new correction potential output from the adder circuit 13 is input to the second register 14 and is delayed from the clamp timing signal (signal B in FIG. 2B) and in the horizontal blanking period. A set signal generated at a timing once (a signal input to the second register 14 from the timing generating circuit 15 is shown in FIG. 2C).
It is rewritten by the signal C) and is held for one horizontal period. That is, the correction potential output from the second register 14 is rewritten every time the clamp timing signal is generated. The new correction potential output from the second register 14 is analogized by the DA converter 16 and input to the differential amplifier 9, and the input video signal having no DC component is converted into a new correction potential. Clamped.

[0014]

As is apparent from the above description, the video signal feedback clamp circuit of the present invention detects an error between the DC component of the clamped video signal and the set value, and corrects the detected error before a predetermined period. By adding to the potential to obtain a new correction potential and subtracting the obtained new correction potential, a video signal having an accurate DC component with a small error is generated.
It is possible to reproduce without increasing the accuracy (bit number) of the D converter itself. Further, even if the characteristics of the AD converter or the amplifier vary or change over time, it is possible to reproduce a video signal having a constant DC component with high accuracy and little error.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a video signal feedback clamp circuit of the present invention.

2A, 2B and 2C are signal waveform diagrams showing the operation of the embodiment.

FIG. 3 is a block diagram of a video signal clamp circuit in a conventional example.

4A and 4B are signal waveform diagrams of a video signal clamp circuit in a conventional example.

[Explanation of symbols]

 9 Differential Amplifier 10 AD Converter 11 First Register 12 Subtraction Circuit 13 Addition Circuit 14 Second Register 15 Timing Generation Circuit 16 DA Converter

Claims (1)

[Claims] 1. A differential amplifier for subtracting a correction potential from an analog input video signal, an AD converter for receiving and digitizing an output signal of the differential amplifier, and a pedestal for a digital video signal output from the AD converter. A first register for extracting and holding a video signal at a timing corresponding to, a subtracting circuit for subtracting a specified pedestal level value from the value held by the first register to detect an error, and an output from the subtracting circuit The added error value and the correction potential to output a new correction potential, a second register for holding the new correction potential, and the new register output from the second register. A DA converter for converting the correction potential into an analog signal, wherein the differential amplifier uses the analogized new correction potential as the correction potential. Video signal feedback clamping circuit so as to subtract from the signal