JPS61173591A - Dc level reproduction system - Google Patents

Abstract

PURPOSE:To reproduce a DC level with invariably high precision regardless of a signal waveform by making a specific waveform part which appears a every constant period of a video signal constant in DC level and determining the DC level. CONSTITUTION:The signal level of the video signal (VID) inputted in synchronism with the 1st timing signal (ta) is sampled and held by a sample holding capacitor 15 and outputted from a voltage amplifier 16. The signal sampled and held by this 1st sample holding circuit (SH-1) is inputted to an arithmetic circuit 23 together with the signal sampled and held by the 3rd sample holding circuit (SH-3) and compared. The voltage level of a constant-period horizontal synchronizing signal contained in the inputted video signal (VID) is prevented through the operation of the arithmetic circuit from deviating from a set potential even if the waveform varies.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a DC level reproduction method suitable for use in digitally converting an analog image signal.

[Technical background of the invention and its problems] Conventionally, when determining the DC level of an AC-coupled analog signal during analog-to-digital conversion, a C level regeneration circuit as shown in FIG. It was used. The operation of this circuit is such that the voltage at point A becomes the center level of the signal, and for the signal p, the center level (A)
The areas of the plus side and minus side of are equal. However, in the circuit described above, the peak value (pe
akt.

Even if the peak) voltage is the same, for example, in Figure 2 (a)
, or as shown in (b), when the waveforms are different, it is not determined at which position in the waveform the center level (DC level) will be. In other words, in the case of signals with the same peak open circuit voltage but different waveforms, the highest potential of the signal,
The lowest potentials cannot be made equal.

Therefore, in the conventional DC level reproduction circuit described above,
There was a drawback that the DC level could not be faithfully reproduced regardless of the signal waveform.

In particular, when converting an AC-coupled NTSC video signal to digital using an A/D converter, the DC
If the level cannot be reproduced, the capabilities (number of bits, precision) of the A/D converter cannot be fully utilized.

[Object of the Invention] The present invention was made in view of the above-mentioned circumstances, and an object of the present invention is to provide a DC level reproduction method that can always reproduce the DC level faithfully regardless of the waveform of the signal.

[Summary of the Invention] The present invention provides a method for converting image signals, such as NTSC video signals, to DC
When reproducing the level, focus on a specific part of the video signal (for example, the horizontal synchronizing signal part), keep the voltage level of that part constant, and set it as the reference DC of the video signal.
level. That is, the DC level is determined by assuming that a specific waveform portion of the video signal that is observed at regular intervals is constant in terms of DC. As a result, the DC level can always be reproduced with high accuracy regardless of the signal waveform, and accurate C reproduction is possible when converting an AC-coupled NTSC video signal into digital with an A/D converter.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. Third
The figure is a circuit block diagram showing one embodiment of the present invention. In the figure, 11 is a video amplifier circuit that amplifies the NTSC video signal (VID), 12 is a coupling capacitor, and 13 is a buffer for converting the input impedance of the DC level reproduction circuit. It is a circuit. 14 to 16 each form a component of the first sample hold circuit (SH-1);
4 is an analog switch turned on by a first timing signal (ta) synchronized with the horizontal synchronization signal of the video signal (VID), 15 is a sample hold capacitor, and 16 is a voltage amplifier (operational amplifier) for compensating the sample voltage. be.

17 to 19 are respectively second sample and hold circuits (
17 is an analog switch turned on by a second timing signal (tb> delayed by 1/n period from the first timing signal (ta)), and 18 is a sample hold. Capacitor 19 is a voltage amplifier for sample voltage compensation.

20 to 22 are third sample and hold circuits (
20 is an analog switch turned on by a third timing signal (tc) delayed by 1/n period from the second timing signal (tb), and 21 is a sample hold. A capacitor 22 is a voltage amplifier for sample voltage compensation.

23 is a new video signal (Vr
D> is received at the negative side input terminal, and the signal sampled and held by the third sample and hold circuit (SH-3) is received at the positive side input terminal, and the third sample and hold circuit (SH-3)
The signal level sampled and held by the first sample and hold circuit (SH-1) is compared with the signal level newly sampled and held by the first sample and hold circuit (SH-1), and the output signal is sent to the second sample and hold circuit (SH-2). This is an arithmetic circuit that supplies As described above, this arithmetic circuit 23 receives at its negative input terminal the signal sampled and held by the first sample and hold circuit (SH-1), and receives the signal sampled and held by the third sample and hold circuit (SH-3). Since the signal is received at the positive input terminal, its output will decrease if the signal from the first sample and hold circuit (SH-1) is higher than the signal from the third sample and hold circuit (SH-3). On the other hand, if it is low, it works to raise it.

R1 is a resistance element for feeding back the output of the second sample and hold circuit (SH-2) to the first sample and hold circuit (SH-1).

24 is a synchronization detection circuit that detects a horizontal/vertical synchronization signal (H-V) from the video signal (VID) supplied to the video amplifier circuit 11; 25 is a fourth synchronization detection circuit based on the output of this synchronization detection circuit 23; First to third timing signals (ta, tb) as shown in FIGS. (b) to (d).

This is a timing generation circuit that generates tC).

FIG. 4 is a diagram showing the signal timing of each part in the above embodiment, in which (a) shows the video signal (VID) input to the video amplifier circuit 11, and (b) shows the first sample. The first timing signal (ta) supplied to the analog switch 14 of the hold circuit (SH-1>, same figure (C))
is the second timing signal (tb) supplied to the analog switch 11 of the second sample and hold circuit (SH-2).
), Figure (d) shows the third sample hold circuit (SH-
3) is the third timing signal (tc) supplied to the analog switch 20, and H in FIG. 3(a) is a horizontal synchronization signal.

Here, the operation of one embodiment will be explained with reference to the third factor and FIG. 4. FIG. 4 (
The video signal (VID) shown in a) is the video signal (VID) shown in the video amplifier circuit 1.
After analog amplification with 1, coupling capacitor 1
2 to the input impedance conversion buffer circuit 13 of the DC level reproduction circuit. Video signal (VID) impedance-converted by this buffer circuit 13
is supplied to the analog switch 14 of the first sample and hold circuit (SH-1). The analog switch 14 is
FIG. 4 (1) generated by the timing generation circuit 25)
The switch is turned on in synchronization with the first timing signal ((a) shown in FIG. 1), and the input video signal (VID) is applied to the sample-hold capacitor 15. As a result, the signal level of the video signal (VID) input in synchronization with the first timing signal (ta) is sampled and held by the sample-hold capacitor 15,
It is output from the voltage amplifier 16.

The signal sampled and held by the first sample and hold circuit (SH-1) is inputted to the arithmetic circuit 23 together with the signal sampled and held by the third sample and hold circuit (SH-3), and subjected to a comparison operation. The comparison operation of the arithmetic circuit 23 at this time will be described later.

The signal output from the arithmetic circuit 23 is supplied to the analog switch 17 of the second sample hold circuit (SH-2). The switch is turned on in synchronization with the second timing signal (tb) shown in FIG. The signal level is sampled and held by the sample-and-hold capacitor 18 and output from the voltage amplifier 19.

The signal sampled and held in the second sample and hold circuit (SH-2) is passed through the resistance element R1 and the buffer circuit 13 to the first sample and hold circuit (SH-1).
The signal is fed back to the analog switch 20 of the third sample and hold circuit (SH-3).

The analog switch 20 receives a third timing signal (shown in FIG. 4(d)) generated by the timing generation circuit 25.
tc), the switch is turned on, and the input signal is applied to the sample-hold capacitor 21. As a result, the signal level of the signal input in synchronization with the third timing signal (tc) is sampled and held by the sample-and-hold capacitor 21, and is output from the voltage amplifier 22.

The signal sampled and held by the third sample and hold circuit (SH-3) is supplied to the arithmetic circuit 23 together with the signal newly sampled and held by the first sample and hold circuit (SH-1), as described above. Ru.

The operation of this arithmetic circuit 23 will be explained. The first sample and hold circuit (SH-1) receives the first timing signal (ta).
) sampled and held by the nth signal (n
th horizontal synchronization signal) voltage Vn.

If the voltage of the n-1st signal (horizontal synchronizing signal before the nth 10) is V n-1, and the output of the arithmetic circuit 23 after calculation at V n-1 is f (Vn-1). ,n
Output f (Vn) of the arithmetic circuit 23 by the th operation
is f (Vn) = - (k-Vadd -B2-Vn-m-f (Vn-1>) - (1)
(However, k, R, and m are determined by R2-R6).

First, V add is set to determine the voltage level of the horizontal synchronizing signal (H) shown in FIG. 4(a). Here, it is the output of the voltage amplifier 19 that directly controls the voltage level.

As is clear from the above equation (1), as Vn increases, f
(Vn) decreases, which is fed back through resistance element R1 and is controlled to lower the voltage level. or,
When Vn decreases, the operation described above is also reversed. Through this operation, the input video signal (VI
The voltage level of the constant period horizontal synchronizing signal (H) included in D) does not deviate from the set potential even if the waveform changes, and accurate DC level reproduction is always performed.

Therefore, when an A/D converter converts an AC-coupled NTSC video signal to digital, the DC level is accurately reproduced, making full use of the A/D converter's capabilities and improving fidelity. This enables A/D conversion of high-quality video signals.

In the above-described embodiment, the horizontal synchronization signal was sampled, but the present invention is not limited to this, and other specific signals having a constant period may be sampled.

Further, in the above embodiments, an NTSC video signal is taken as an example of an image signal, but the image signal is not limited to this, and for example, a PAL video signal can be used.
It is also possible to use a video signal of the same method.

[Effects of the Invention] As detailed above, according to the DC level reproduction method of the present invention, it is possible to always reproduce the DC level with high precision and fidelity regardless of the signal waveform. A conversion mechanism can be easily realized.

[Brief explanation of the drawing]

The first cause and Figures 2 (a) and (b) are respectively the conventional D
This is for explaining the C level reproducing means, and FIG. 1 shows the circuit cause, and FIGS. 2(a) and 2(b) show signal waveform diagrams. The third factor and FIGS. 4(a) to 4(d) are for explaining one embodiment of the present invention, respectively. FIG. 3 is a circuit block diagram showing the configuration of one embodiment, and FIG. (a)-(d
) are time charts showing signals of each part in one embodiment. 11... Video amplifier circuit, 12... Coupling capacitor, 13... Buffer circuit, 14.17.20
... Analog switch, 15.18.21 ... Sample hold capacitor, 16.19.22 ... Voltage amplifier, 23 ... Arithmetic circuit, 24 ... Synchronization detection circuit, 25 ... Timing generation Circuit, 5H-1, 8H-2
, 5H-3... Sample hold circuit. Applicant's agent Patent attorney Takehiko Suzue 1st WJ ◆V

Claims (1)

[Claims] In a circuit that reproduces a DC level of an image signal, a first circuit that samples the specific signal using a first timing signal synchronized with a specific signal of a constant period included in the image signal.
a second sample and hold circuit that samples an input signal using a second timing signal that is delayed by a certain period from the first timing signal; a third sample-and-hold circuit that samples the signal held in the second sample-and-hold circuit using a third timing signal, and a signal held in the third sample-and-hold circuit and the first sample-and-hold circuit; and an arithmetic circuit that compares and computes the newly sampled and held signal with the signal newly sampled and held, and supplies the output to the second sample and hold circuit, and always uses the specific signal as a reference DC level to compare the current specific signal with the previous specific signal. A DC level reproduction method characterized in that the DC level of the image signal is determined by comparing the DC level with a specific signal of the image signal.