JPH06349289A - Nonvolatile semiconductor circuit - Google Patents

Abstract

(57) [Summary] [Construction] MOS transistors 1 and 2 are formed in parallel with a plurality of memory cells connected between a data line and a source line of a memory array in which nonvolatile semiconductor memory cells are arranged in a matrix. , When pulling out electrons, M
The source line or the data line is charged through the OS transistors 1 and 2. [Effect] It is possible to prevent the threshold voltage variation of the non-selected memory cell in the electron extraction operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device having an electric write / erase function, and more particularly to a non-volatile semiconductor circuit having improved data retention characteristics.

[0002]

2. Description of the Related Art Conventionally, as a non-volatile semiconductor memory device, for example, a memory device called an NOR type flash memory of electrical batch erasing type has been developed as disclosed in Japanese Patent Laid-Open No. 3-219496. The conventional NOR flash memory has been constructed by arranging memory cells having a floating gate field effect transistor structure in a matrix. Here, the control gates of the respective memory cells whose drain terminals are directly connected to the data lines are connected to different word lines, and the source terminals of all the memory cells are directly connected to a common source line.

Erasure of memory cell data is performed in units of word lines. A negative voltage is applied to the control gate of the memory cell to open the data line and a positive voltage is applied to the source terminal. At this time, a high electric field is applied to the gate oxide film on the source terminal side of the memory cell, and electrons accumulated in the floating gate are extracted to the source terminal by the Fowler-Nordheim tunnel phenomenon. As a result, the threshold voltage of the memory cell becomes low,
Erase operation is completed.

The positive voltage applied to the source line in the erase operation is also applied to the source terminals of non-selected memory cells other than the memory cell selected in response to the erase command. In a non-selected memory cell, a weak electric field is applied to the gate oxide film from the floating gate in the direction of the source terminal, causing a disturb phenomenon relating to the source terminal in which electrons accumulated in the floating gate gradually escape. Therefore, it has been necessary to apply a positive voltage to the control gates of the non-selected memory cells in order to prevent the threshold voltage from decreasing due to the emission of electrons.

[0005]

When the erase operation is performed, different positive voltages are applied to the control gate and the source terminal of the non-selected memory cell, so that the non-selected memory cell is turned on and the non-selected memory cell is turned on. A charging current for charging the capacitance of the drain line flows from the source terminal to the drain terminal via the. In addition, since the positive voltage applied to the source terminal becomes 0V even after the erasing operation is completed, a discharge current that causes the charge accumulated in the drain line to be discharged to the source terminal side through the non-selected memory cell flows. Hot electrons are generated in the non-selected memory cells by the charge / discharge current, and electrons are injected into the floating gate. There has been a problem that the amount of hot electrons injected increases in proportion to the number of erases and the threshold voltage increases.

Regardless of the erase operation, generally, in the operation of extracting electrons from the floating gate using the diffusion layer end of the source terminal or the drain terminal of the memory cell, a positive voltage may be applied to the control gate of the non-selected memory cell. This is necessary, and as the number of times of programming and erasing increases, the amount of hot electrons injected increases and the threshold voltage increases.

[0007]

In order to solve the above problems, the present invention has the following circuit configuration and system.

For example, as shown in FIG. 1, in a memory array in which nonvolatile semiconductor memory cells having floating gates are arranged in a matrix, a plurality of memories arranged in parallel between a data line and a source line. A cell and a MOS transistor arranged in parallel with those memory cells are provided, and each data line is connected to the source line via the MOS transistor.

Further, in the operation of extracting electrons from the floating gate of the memory cell, a positive voltage is applied to the source line in advance, a positive voltage is applied to the gate of the MOS transistor, and the MOS transistor is turned on.
The voltage of the drain terminal is made substantially equal to the voltage of the source terminal. After that, a positive voltage for disturb prevention with respect to the source terminal is applied to the control gate of the non-selected memory cell, and a negative voltage is applied to the control gate of the selected memory cell to extract electrons from the floating gate.

On the other hand, after the extraction operation is completed, first, the voltage of the control gate of the selected memory cell is set to 0V, the voltage of the control gate of the non-selected memory cell is set to 0V, and then the voltage of the source is set to 0V and the drain is set. The charge charged on the line is extracted to the source line side, and the voltage on the drain line side is set to about 0.
V. Further, the voltage of the gate of the MOS transistors inserted in parallel is set to 0V, and the drain region is electrically separated from the source region.

[0011]

According to the present invention, before the operation of extracting electrons from the floating gate is started, the MO connected in parallel to the memory cell is
The drain terminal and the source terminal of the non-selected memory cell are set to substantially the same voltage by the S transistor. Therefore, when a positive voltage is applied to the control gate of the unselected memory cell, a transient current does not flow through the unselected memory cell even when the threshold voltage of the unselected memory cell is low. As a result, generation of hot electrons in the non-selected memory cell is suppressed, and electron injection into the floating gate does not occur.

Further, even when the operation of extracting electrons from the floating gate is completed, first, the voltage of the control gates of the selected memory cell and the non-selected memory cell is returned to 0V, so that the drain terminal and the source terminal are maintained at substantially the same voltage. Since it is in the open state, a transient current does not flow through the non-selected memory cell. After that, the source terminal voltage is set to 0V, and the accumulated charge of the drain terminal is discharged through the MOS transistor, and then the gate voltage of the MOS transistor is set to 0V.
Return to.

As described above, since the drain terminal is charged and discharged through the MOS transistor provided in parallel with the memory cell, hot electron injection does not occur in the memory cell and the threshold voltage does not change. .

[0014]

EXAMPLE A first example of the present invention will be described with reference to FIG. FIG. 1 shows a circuit configuration of a nonvolatile semiconductor memory cell. Here, NO is used as the nonvolatile semiconductor memory cell.
Although an R-type memory cell is used and a word line for 2 bits and a data line for 2 bits are shown, the memory cell and arrangement are not limited to this.

Memory cell M1 connected to data line D1
The control gates of M1 and M21 are different word lines W1 and W
2 and the source terminals are memory cells M12 and M22.
Connected to the common source line together with the source terminal of. The n-type MOS transistors 1 and 2 are arranged in parallel with the memory cell between the data line and the source line, and the gates of the n-type MOS transistors 1 and 2 are connected to a common control line SG. Each data line is connected to the peripheral circuit 3 of the decoder and the sense amplifier, and each word line is connected to the decoder 4. In the NOR type memory cell, data writing is performed by hot electron injection at the drain end, and erasing is performed by tunnel emission of electrons from the source terminal side in word line units.

An example of the voltage relationship of the control line SG at the time of rewriting and reading the data of the memory cell M11 and the timing at the time of erasing is shown below. When writing data,
The voltage of the data line D1 is set to 5V, for example, and the word line W1 is set to 10V. The common source line is 0V. Here, the control line SG is held at 0V and the MOS transistors 1 and 2 are turned off. A current flows from the data line to the source line through the memory cell M11, and electrons are injected into the memory cell M11 by hot electron injection. In reading, the data line voltage is set to, for example, 1V.
, 5V is applied to the word line W1, and the control line SG is set to 0.
V. The data line voltage fluctuates according to the threshold voltage of the memory cell, and this fluctuation value is read by the sense amplifier.

In the erase operation, a voltage is applied to each signal line according to the voltage timing chart shown in FIG. Word line W
The data in all the memory cells connected to 1 can be erased collectively. The data lines D1 and D2 are opened on the decoder side, and a voltage of about 5 V is applied to the source line. Applying 5V to the control line SG at about the same time,
The data lines D1 and D2 are charged through the S transistors 1 and 2. After each data line is charged, for example, 5V is applied to the word line W2 relating to the non-selected memory cell, and -8V is applied to the word line W1. Regarding M11 and M12,
The word lines W1 and W2 are returned to 0V after a lapse of time for discharging electrons from the floating gate to the source terminal side by a tunnel phenomenon. Furthermore, the source terminal is set to 0V, and M
After the electric charge accumulated in the data line via the OS transistors 1 and 2 is extracted to the source line, the control line SG is set to 0V.

A second embodiment of the present invention will be described with reference to FIG. FIG. 3 shows a circuit diagram in the case of using a non-volatile semiconductor memory cell that rewrites data by using the tunnel phenomenon. In this embodiment, erasing is performed by injecting electrons into the floating gate using the tunnel phenomenon of the entire surface of the memory cell, and writing is performed by using the tunnel emission phenomenon of electrons from the floating gate to the diffusion layer on the drain terminal side. To do. Here, the source lines S1 and S2 are separated by a MOS transistor connected to the signal line SS. Similar to the first embodiment, MOS transistors 1 and 2 are arranged in parallel with each memory cell.

An example of the voltage relationship of the control line SG at the time of rewriting and reading the data of the memory cell M11 and the timing at the time of writing is shown below. At the time of erasing data, the voltage of the source lines S1 and S2 is set to 0V, and the word line W1 is set to 15V, for example. Here, the control line SG may be 0V to 5V. Electrons are injected into the floating gates of all the memory cells on the word line W1 from the channel side, and the erased state becomes a high threshold voltage state.
In reading, the data line voltage is set to, for example, 1 V, 5 V is applied to the word line W1, and the control line SG is set to 0 V. Data line voltage D according to the threshold voltage of the memory cell
1 fluctuates, and this fluctuation value is read by the sense amplifier.

FIG. 4 shows a timing chart of the voltage applied to each signal line relating to the write operation. Memory cell M11
When data is written in and the erased state is maintained in M12, 5 lines are input to the data lines D1 and D2 from the decoder side.
Voltages of V and 0V are provided. At this time, SS is set to 0V and the source lines S1 and S2 are opened. Also, S
D is 7V, and the voltage of the data line is applied to the drain terminal of each memory cell. Next, 5V is applied to the control line SG, and MO
The source lines S1 and S2 are charged from the data lines D1 and D2 via the S transistors 1 and 2. After each data line is charged, for example, 5V is applied to the word line Wn relating to the non-selected memory cell, and -8V is applied to the word line W1. M
Regarding 11 and M12, the word lines W1 and Wn are returned to 0V after the time for emitting electrons from the floating gate to the drain terminal side by the tunnel phenomenon has elapsed. Further, the data lines D1 and D2 are set to 0V, the charges accumulated in the data line via the MOS transistors 1 and 2 are extracted to the data line, and finally the control line SG is set to 0V.

In this embodiment, data is written by lowering the threshold voltage of the memory cell by using the tunnel phenomenon between the diffusion layer region on the drain side and the floating gate. Even in this case, as shown in the first embodiment, the voltage of the non-selected word line needs to be set to, for example, 5 V, and the source line is charged through the memory cell connected to the non-selected word line. . At this time, hot electrons generated in the memory cell may be injected into the floating gate, which may cause variation in the threshold voltage. However, as shown in this embodiment, the MOS transistors 1 and 2 are By precharging the source line via the via, it is possible to prevent generation of hot electrons in the memory cell.

A third embodiment of the present invention will be described with reference to FIGS. FIG. 5 shows a sectional view of a memory cell and an outline of its operation. In the second embodiment, the data writing to the memory cell is performed by using the tunnel emission phenomenon of electrons from the floating gate to the diffusion layer on the drain side, but in the present embodiment, the floating gate to the source diffusion layer side is used. It is carried out by using the tunnel emission phenomenon of electrons to the.

That is, as shown in FIG. 4, after receiving the command of the write operation, 5 V is applied to the data line D1 and the control line S is applied.
Add 0V to S and 7V to SD. Here, the drain line in the block is connected to the data line, and the source line is separated from the common source line. Next, 7V is applied to the control line SG, and the voltage on the drain side of the memory cell appears on the source line S1 via the MOS transistor 1. Subsequently, −8V is applied to the selected word line and 5V is applied to the non-selected word line. In the memory cell M1 on the selected word line W1, a high electric field is applied between the source terminal and the floating gate.

If the memory cell structure shown in FIG. 5 is adopted, the impurity concentration of the diffusion layer 18 on the source side is made higher than that of the diffusion layer 16 on the drain side by one digit or more, so that the impurity concentration of the diffusion layer 18 on the source side is higher than that of the drain terminal side. Electrons are emitted from the floating gate to the source terminal side in accordance with the tunnel phenomenon, and the threshold voltage of the memory cell becomes low. That is, data writing is performed using the tunnel emission phenomenon of electrons from the floating gate to the source diffusion layer side.

In the present embodiment, since the tunnel emission amount of electrons from the drain terminal side can be suppressed, in the non-volatile memory cell, the charge amount in the floating gate is generally maintained even for continuous data read for 10 years. Fluctuations must be suppressed. However, at the time of reading, a voltage is applied to the data line, and the fluctuation of the voltage is read by a sense amplifier or the like, so a weak electric field is applied between the drain terminal and the floating gate electrode of the memory cell connected to the data line, and the floating gate is gradually increased. The electrons inside are emitted to the drain terminal (disturb phenomenon on the drain terminal side).

In order to suppress the variation of the threshold voltage due to this, the limit of the drain terminal voltage is about 1V in the past. A MOS transistor 1 as shown in this embodiment,
By adding 2 to the circuit, the tunnel emission of electrons from the source terminal side becomes possible, so that the concentration of the diffusion layer on the drain side can be lowered, and the electrons in the floating gate to the drain terminal at the time of reading can be made. It has become possible to suppress the release amount of. As a result, the restriction on the drain terminal voltage is relaxed to about 3V, and the sense amplifier can be easily designed.

A fourth embodiment of the present invention will be described with reference to FIG. The memory cell used in FIG. 6 has the sectional view shown in FIG. The rewriting method similar to that of the third embodiment is adopted. As a result, the influence of the drain disturb phenomenon is alleviated, and the drain terminals of the two memory cells M11 and M12 on the same word line W1 have the common data line D1.
Can be connected to. Here, MOS transistors 1 and 2 are provided for the two source lines S1 and S2.

At the time of writing, when writing data to M11, the MOS transistor 1 is turned on, and when writing data to M12, the MOS transistor 2 is turned on. Further, in order to prevent a malfunction during reading, the source side control line is separated into two SS1 and SS2.

In this embodiment, in addition to the effect shown in the third embodiment, the number of data lines can be reduced, and the effective memory cell area can be reduced.

A fifth embodiment of the present invention will be described with reference to FIG. In this embodiment, each of the source side control lines SS and SG in the fourth embodiment is one. For this reason,
The word lines of the memory cells connected to the source lines S1 and S2 are separated from each other. Also in this embodiment, in addition to the effect shown in the third embodiment, the number of data lines can be reduced, and the effective memory cell area can be reduced.

[0031]

According to the present invention, in the nonvolatile semiconductor memory device in which the threshold voltage of the memory cell is changed by using the tunnel emission phenomenon of electrons between the floating gate electrode and the drain or source diffusion layer, tunnel emission of electrons is performed. Sometimes
The fluctuation of the threshold voltage of the memory cell due to the generation of hot electrons when charging the drain line or the source line via the memory cell on the unselected word line can be suppressed, and the data retention characteristic of the memory cell can be improved.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a configuration of a memory cell according to a first embodiment of the present invention.

FIG. 2 is a timing chart of each signal line in the first embodiment of the present invention.

FIG. 3 is an explanatory diagram showing a configuration of a memory cell according to a second embodiment of the present invention.

FIG. 4 is a timing chart of each signal line in the second embodiment of the present invention.

FIG. 5 is a sectional view of a flash memory cell according to a third embodiment of the present invention.

FIG. 6 is an explanatory diagram showing a configuration of a memory cell according to a fourth embodiment of the present invention.

FIG. 7 is an explanatory diagram showing a configuration of a memory cell according to a fifth embodiment of the present invention.

[Explanation of symbols]

1, ... MOS type transistors, 3 ... Peripheral circuits such as sense amplifiers, 4 ... Decoder circuits.

Claims (4)

[Claims] 1. A plurality of non-volatile memory cells comprising a memory array in which non-volatile semiconductor memory cells capable of electrically writing and erasing a floating gate are arranged in a matrix, and connected between a data line and a source line. A semiconductor memory cell and M connected in parallel to the nonvolatile semiconductor memory cell
A non-volatile semiconductor circuit in which each data line is connected to a source line through an OS transistor. 2. The voltage of the data line and the source line are electrically connected to each other in advance by using the MOS transistor in the operation of extracting electrons from the floating gate of the nonvolatile semiconductor memory cell. Nonvolatile semiconductor circuit. 3. The non-volatile semiconductor memory cell according to claim 1, wherein the non-volatile semiconductor memory cell is connected to the gate of the non-volatile semiconductor memory cell after the completion of the electron withdrawal operation in the non-volatile semiconductor floating gate operation. A non-volatile semiconductor circuit for electrically separating the data line from the source line by turning off the MOS transistor after setting the voltage of the word line to 0V. 4. The voltage of the data line and the source line are electrically connected to each other in advance by using the MOS transistor in the operation of extracting electrons from the floating gate of the nonvolatile semiconductor memory cell according to claim 1. Subsequently, the voltage of the word line connected to the gate of the nonvolatile semiconductor memory cell is set to a predetermined voltage necessary for erasing, and further, after the operation of extracting electrons is completed, the voltage of the word line is set to 0V, and then A non-volatile semiconductor circuit that electrically isolates a data line from a source line by turning off a MOS transistor.