KR20010072189A - Semiconductor device with a non-volatile memory - Google Patents

Abstract

The present invention relates to a semiconductor device having a semiconductor body provided with a programmable electrically electrically erasable non-volatile memory comprising a matrix of memory cells each comprising a field effect transistor having a floating gate. The device according to the invention is characterized in that each memory cell comprises a select transistor T2 connected in series with the floating gate transistor T1 while the write and erase operations are carried out based on the Fowler-Nordheim tunneling mechanism. It forms a matrix of the type and is characterized in that the select transistor is connected to the source of the floating-gate transistor.

Description

Semiconductor device {SEMICONDUCTOR DEVICE WITH A NON-VOLATILE MEMORY}

The present invention relates to a semiconductor device having a semiconductor body provided with a programmable electrically electrically erasable nonvolatile memory portion comprising a matrix of memory cells each comprising a field effect transistor having a floating gate. The main embodiment of such a device is a CMOS circuit manufactured in a standard CMOS process and provided with a buried memory section. Such semiconductor devices are generally well known.

The embedded non-volatile memory portion usually requires high reliability, short access time and low power during write and erase operations. The techniques used to make so-called stand-alone memory sections typically do not fully comply with the requirements imposed on the embedded memory sections. Therefore, for example, flash memory, in which cells are placed in a NOR structure and write and erase is caused by channel hot electron injection (CHEI) and FN tunneling (Fowler-Nordheim tunneling mechanism), is usually over-exhaust ( overerasure). In addition, writing (programming) generally requires a large amount of current. Memory having a NAND structure in which writing and erasing is caused by Fowler-Nordheim tunneling may have important problems in this technique because a high voltage is required for erasing and writing.

It is an object of the present invention, in particular, to provide a non-volatile memory which does not have the above drawbacks and is therefore particularly suitable as an embedded memory. According to the present invention, the semiconductor device type described above in the introduction includes a selection transistor in which each memory cell is connected in series with a floating-gate transistor, while write and erase operations of the memory cells are performed based on the Fowler-Nordheim tunneling mechanism. And the memory cell forms a NOR type matrix, and the select transistor is connected to the source of the floating-gate transistor.

Short access times are possible by using a NOR structure where the cells are not sequential. The problem of over-erasing can be solved by the selection transistor. The use of Fowler-Nordheim for write and erase operations makes it possible to limit the current (power) for write and erase operations. In addition, it is possible to use the entire channel surface area for FN tunneling in that the select transistor is located on the source side of the floating gate transistor. As a result, the FN tunneling mechanism has high efficiency, so even low power is sufficient.

The preferred embodiment includes a p-type surface region adjacent to the surface of the semiconductor body, whereas the transistors in each cell are of the n-channel type, with p-types adjacent to and interposed by the n-type wells. It is characterized in that the transistor is provided in a p-type well insulated from the type surface region.

The use of an insulated p-type well allows for the use of voltages that are both polarized so that the maximum voltage is halved (in absolute), which is particularly important for the total number of write / erase cycles that can be performed. .

These and other aspects of the invention will be described in more detail with reference to the following examples.

1 is an equivalent circuit diagram of a non-volatile memory according to the present invention.

2 is a cross-sectional view of a memory cell of the device of FIG. 1.

1 illustrates a diagram of a nonvolatile, programmable, electrically erasable memory in accordance with the present invention. The device includes a matrix of memory cells arranged in m rows and n columns. The cells in row i are Mi1, Mi2, ... Min, where i is the row number. The cells in column j are equal to M1j, M2j, ... Mnj. As is generally known, each memory cell includes a floating gate transistor T1 in which data can be stored on a floating gate. Subsequently each memory cell includes a second transistor T2 connected in series with T1 to form a select transistor connected to the source of the floating gate transistor T1. The source of the selection transistor T2 is connected to the common junction point 1. The drains of the transistors T1 in the same column are connected to the bit line BLi, where i is the column number. The bit lines BL are connected to means 2 for applying a desired voltage to the selected bit lines. Each floating gate transistor T1 is provided with a control gate connected to the word line Cgi, where i is the row number. Similarly, the gate of the select transistor T2 is connected to the word line Sgi. Lines Sg and Cg are connected to means 3 capable of applying an appropriate voltage to the selected lines.

The memory cell device described herein is referred to in the literature as a NOR structure. Since the read current between the bit line BL and the junction point 1 flows only through the selected cell, a relatively low voltage on the word line may be sufficient, for example, in contrast to a NAND type circuit in which cells of the same column are connected in series. Can be.

2 shows a cross section of a single memory cell. Obviously, the device includes peripheral electronics, not shown, separate from the memory cells shown herein. Additionally, the device may also include logic portions fabricated in standard CMOS processes of embedded applications, although not shown. The silicon semiconductor body also includes a p-type surface region 5 adjacent to the surface 4. The surface area can cover the entire semiconductor body, but this is not necessary. The deep n-type well 6 is provided in the surface region 5, and the deep n-type well is provided with a less deep n-type well provided with n-channel transistors T1, T2. The n-well 6 insulates the p-type well 7 from the p-type substrate 5, so that a voltage different from the voltage applied to the substrate 5, such as a positive voltage, is p-type well 7. And / or a negative voltage may be applied to the bit line. Transistor T2 comprises an n-type source 8, an n-type drain 9 and a gate 10 separated from the channel between the source and the drain by a gate oxide. As shown, the source is connected to junction point 1 and the gate is connected to word line Sg. Transistor T1 includes a source formed by region 9 and an n-type drain 11 connected to bit line BL. A floating gate 12 is provided above the channel, which is electrically insulated from the channel. A control gate 13 is provided above the floating gate, which is electrically insulated from the floating gate and connected to the selection line Cg. In the embodiment of FIG. 2, a control gate 13 is provided to overlap the floating gate 12, whereby a large capacitive coupling between the gates is obtained. Obviously, the gates can be arranged as a stack, so the capacitance between these gates becomes somewhat smaller, but in this case the cell can be made smaller.

See Table 1 below for the operation of the memory.

Record (programming)

Since the low (negative) voltage Vnn (e.g. -5V) is applied to all word lines Sg, the selection transistor is not in a conductive state. In addition, since the low voltage Vnn is applied to the selected bit line, the related drain may temporarily serve as a source. Since a positive voltage Vpp (for example, 5V) is applied to the selected word line Cg, an inversion channel is formed in the transistor T1.

Since the select transistor is not in a conductive state, no current flows through the cell, so no or substantially no power is lost. The maximum voltage is present between the channel and the control gate, which voltage is selected so that electrons are stored in the floating by Fowler-Nordheim tunneling (eg, depending on the oxide thickness and other process parameters). Since charge transport occurs on the entire channel, high efficiency is obtained and the voltage used will be relatively low. As a result, the field strength across the tunnel oxide is also relatively small, and damage to the oxide is limited, which is particularly important for the number of write / erase cycles that can be performed. Since 0V is applied to the non-selected bit line, the voltage across the oxide is so small that no Fowler-Nordheim tunneling occurs in the non-selected cell. During programming, a low voltage Vnn is applied to the p-type well 7 to prevent forward biasing of the pn junction belonging to the selected bit line.

Erasing

A positive voltage Vpp is applied to the p-type well 7 and the n-type well 6 to prevent forward bias of the pn junction between the n-type well and the p-type well. The low voltage Vnn is applied to the selected word line Cg, and 0V is applied to the other word line. The voltage across the gate oxide of the selected cell is high enough for Fowler-Nordheim tunneling, so electrons will tunnel from the floating gate to the substrate 5. The potential of the floating gate is increased and the threshold voltage of the transistor is lowered. As during writing, tunneling occurs on the entire channel surface during erase, so a relatively low voltage can also be used during erase. Using the tunneling mechanism, the power consumption during the erase is very small. Furthermore, since each cell contains a selection transistor, there is no obstacle to erasure at the point where the threshold voltage becomes very low, even below 0V, which is of particular advantage for reading.

Reading

In the case of reading a constant cell, a voltage is applied to the selected word line Cg, which lies between the threshold voltage (high threshold voltage) of the programmed cell and the threshold voltage of the non-programmed cell (low threshold voltage of the erased cell). Then, it is checked whether the floating gate transistor is in a conductive state. The highest available voltage Vdd is applied to the word line Sg of the cell so that the selection transistor is in a conductive state. Since a low read voltage of 0.5V is applied to the selected line and 0V is applied to the non-selected bit line, Vds = 0V in these cells and no current can flow into these cells. Since the threshold voltage of the non-programmed cell is low and the wick may also be less than or equal to 0V as described above, in the embodiment according to the table, a voltage of 1V may be used on the selected word line Cg.

The invention is not limited to the embodiments described herein, and it will be apparent to those skilled in the art that various changes are possible.

Claims (2)

A semiconductor device having a semiconductor body provided on a surface thereof with a programmable electrically electrically erasable non-volatile memory comprising a matrix of memory cells each comprising a field effect transistor having a floating gate. As the writing and erasing of the memory cell is performed based on the Fowler-Nordheim tunneling mechanism, each memory cell includes a select transistor connected in series with a floating-gate transistor, the memory cell forming a NOR type matrix. And the selection transistor is connected to a source of the floating-gate transistor. The method of claim 1, The semiconductor body includes a p-type surface region adjacent to the surface, but the transistor of each cell is of the n-channel type, and the p- is defined by an n-type well adjacent and interposed on the surface. A semiconductor device provided with a transistor in a p-type well insulated from the type surface region.