JP2003501838A - Semiconductor device having nonvolatile memory - Google Patents

Abstract

The present invention relates to a semiconductor device having a semiconductor structure having a programmable and electrically erasable non-volatile memory on its surface, having a matrix of memory cells each having a field effect transistor having a floating gate. About. The device according to the invention comprises a select transistor T2 in which each memory cell is connected in series with a floating gate transistor T1, said memory cells forming a NOR type matrix, wherein the select transistor is connected to the source of the floating gate transistor. On the other hand, both writing and erasing are performed based on a Fowler-Nordheim tunnel (injection) mechanism.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD OF THE INVENTION

The present invention relates to a semiconductor device having a semiconductor structure having on its surface a programmable and electrically erasable non-volatile memory having a matrix of memory cells each having a field effect transistor with a floating gate. The primary implementation of such a device is a CMOS circuit with built-in memory manufactured in a standard CMOS process. Such a semiconductor device is generally known.

[0002]

[Problems to be Solved by the Invention]

Built-in non-volatile memories often require high reliability during writing and erasing, short access times, and low power consumption. The techniques used to create so-called stand-alone memories usually do not adequately meet the requirements imposed on the embedded memory. As a result, for example, if the cell is N
It is arranged in an OR structure, and CHEI (Channel Hot Electron Injection
Electron Injection)) and FN tunneling ((Fowler-Nordheim tunneling
): Flash memories that undergo programming and erasing by the Fowler-Nordheim tunnel) mechanism often face the problem of over-erase (being over-erased). Further, general writing (programming) requires a large current. A memory with a NAND structure, in which both writing and erasing occur by the Fowler-Nordheim tunnel, requires high voltages for erasing and writing, and can thus have important consequences for the art.

[0003]

[Means for Solving the Problems]

It is an object of the present invention to provide a non-volatile memory which does not have the abovementioned disadvantages and which is particularly suitable as an embedded memory. According to the invention, a semiconductor device of the type described in the opening paragraph has, according to the invention, a select transistor in which each memory cell is connected in series with a floating gate transistor, both writing and erasing of the memory cell being a follower. It can be implemented on the basis of the Nordheim tunnel mechanism, characterized in that the memory cells form a NOR type matrix and the select transistor is connected to the source of the floating gate transistor.

The use of a NOR structure in which these cells are not in series allows for short access times. The problem of over-erasing can be solved by the select transistor. Using Fowler-Nordheim for both writing and erasing makes it possible to limit the current (power) for writing and erasing. Furthermore, the fact that the select transistor is arranged on the source side of the floating gate transistor makes it possible to use the entire surface of the channel for the FN tunnel. The resulting FN tunnel mechanism has high efficiency, so that lower voltage may be sufficient.

A preferred embodiment is that the transistor of each cell is of the n-channel type, while the semiconductor structure has a p-type surface region adjoining its surface, said transistor adjoining its surface. The p-type well is insulated from the p-type surface region by the n-type well to be inserted.

By using an isolated p-type well, it is possible to use bipolar voltages, so that the voltage (absolute value) has a maximum value and can be written / written in particular that can be made feasible. It is of great importance to the total number of erase cycles.

The above and other aspects of the invention will be described in detail below with reference to embodiments.

[0008]

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 represents a schematic diagram of a non-volatile, programmable and electrically erasable memory according to the invention. The device has a matrix of memory cells arranged in m rows and n columns. The cells in one row have Mi1, Mi2 ,. ． ．
, Min. The cells in column j are M1j, M2, where j is the number of columns.
j ,. ． ． , Mnj. As is generally known, each memory cell has a floating gate transistor T1 in which data can be stored on the floating gate. Each memory cell further has a second transistor T2 connected in series with T1, forming a select transistor connected to the source of the floating gate transistor T1. The source of the select transistor T2 is connected to the common junction point 1. The drains of the transistors T1 in a column are connected to the bit line BLi, where i is the number of columns. The bit line BL is connected to means 2 for supplying the desired voltage to the selected bit line. Each floating gate transistor T1 comprises a control gate connected to a word line Cgi, where i is the number of rows. Similarly, the gate of the select transistor T2 is connected to the word line Sgi. The Sg line and the Cg line are connected to the means 3,
By this means 3 an appropriate voltage can be supplied to the selected line.

The configuration of the memory cell described herein is described in the text as a NOR structure. The read current between the bit line BL and the junction point 1 flows only in the selected cell, and in the word line, for example, the cells in the column are connected in series, NAN
Relatively low voltage may be sufficient in contrast to D-type circuits.

FIG. 2 shows a cross-sectional view of one memory cell. Although not shown, apart from the memory cells shown here, this device clearly has electronic elements in its periphery. In addition, the device may also have logic portions manufactured in standard CMOS processes, not shown here, in further embedded applications. The silicon semiconductor structure has a p-type surface region 5 adjacent to the surface 4.
Have. This surface region can cover the entire semiconductor structure, but this is not necessary in this case. A deep n-type well 6 is provided in the surface region 5, with a slightly shallower p-type well in which the n-type channel transistors T1 and T2 are provided. The n-type well 6 insulates the p-type well 7 from the p-type substrate 5, so that a different voltage, eg a positive voltage, may be applied to the p-type well 7 compared to the voltage applied to the substrate 5, and / or Negative voltage is applied to the bit line. The transistor T2 has a gate 10, an n-type source 8 and an n-type drain 9 which are separated from the channel between the drain and the source by a gate oxide. The source is connected to junction point 1 as shown schematically and the gate is connected to word line Sg. The transistor T1 has a source formed by the zone 9 and an n-type drain 11 connected to the bit line BL.
The floating gate 12 is provided above the channel and is electrically insulated from the channel. A control gate 13 is provided above the floating gate, electrically insulated from the floating gate, and connected to the select line Cg. In the embodiment of FIG. 2, the control gate 13 is provided so as to overlap the floating gate 12, so that a large capacitive coupling is obtained between the gates. Obviously, the gates could alternatively be arranged as a stack. As a result, the capacitance between the gates is somewhat smaller, but the cell can then be made smaller.

[0011]   See Table 1 below for memory operations.

[Table 1]

Write (Programming) A low (negative) voltage Vnn (eg, −5V) is supplied to all word lines Sg. As a result, the selector transistor is not conducting. The low voltage Vnn is supplied to the selected bit line. As a result, the associated drain can temporarily act as the source. A positive voltage Vpp (eg, 5V) is supplied to the selected word line Cg. As a result, an inversion channel is formed in the transistor T1. Since the selector transistor is not conducting, no current is flowing in the cell. As a result, little or no power is wasted. There is a maximum voltage between the channel and the control gate. This voltage causes the electrons to be stored on the floating part due to the Fowler-Nordheim tunnel, (
For example, depending on oxide thickness and other process parameters). High efficiency is obtained because the transfer of charge occurs throughout the channel. As a result, the voltage used can be relatively low. As a result of this, the strength of the electric field across the tunnel oxide is also relatively small. As a result, damage to this oxide can be kept limited. Among other things, this is important for the number of write / erase cycles that can be performed. 0 volts is supplied to the unselected bit lines. As a result, the voltage between the oxides is so low that no Fowler-Nordheim tunnel occurs in the unselected cell. A low voltage Vnn is applied to the p-type well 7 during programming to prevent the pn junction belonging to the selected bit line from becoming forward biased.

In order to prevent the erase positive voltage Vpp from being forward biased to the pn junction between the n-type well and the p-type well, the p-type well 7 and further the n-type well are prevented. 6 is supplied. The low voltage Vnn is supplied to the selected word line Cg and 0 volt is supplied to the other word lines. The voltage on the gate oxide of the selected cell is now high enough again for the Fowler-Nordheim tunnel. As a result, electrons will tunnel from the floating gate to the substrate 5.
The potential of the floating gate and the threshold voltage of the transistor are lowered.
During erase, tunneling occurs across the channel surface, as is the case during writing. As a result, a relatively low voltage can be used during erase. Thanks to the use of this tunneling mechanism, the waste is very small during erasing. Since each cell has a select transistor, the threshold voltage is also very low and is never against erase to the point where it is less than 0 volts. This has important advantages, especially for reading.

Read To read a cell, a voltage is applied between the programmed cell threshold voltage (high threshold voltage) and the unprogrammed cell threshold voltage (erased cell low threshold voltage). It is applied to a selected word line Cg to see if the floating gate transistor is conducting. The highest available voltage Vdd is applied to the word line Sg of the cell. As a result, the select transistor becomes conductive. A low read voltage of 0.5 volts is applied to the selected lines and 0 volts is applied to the unselected bit lines. The result is Vds = 0 volts in these cells and no current can flow in these cells. As the threshold voltage of the unprogrammed cells is low as described above and can even be less than 0 volts, a relatively low voltage, for example 1 volt in the example according to the above table, is available on the selected word line Cg. is there.

It will be appreciated that the invention is not limited to the examples described here and that many other variants are feasible to a person skilled in the art.

[Brief description of drawings]

FIG. 1 is a diagram of an equivalent circuit of a non-volatile memory according to the present invention.

2 is a cross-sectional view of a memory cell of the device of FIG.

[Explanation of symbols]

1: floating gate transistor, 4: surface, 5: substrate, 6: n-type well, 7: p-type well, 10: Gate, 11: n-type drain, 12: floating gate, BL: Bit line, Cg: Select line, Sg: Word line, T1: transistor, T2: Transistor

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Verhal Robertas DJ Netherlands 5656 Aer Aindo Fenprof Holstraan 6 (72) Inventor Dolmans Guid J.M. Netherlands 5656 Aer Aindo Venprof Holstran 6 (72) Invention Kuppens Roger The Netherlands 5656 Aer Aindouven Fenprof Holsstraan 6 (72) Inventor De Graaf Caroline The Netherlands 5656 Aar Aindou Fenprofl Holstran 6 F Term (Reference) 5B025 AA03 AB01 AC02 AD04 AD05 AD08 AE05 AE06 AE08 5F083 EP02 EP02 5F083 EP02 EP34 EP77 ER09 ER19 ER29 ER30 GA05 PR41 5F101 BA07 BB02 BC02 BD22 BD31 BD33 BD36 BE02 BE05 BE07 BH21 [Summary] Continued】

Claims (2)

[Claims] 1. A semiconductor device having a semiconductor structure having a programmable and electrically erasable non-volatile memory on its surface, comprising a matrix of memory cells each having a field effect transistor having a floating gate, each comprising: The memory cell has a select transistor connected in series with a floating gate transistor, the memory cell forms a NOR type matrix, the select transistor is connected to a source of the floating gate transistor, and the memory cell is programmed. A semiconductor device in which both erasing and erasing are performed based on the Fowler-Nordheim tunnel mechanism. 2. The transistor of each cell is an n-channel type, the semiconductor structure has a p-type surface region adjacent to the surface, and the transistor is provided in a p-type well connected to the surface, 2. The semiconductor device according to claim 1, wherein a p-type well is insulated from the p-type surface region by an n-type well inserted therein.