JPH0630066A - Data decoder - Google Patents

Abstract

PURPOSE:To detect an identification point in a stable state without receiving the influence of short interval fluctuation. CONSTITUTION:One piece of specific data is selected from memory 11, and a reception phase 22 is found by a reception phase computer 21, and a square sum of error and a frequency offset are found by an error computer 23, and the minimum point of a square sum 25 of error is found by a minimum point detector 26. A rough estimation value 27 of a pilot symbol and a frequency offset rough estimation value 28 are found from the minimum point, thence, the reception phase 32 of the pilot symbol is found by a reception phase computer 31. A square sum of error of a value in which the reception phase of the pilot symbol is corrected by the frequency offset and a wall-known pilot symbol is found. An identification point detector 36 finds the minimum point of a square sum 35 of error, and finds an identification point position and the frequency offset from the minimum point. Data obtained from the detection result of the identification detector 36 is corrected by a phase controller 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data decoding device, and more particularly to a data decoding device suitable for use in a digital communication receiver or the like.

[0002]

2. Description of the Related Art Conventionally, a data decoding device shown in FIG. 2 has been known as a data decoding device used in a digital communication receiver. In FIG. 2, 41 is a transmitter, and 42 is a transmission antenna of the transmitter 41. Reference numeral 43 is a receiving antenna of the receiver 44, and the receiver 44 can separate the received signal into IQ components. Reference numeral 45 is an I signal output from the receiver 44, and 46 is a Q signal. 47 and 48 are A / D converters that oversample I and Q signals by m times, and 49 and 50 are digitized I / D converters.
Signal and Q signal. Reference numeral 51 is a memory for storing the I and Q signals as data. 52 and 53 are I and Q signals, respectively, of which the identification points are detected, and the phase controller 54 of 54
The frequency offset is removed by. Reference numerals 55 and 56 are I and Q signals from which the frequency offset has been removed by the phase controller 54, and these signals are decoded by the decoder 57 and output as a decoded signal 58. On the other hand, 59 and 60 are I and Q signals extracted from the memory 51, and these signals are received phase calculator 6
When input to 1, the reception phase 62 is obtained here.
An error calculator 63 calculates a frequency offset from the reception phase 62 and the phase of the known synchronization word stored in the memory 64 by the least squares method, removes the frequency offset from the reception phase, and removes the frequency offset from the reception phase. The sum of squares of the difference between the synchronization words is output as the sum of squares of error 65. The error square sum 65 is input to the discrimination point detector 66, where the minimum position of the error square sum 65 is detected, and the m-times oversampled I and Q signals in the memory 51 are discriminated based on this detected value. The point is detected. When the detection result 68 of the identification point detector 66 is input to the phase controller 54, the frequency offset for the I signal 52 and the Q signal 53 is removed.

Signals having a data structure as shown in FIG. 3 are used in the apparatus shown in FIG. In FIG.
P is a pilot symbol, which is a known signal. D is data and SW is a known signal in the synchronization word. P
_{0 to} P _m-1 are signals oversampled m times. In the above apparatus, one unit of data (referred to as one symbol) is oversampled m times (1 symbol = m samples), and the most synchronized point is detected from this data.

The operation of the data decoding apparatus configured as described above will be described below. First, the transmitter 41
When a signal is transmitted from the antenna through the antenna 42, the signal is received by the antenna 43 and input to the receiver 44. The receiver 44 separates the received signal into I and Q signals, and outputs the separated signals, I signal 45 and Q signal 46, to A / D converters 47 and 48, respectively. Each A / D converter 47, 48
Performs m times oversampling on the input signal and stores the sampling result in the memory 51. When the m-times sampled data is stored in the memory 51, the reception phase 62 based on the data stored in the memory 51.
Is required. The sum of squares of error 65 is calculated from the difference between the reception phase 62 and the phase of the synchronization word stored in the memory 64, and based on the sum of squares of error 65, the most synchronized data is sampled m times. An identification point, which is a point, is detected. When the detection result of this discrimination point is input to the phase controller 54, the I signals 52 and Q extracted from the memory 51 are extracted.
Processing for removing the frequency offset for the signal 53 is performed. When the data from which the frequency offset has been removed is input to the decoder 57, the data is decoded here.

In the course of the above series of processing, the following processing is performed on the signal stored in the memory 51 to detect the discrimination point.

That is, the reception phase calculator 61 obtains the reception phase 62 from the I and Q signals of the memory 51, and the following processing is performed on the reception phase 62.

First, the frequency offset is obtained from the difference between the reception phase 62 and the phase of the sync word stored in the memory 64 by the method of least squares. Further, the frequency offset is corrected for the reception phase 62. Then, the sum of squares of the difference between the reception phase 62 subjected to the frequency offset correction and the phase of the synchronization word is obtained, and this sum of squares is input to the discrimination point detector 66 as the sum of squares of error 65. The discrimination point detector 66 finds the minimum point of the error sum of squares 65 and generates the address of the memory 51 in which this data is stored. At the same time, the frequency offset value 68 is output to the phase controller 54. Identification point detector 66 in memory 51
When the address 67 from is input, the I signal 52 and the Q signal 53 according to this address are input to the phase controller 54. The phase controller 54 corrects the frequency offset based on the frequency offset value. The decoder 57 decodes the data for which the frequency offset correction has been performed.

As described above, in the above-mentioned conventional data decoding device, the data obtained by oversampling m times by the A / D converters 47 and 48 is optimized by the reception phase calculator 61, the error calculator 63, and the discrimination point detector 66. , The phase offset is removed by the phase controller 54 from the data 52, 53 extracted by this identification point, and the decoder 57 performs decoding on the data from which the frequency offset is removed. Will be seen.

[0009]

However, the above conventional data decoding device has the following problems. (1) Since the synchronization word is short, the detection value of the identification point fluctuates when affected by the short section fluctuation. (2) Since the sync word is short, the frequency offset fluctuates when affected by the short-term fluctuation. (3) Since the identification point detection is performed on the m-times oversampled data, the processing amount increases.

The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a data decoding device capable of accurately detecting an identification point without being affected by short-term fluctuations. Is.

[0011]

In order to achieve the above-mentioned object, the present invention separates a signal having a sync word and a pilot symbol into I and Q component signals, and separates each separated by the separating means. A / D conversion means for converting each signal into a digital signal, first storage means for storing the output signal of the A / D conversion means as digital data of I and Q components, and the first storage means The first reception phase calculation means for calculating the reception phase of both components from the specific data of each component, the second storage means for storing the data relating to the phase of the synchronization word, the phase of the synchronization word and the reception phase. First frequency offset calculating means for calculating the frequency offset of the reception phase from the difference between the two, and first frequency offset correcting means for correcting the frequency offset,
First error calculating means for calculating an error between the corrected reception phase and the phase of the synchronization word, pilot symbol position rough estimating means for roughly estimating a pilot symbol position based on the error value, and the error A frequency offset rough estimation value constant calculation means for calculating a rough estimation value of the frequency offset based on the value; and a second reception phase calculation means for calculating the reception phase of the data of each component stored in the first storage means. Second frequency offset calculation means for calculating a frequency offset with respect to the reception phase from the difference between the reception phase calculated by the second reception phase calculation means and the phase of the synchronization word stored in the second storage means; Second frequency offset correction means for correcting the frequency offset calculated by the frequency offset calculation means of FIG. Identification point detecting means for detecting an identification point, extraction means for extracting data from the specific data of each component stored in the first storage means based on the identification point, and second frequency offset correction means Frequency offset value calculation means for calculating a frequency offset value based on the difference between the reception phase and the phase of the pilot symbol corrected by the frequency offset correction means, and the calculated value of the frequency offset value calculation means for the data by the data extraction means. Phase control means for correcting the frequency offset according to the above.

[0012]

Therefore, according to the configuration of the present invention, one designated data is selected from the m-times oversampled data, and the sum of squares of the error is calculated for the data based on the phase of the synchronization word. . Then, the rough estimation of the position of the pilot symbol and the rough estimation of the frequency offset are performed based on the sum of squared errors. Then, the phase of the pilot symbol received from the data relating to the pilot symbol is compared with the phase of the known pilot symbol, and the frequency offset is obtained by the least square method. Then, the sum of squared errors between the result obtained by removing the frequency offset from the received pilot symbol and the phase of the pilot symbol is obtained. Then, the identification point is determined from the minimum point of the sum of squared errors, and the frequency offset is obtained. That is, the position of the pilot symbol is roughly estimated from the synchronization word, and the identification point and the frequency offset are obtained from the pilot symbol having a longer period than the synchronization word. Therefore, the identification point is detected in a section longer than the synchronization word, and the identification point can be stably detected. Further, since the frequency offset is detected in a section longer than the synchronization word, it is possible to reduce the influence of the short section fluctuation of the frequency offset. Furthermore, since the rough estimation uses only one of the data oversampled multiple times, the processing amount can be reduced.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows the configuration of an embodiment of the present invention. In FIG. 1, the data decoding device includes an antenna 3, a receiver 4, an A / D converter 7, a memory 11, and a phase controller 1.
4, decoder 17, reception phase calculator 21, error calculator 2
3, memory 24, minimum point detector 26, reception phase calculator 3
1, an error calculator 33, a memory 34, and an identification point detector 36 are provided, and the signal transmitted from the antenna 2 of the transmitter 1 is input to the receiver 4 via the antenna 3.

The receiver 4 is configured as a separating means for separating a received signal having a sync word and a pilot symbol into an I component signal and a Q component signal. A / D converter 7,
Reference numeral 8 is configured as A / D conversion means for receiving the I signal 5 and the Q signal 6 from the receiver 4 and oversampling these signals by m times and converting them into digital signals. The memory 11 is configured as first storage means for storing the output signals of the A / D converters 7 and 8 as digital data. The reception phase calculator 21 is configured as a first reception phase calculation means for receiving the data of the I data 19 and the Q data 20 extracted from the memory 11 and calculating the reception phase 22 of both from the data. The memory 24 constitutes second storage means for storing data relating to the phase of the sync word. The error calculator 23 is configured as first frequency offset calculating means for calculating the frequency offset of the reception phase from the difference between the phase of the synchronization word stored in the memory 24 and the reception phase 22. Further, a first frequency offset correction means for correcting the frequency offset of the reception phase based on the reception phase 22 is configured. Further, it is configured as a first error calculating means for calculating an error between the reception phase whose frequency offset is corrected and the phase of the synchronization word stored in the memory 24. The minimum point detector 26 constitutes a pilot symbol position rough estimation means for roughly estimating the position of the pilot symbol based on the calculated value of the first error calculation means, and also the frequency offset of the frequency offset based on the calculated value of the first error calculation means. The frequency offset rough estimated value calculating means for calculating the rough estimated value is configured.

On the other hand, the reception phase calculator 31 extracts data from the data of each component stored in the memory 11 according to the rough estimated value 27 of the minimum point detector 26 to calculate the reception phase 32 of both. It is configured as a phase calculation means. The error calculator 33 constitutes second frequency offset calculation means for calculating a frequency offset with respect to the reception phase from the difference between the phase of the synchronization word stored in the memory 34 as the second storage means and the reception phase 32, and also the frequency offset The second frequency offset correcting means for correcting the above is based on the detection result 28 of the minimum point detector 26. The identification point detector 36 constitutes an identification point detecting means for detecting an identification point based on the difference between the reception phase whose frequency offset is corrected and the phase of the pilot symbol, and the data of each component stored in the memory 11 is detected. A data extracting means for extracting data according to the detected value of the identification point from the inside is configured. Further, a frequency offset value calculating means for calculating a frequency offset value based on the difference between the reception phase corrected for the frequency offset and the phase of the pilot symbol is configured. The phase controller 14 uses the data 12, 13 extracted from the memory 11
On the other hand, it is configured as phase control means for correcting the frequency offset according to the detection result of the identification point detector 36. The decoder 17 is configured as a decoding unit that decodes the data subjected to the frequency offset correction.

Next, the operation of the above embodiment will be described. When the reception signal is separated into the I signal 5 and the Q signal 6 by the receiver 4, these signals are oversampled m times by the A / D converters 7 and 8 and converted into digital signals. These digital signals 9 and 10 are stored in the memory 11 as digital data. When the data of I and Q components are stored in the memory 11, these data are received by the reception phase calculator 3
It is output to 1. The reception phase calculator 31 calculates the reception phase 22 based on the data from the memory 1. Then, the following processing is performed on the reception phase 22.

First, the error calculator 23 obtains a frequency offset from the difference between the phase of the reception phase 22 and the phase of the synchronization word stored in the memory 11 by the least square method. Next, the frequency offset is corrected for the reception phase 22. Then, the reception phase 2 for which the frequency offset correction has been performed
The sum of squares of the difference between 2 and the phase of the sync word is obtained, and the sum of squares is output to the discrimination point detector 26 as the sum of squares of error 25. When the error sum of squares 25 is input to the minimum point detector 36, the minimum point detector 26 executes the following two processes based on the error square sum 25.

The minimum point detector 26 determines the minimum point based on the error sum of squares 25, performs rough estimation of the position of the pilot symbol based on this minimum point, and outputs this estimation result to the address 27.
Is output to the memory 11. Further, a rough estimation value of the frequency offset at the minimum point is obtained, and this rough estimation value is output to the error calculator 33.

When the data of each component is extracted from the memory 11 according to the address 27, these data 29, 30 are obtained.
Is input to the reception phase calculator 31. Reception phase calculator 3
In 1, the reception phase 32 of these data is obtained from the deviation from the data 29 and 30, and the reception phase 32 is output to the error calculator 33. Then, the error calculator 33 performs the following processing on the reception phase 32.

The error calculator 33 calculates the frequency offset from the difference between the phase of the synchronization word stored in the memory 34 and the reception phase 32 by the least square method. At this time,
When the interval between pilot symbols is long, the phase makes one rotation or more, so the rotation speed is corrected based on the frequency offset obtained from the synchronization word. Further, the frequency offset is corrected for the reception phase 32. Next, the sum of squares of the difference between the reception phase 32 subjected to the frequency offset correction and the phase of the pilot symbol is calculated. Then, this calculated value is output to the discrimination point detector 36 as the error sum of squares 35.

The discriminant point detector 36 finds the minimum point of the sum of squared errors 35 based on the sum of squared errors 35, and detects the discriminant point from this minimum point. Then, the address 37 of the identification point is set to the memory 1
Output to 1. At this time, at the same time, the offset frequency 38 at the minimum point is obtained, and information regarding this offset frequency 38 is output to the phase controller 14.

The data 12 and 13 designated by the address 37 are input to the phase controller 14, and the frequency offset of the data 12 and 13 is corrected according to the offset frequency 38. Then, the data 15 and 16 for which the frequency offset is corrected are the decoder 17
When the input signal is input to, the data is decoded and the decoded signal 18 is output.

[0024]

As is apparent from the above-described embodiment, the present invention performs rough estimation of the pilot symbol by the synchronization word and coarse estimation of the frequency offset, and based on the pilot symbol, determines the position of the identification point and the frequency offset. Since the determination is made, the identification point and the frequency offset can be detected for a time longer than that of the sync word, and the identification point and the frequency offset can be detected without being affected by the short-term fluctuation. Further, since the position of the pilot symbol is roughly estimated by the synchronization word, it is not necessary to detect the identification point for all the data oversampled multiple times. Therefore, the detection of the identification point and the frequency offset is performed less than before. It can be done in quantity.

[Brief description of drawings]

FIG. 1 is a block diagram of a data decoding device showing an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional data decoding device.

FIG. 3 is a block diagram of transmission data having a synchronization word and a pilot symbol.

[Explanation of symbols]

 1 transmitter 2 transmission antenna 3 reception antenna 4 receiver 7,8 A / D converter 11 memory 12 phase controller 17 decoder 21 reception phase calculator 23 error calculator 24 memory 26 minimum point detector 31 reception phase calculator 33 error calculator 34 memory 36 identification point detector

Claims (1)

[Claims] 1. A separation means for separating a signal having a sync word and a pilot symbol into I and Q component signals, an A / D conversion means for converting each signal separated by the separation means into a digital signal, and A First storage means for storing the output signal of the D / D conversion means as digital data of I and Q components, and first reception means for calculating the reception phases of both components from the specific data of each component stored in the first storage means. No. 1 reception phase calculation means, second storage means for storing data relating to the phase of the synchronization word, and first frequency offset for calculating the frequency offset of the reception phase from the difference between the phase of the synchronization word and the reception phase. Calculation means, first frequency offset correction means for correcting the frequency offset,
First error calculating means for calculating an error between the corrected reception phase and the phase of the synchronization word, pilot symbol position rough estimating means for roughly estimating a pilot symbol position based on the error value, and the error A frequency offset rough estimation value constant calculation means for calculating a rough estimation value of the frequency offset based on the value; and a second reception phase calculation means for calculating the reception phase of the data of each component stored in the first storage means. Second frequency offset calculation means for calculating a frequency offset with respect to the reception phase from the difference between the reception phase calculated by the second reception phase calculation means and the phase of the synchronization word stored in the second storage means; Second frequency offset correction means for correcting the frequency offset calculated by the frequency offset calculation means of FIG. Identification point detecting means for detecting an identification point, extraction means for extracting data from the specific data of each component stored in the first storage means based on the identification point, and second frequency offset correction means Frequency offset value calculation means for calculating a frequency offset value based on the difference between the reception phase and the phase of the pilot symbol corrected by the frequency offset correction means, and the calculated value of the frequency offset value calculation means for the data by the data extraction means. And a phase control unit that corrects the frequency offset according to the data decoding apparatus.