JP3106709B2 - Data decoding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data decoding apparatus used for a digital communication receiver capable of receiving a video signal.

[0002]

2. Description of the Related Art FIG. 5 shows a configuration of a conventional data decoding device. In FIG. 5, reference numeral 101 denotes a transmitter.
2 is the transmitting antenna. Reference numeral 103 denotes a receiving antenna of a receiver, and 104 denotes a receiving unit that separates a received signal into I and Q signals. 105 is an I signal output from the receiving unit 104;
106 is a Q signal. A / D converters 107 and 108 oversample the I and Q signals by m times.
110 is a memory for storing the digitized I and Q signals, and 111 is a memory for storing the I and Q signals. Reference numerals 112 and 113 denote I and Q signals at which identification points are detected, 114 denotes a decoder, and 115 denotes decoded received data. 11
Reference numerals 6 and 117 denote I and Q signals read from the memory 111, and 118 denotes a reception phase calculator which outputs a reception phase 119. Reference numeral 120 denotes an error calculator that obtains a sum of error squares from a result obtained by removing a frequency offset from the reception phase 119 and the phase of the synchronization word stored in the memory 121 by the least square method, and 122 denotes a sum of error squares of the result. . Reference numeral 123 denotes an identification point detector which detects the minimum position of the error square sum 122 and obtains the identification points of the oversampled I and Q signals in the memory 111 based on the detected minimum position. Reference numeral 124 denotes the address of the obtained identification point.

FIG. 4 shows a data structure used in the above device. P is a signal known as a pilot symbol. D is data. SW is a known signal of a synchronization word. An identification point is detected based on the synchronization word SW.
In the present apparatus, one unit of data (referred to as one symbol) is oversampled by m times (one symbol = m samples), and the most synchronized point is detected from this data.

[0004] The operation of the data decoding device configured as described above will be described below. First, FIG.
In, the transmitter 101 transmits a signal from the transmission antenna 102 to the receiver. Receiver is receiving antenna 1
In step 03, the receiving unit 104 separates the signal into an I signal 105 and a Q signal 106. Next, the I and Q signals 105 and 10
A / D converters 107 and 108 perform m-times oversampling on each of the 6 signals, and digitized I and Q signals 109 and 110 are stored in a memory 111.
Then, the most synchronized point, that is, the discrimination point is detected from the data 109 and 110 of the m-times sample, and the I and Q signals 112 and 113 are transmitted from the memory 111 based on the detected signal.
And the decoder 114 decodes the received signal.

[0005] Identification point detection is performed on the I and Q signals stored in the memory 111 as follows. Memory 1
11 from the I and Q signals 116 and 117
At 18, a reception phase 119 is obtained. The following processing is performed on the reception phase 119. First, a frequency offset is obtained from the difference between the reception phase 119 and the phase of the synchronization word stored in the memory 121 by the least square method. Next, the frequency offset of the reception phase 119 is corrected. Then, the sum of squares of the difference between the reception phase subjected to the frequency offset correction and the phase of the synchronization word is obtained. This is sent to the discrimination point detector 123 as the error square sum 122. The discrimination point is obtained as the address 124 of the memory where the received data that minimizes the error square sum 122 is stored. Based on the address 124, the I signal 112 and the Q signal 113 at the discrimination point are sent from the memory 111 to the decoder 114 to decode the data.

As described above, in the above-mentioned conventional data decoding apparatus, the data obtained by oversampling by the A / D converters 107 and 108 are optimally identified by the reception phase calculator 118, the error calculator 120 and the identification point detector 123. A point is obtained, and the decoder 114 decodes the data 112 and 113 in the memory 111 extracted by the identification point address 124.

[0007]

However, the above-mentioned conventional data decoding apparatus has the following problem because the synchronization word is shorter than the received signal. (1) When the reception state near the synchronization word is deteriorated, the detection of the identification point is erroneously performed. (2) Since the synchronization word is short, the performance of estimating the frequency offset is low and the performance of discriminating point position detection is poor.

The present invention solves the above-mentioned conventional problem, and provides an excellent data decoding apparatus capable of stably detecting an identification point without error even when the reception state near a synchronization word is poor. The purpose is to:

[0009]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a digital signal obtained by oversampling a received signal separated into I and Q signals from data having a known synchronization word and pilot symbols. A / D converter to be converted, a memory for storing the oversampled I and Q signals, a first reception phase calculator for obtaining a reception phase from the I and Q signals, and a frequency offset superimposed on the reception signal is minimized. A first error calculator for obtaining a first error sum of squares, which is an integrated value of the square of an error between a synchronization word included in the received signal and a previously stored synchronization word, When the address by performing reception time estimated pilot symbols from a position stored in the smallest time in the first error square sum of the sync word And outputs the serial memory, the first minimum point detector for outputting a second error sum of squares of around the time of the smallest of the first error square sum with frequency offset estimate, near the pilot symbols I, A second reception phase calculator for obtaining a reception phase from the Q signal; a frequency offset superimposed on the pilot symbol section is removed by a least squares method, and a square of an error between the pilot symbol section of the reception signal and a pilot symbol stored in advance. the minimum second seeking third error square sum is an integrated value and the error calculator, a second outputting a fourth error sum of squares of around smallest time in the third error square sum of pilot symbols A point detector, the second sum of squares of error determined by a synchronization word and the fourth sum determined by a pilot symbol.
An identification point detector for detecting an identification point from the sum of squared errors and outputting the address to the memory;
And a decoder for demodulating data from the Q signal.

[0010]

According to the present invention, the sum of the square of the error and the position of the pilot symbol are estimated based on the synchronization word. Next, from the data in the vicinity of the pilot symbol, the phase of the received pilot symbol is compared with the phase of the known pilot symbol, the frequency offset is obtained by the least square method, and the result of removing the frequency offset from the received pilot symbol and the pilot symbol Of the square of the error with the phase of Then, a discrimination point position is obtained from the amplitude near the minimum point of the sum of error squares obtained by the synchronization word and the amplitude near the minimum point of the error sum of squares obtained by the pilot symbol.

Therefore, by correcting the discrimination point obtained from the synchronization word with the discrimination point obtained from the pilot symbol, (1) the detection of the discrimination point position can be performed even when the reception state of the section of the synchronization word is poor. . (2) Since the identification point is detected in a section longer than the synchronization word, the identification point can be detected stably. It has the effect of.

[0012]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of a data decoding device according to an embodiment of the present invention. 1 is a transmitter,
2 is the transmitting antenna. Reference numeral 3 denotes a receiving antenna of the receiver, and reference numeral 4 denotes a receiving unit that separates a received signal into I and Q signals. Reference numeral 5 denotes an I signal which is an output of the receiving unit 4, and reference numeral 6 denotes a Q signal. 7 and 8 are A for oversampling the I and Q signals by m times.
/ D converters, 9 and 10 are memories for storing digitized I and Q signals, and 11 is a memory for storing I and Q signals.
Reference numerals 12 and 13 denote I and Q signals at which the identification points are detected, respectively.
Reference numeral 4 denotes a decoder, and reference numeral 15 denotes decoded reception data. Reference numerals 16 and 17 denote I and Q signals output from the memory 11, and reference numeral 18 denotes a reception phase calculator which outputs a reception phase 19. Reference numeral 20 denotes an error calculator that obtains a sum of error squares from a result obtained by removing a frequency offset from the reception phase 19 and the phase of the synchronization word stored in the memory 21 by the least square method, and 22 denotes a sum of error squares of the result. . Reference numeral 23 denotes a minimum point detector that obtains an address 24 of an estimated position of a pilot symbol from the minimum point of the error square sum 22, an estimated frequency offset value 25, and an error square sum 26 for one symbol near the minimum point. 27 and 28 are I and Q signals near the pilot symbol output from the memory 11 based on the estimated address 24 of the pilot symbol, and 29 is an I and Q signal.
This is a reception phase calculator that calculates the reception phase 30 for the signals 27 and 28. An error calculator 31 calculates the frequency offset of the pilot symbol by the least square method from the reception phase 30 and the phase of the pilot symbol stored in the memory 32 and the frequency offset estimation value 25 of the synchronization word. Error sum of squares. 34 is the error square sum 3 of one symbol near the minimum point of the error square sum 33
5 is the minimum point detector that outputs 5. An identification point detector 36 detects an identification point from the error square sum 35 for one symbol of the pilot symbol and the error square sum 26 for one symbol of the synchronization word, and outputs the address 37 to the memory 11. is there.

Next, the operation of the above embodiment will be described. Note that this embodiment also has the same data configuration as the data configuration shown in FIG. In FIG. 1, when a signal from a transmitter 1 is received by a receiving antenna 3 of a receiver, a receiving unit 4 separates the received signal into an I signal 5 and a Q signal 6.
Next, the A / D converters 7 and 8 perform oversampling by m times on the I and Q signals 5 and 6, respectively, and store the digitized I and Q signals 9 and 10 in the memory 11. Then, the most synchronized point, that is, the discrimination point is detected from the data of the m-times sample, the I and Q signals 12 and 13 are read out from the memory 11 based on the detected signal, and the decoder 14 decodes the received signal. Perform

In this embodiment, the identification point is detected in the memory 1
1 is performed as follows on the basis of the synchronization word and the pilot symbol.

A reception phase calculator 18 obtains a reception phase 19 from the I and Q signals 16 and 17 of the memory 11 for the synchronization word. The following processing is performed on the reception phase 19. First, the error calculator 20 calculates a frequency offset from the difference between the reception phase 19 and the phase of the synchronization word stored in the memory 21 by the least square method, and corrects the frequency offset for the reception phase 19 to obtain the frequency offset. The sum of squares of the difference between the corrected reception phase and the phase of the synchronization word is obtained. This is sent to the minimum point detector 23 as the error square sum 22. At the same time, a frequency offset is sent. The minimum point detector 23 calculates the following three based on the error square sum 22. (1) Find the minimum point, estimate the position of the pilot symbol based on it, and send its address 24 to the memory 11. (2) Find the frequency offset estimation value 25 at the minimum point,
It is sent to the error calculator 31. (3) Error square sum 26 near the minimum point (1 symbol m
Are sent to the discrimination point detector 36.

With respect to the pilot symbols, based on the estimated address 24 of the pilot symbol in the memory 11 estimated from the synchronization word, the I, Q signals 27,
28, and a reception phase calculator 29 calculates a reception phase 30. The following processing is performed on the reception phase 30. (1) A frequency offset is obtained from the difference between the reception phase 30 and the phase of the synchronization word stored in the memory 32 by the least square method. At this time, when the interval between the pilot symbols is long, the phase is rotated by one or more times. Therefore, the rotation speed is corrected based on the frequency offset obtained by the synchronization word. (2) The frequency offset is corrected for the reception phase 30. (3) The sum of squares of the difference between the reception phase after the frequency offset correction and the phase of the pilot symbol is obtained.

This is sent to a minimum point detector 34 as a sum of error squares 33. In the minimum point detector 34, m error square sums 35 for one symbol near the minimum point of the error square sum 33 are passed to the discrimination point detector 36.

The discriminating point detector 36 calculates a sum of error squares 26 with the synchronization word and a sum of error squares 35 with the pilot symbol.
To detect the identification point. FIG. 2 shows an example of the error square sum 26 using the synchronization word. The horizontal axis is m near the minimum squared error square.
This is a sample over-folded twice. FIG. 3 shows an example of an error square sum 35 using pilot symbols. The abscissa is a sample oversampled by m times near the minimum error square sum point. Identification points are detected from these two points as follows.

First, the minimum point of the sum of error squares 26 based on the synchronization word and the minimum point of the sum of error squares 35 based on the pilot symbol are compared. From the result, the following three methods are used to select an identification point. (1) When the sum of error squares of a small modulus is smaller than a specified value 1, an identification point is determined from the smaller sum of error squares. (2) If the smaller sum of error squares is larger than the specified value 1 and the larger sum of error squares is smaller than the specified value 2, two intermediate points are determined as identification points. (3) If the smaller sum of error squares is larger than the specified value 1 and the larger sum of error squares is larger than the specified value 2, the identification point is determined from the smaller one.

In the example of FIGS. 2 and 3, an identification point is selected from the synchronization word, and the result is sample 3.

[0021]

As described above, according to the present invention, by adding a synchronization detection circuit for pilot symbols, even when the reception state is poor near the synchronization word, the identification point can be detected for a longer time than the synchronization word. This has the effect that identification point detection can be performed stably without error.

[Brief description of the drawings]

FIG. 1 is a block diagram of a data decoding device according to an embodiment of the present invention.

FIG. 2 is a distribution diagram showing an example of a sum of squares of error caused by a synchronization word in one embodiment of the present invention.

FIG. 3 is a distribution diagram showing an example of a sum of squares of errors caused by pilot symbols in one embodiment of the present invention.

FIG. 4 is a data configuration diagram of transmission data having a synchronization word and a pilot symbol.

FIG. 5 is a block diagram of a conventional data decoding device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Transmitter 4 Receiver 5 I signal 6 Q signal 7,8 A / D converter 11 Memory 14 Decoder 18 Reception phase calculator 20 Error calculator 21 Memory storing phase of synchronization word 22 Error sum of squares 23 Minimum inspection Output unit 24 Pilot symbol estimation address 29 Receive phase calculator 31 Error calculator 32 Memory storing pilot symbol phase 34 Minimum point detector 36 Discrimination point detector

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-30066 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 27/00-27/38

Claims (1)

(57) [Claims] An A / D converter for oversampling and digitizing a received signal obtained by separating I and Q from data having a known synchronization word and pilot symbol, and an oversampled I and Q signal , A first reception phase calculator for obtaining a reception phase from the I and Q signals, and a frequency offset superimposed on the reception signal is removed by a least squares method, and a synchronization word included in the reception signal is stored in advance. a first error calculator for obtaining a first error square sum is an integrated value of the squares of errors between the synchronization word has a smallest of the first error sum of squares of the received signal and the synchronization word in said memory A pilot symbol reception time is estimated from a position stored at a given time, and its address is output to the memory. And a first minimum point detector for outputting a second error sum of squares near the time when the first error sum of squares is minimum, and a second reception for obtaining a reception phase from I and Q signals near pilot symbols. The phase calculator removes the frequency offset superimposed on the pilot symbol interval by the least square method, and calculates a third error sum of squares, which is an integrated value of the square of the pilot symbol interval of the received signal and the pilot symbol error stored in advance. A second error calculator for calculating, a second minimum point detector for outputting a fourth error sum of squares around the time when the pilot error is the minimum among the third error sum of squares, The fourth error obtained from the second error sum of squares and pilot symbols;
An identification point detector for detecting an identification point from the sum of squared errors and outputting the address to the memory;
And a decoder for demodulating data from the Q signal.