JPH0787153A - Data converter - Google Patents

Abstract

PURPOSE:To eliminate the occurrence of error for decoding by comparing values preceding and following the sample having a maximum synchronous addition value to correct the timing of A/D conversion. CONSTITUTION:A clock deviation detecting circuit 22 uses a result 19 obtained by a synchronous addition circuit 18 to compare the synchronous addition result of a sample M-1 just preceding the sample M having a maximum synchronous addition result and that of a sample M+1 just following it with each other with respect to the correcting direction and the correction value of the phase difference between transmission and reception clocks, and the timing is not corrected when the difference between them is smaller than a set value. When it is larger, the timing is corrected in the accelerating direction; and when the synchronous addition result or the sample M+1 is larger than that of the sample M-1, the timing is corrected in the delaying direction. A timing correction circuit 24 corrects the timing of conversion start of A/D converters 7 and 8 based on a correction value 23. Thus, the phase difference between transmitter and receiver clocks is absorbed, and the receiver performance is improved without increasing the oversampling of A/D converters, and the occurrence of error for decoding is eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data converter used for reproducing digital data from a received signal in a receiver for digital communication and the like, and more particularly, it can absorb a phase difference between a clock and a transmitter. It is configured as follows.

[0002]

2. Description of the Related Art In digital communication, the receiving side extracts the level of a received signal at the transmission timing of a symbol (1, 0) on the transmitting side, and compares the extracted signal level with a threshold value. Reproduce the original digital signal. Therefore, on the receiving side, all of the received signal levels are once digitized and stored at a sampling frequency that is an integral multiple of the symbol clock (symbol transmission frequency), and the transmitted symbol is represented from these samples. Sample that matches the symbol transmission timing.

The sample representing this transmitted symbol is identified as follows. Assuming that the reception signal is digitized at the sampling frequency N times the symbol clock at the reception side, when the reception signals representing a plurality of symbol strings are digitized, the reception signal levels of every Nth sample are added. The value shows the maximum value when each sample to be added respectively represents a transmission symbol.
Therefore, the received signal levels of the stored samples can be added by the above procedure, and the Nth sample having the maximum added value can be identified as the target.

FIG. 4 shows a conventional data converter in digital communication of 16QAM (16-value quadrature amplitude modulation) system. This device quadrature-modulates transmission data and transmits it through a transmission antenna 2, and quadrature-detects a signal received from a reception antenna 2 to separate it into an in-phase component I signal and a quadrature component Q signal. Receiver 4
And A / D converters 7 and 8 that digitize the I signal 5 and the Q signal 6 output from the receiver 4 at a sampling frequency that is an integral multiple of the symbol clock, and the digitized I
A memory 11 for storing the signal 9 and the Q signal 10, and a memory 11
A synchronous adder circuit 18 for synchronously adding the powers of the I signal 16 and the Q signal 17 of the samples stored in each N sample, and a sample representing a transmission symbol is stored based on the result 19 of synchronous addition over a certain time interval. An identification point detector 20 for detecting a leading address 21 on the memory 11 and a decoding circuit 14 for comparing the I signal 12 and the Q signal 13 representing the extracted symbol with a threshold value and outputting the decoded data 15. I have it.

Further, FIG. 3 shows the signal point arrangement in 16QAM, and the decoding circuit 14 decodes the multilevel signal represented by the symbols of the I signal and the Q signal into the decoded data.
Output as 15.

In this data converter, when the I signal 5 and the Q signal 6 separated from the received signal are output from the receiver 4, the A / D converters 7 and 8 convert these signals into a symbol clock signal. It is sampled by an integer (N) times (referred to as “over-sampling ratio: N”) to be converted into a digital signal, and the values of the I signal and the Q signal in each sample are stored in the memory 11.

The synchronous adder circuit 18 is a sample I signal 16 for one frame of data stored in the memory 11.
And the power of the Q signal 17 is added by the equation (1). i = 0, 1, 2, ..., N-1 I (): I signal Q (): Q signal SUM (): Power synchronous addition result L: Frame length N: Over sample ratio, that is, for one frame The power of the I and Q signals of each sample related to the data is calculated every N samples (i, N + i,
2N + i, ...).

The identification point detection circuit 20 outputs the synchronous addition result 19 (SUM (1), SUM (2), SUM (2),
, SUM (N-1)), the SUM showing the maximum value is detected, and the start address (denoted as ADDR) in the memory 11 is obtained from the address i of the SUM. And
Symbols are extracted from the data stored in the memory 11 by the equation (2). I ′ (i) = I (N × i + ADDR) Q ′ (i) = Q (N × i + ADDR) (2) i = 0, 1, 2, ..., N−1 I (): I signal on memory Q (): Q signal on memory I '(): Extracted I signal Q' (): Extracted Q signal N: Over sample ratio That is, every Nth counting from the sample of the start address (ADDR) Symbol extraction is performed from the sample.

The I signal 12 and the Q signal 13 from the extracted samples are sent to the decoding circuit 14, and the decoding circuit 14 decodes the 16QAM signal based on them.

[0010]

However, in the conventional data conversion apparatus, when there is a phase difference between the clocks of the transmitter and the receiver, the timing of symbol transmission on the transmission side and the start of the sampling period on the reception side are started. There is a gap with the timing of. This deviation reaches 50% of the sampling period at the maximum.

When this deviation exists, the receiving side cannot catch the optimum point of the received signal at the center of the sampling period, and the received signal power is biased to either the sampling period before or after the sampling period. Will be a considerable amount of. Therefore, there is an error in the decoded data due to intersymbol interference, an error occurs at the stage of selecting the sample for symbol extraction, or an error occurs in the process of comparing the reception level of the selected sample with a threshold value. There is a problem.

The present invention solves these conventional problems, and an object of the present invention is to provide a data converter capable of absorbing the phase difference between the clock of the transmitter and the clock of the receiver.

[0013]

Therefore, in the present invention, A / D conversion means for digitizing a received signal at a sampling frequency which is an integral multiple of a symbol clock, and storage means for storing a digital value of each sample, In a data conversion device provided with a synchronous addition means for synchronously adding the values of samples at regular intervals and a reproduction means for reproducing a symbol based on the sample giving the maximum synchronous addition value, Adjustment means is provided for comparing the synchronous addition values in the preceding and following samples and adjusting the digitization timing in the A / D conversion means based on the result.

[0014]

In this data converter, the synchronous addition value in the sample immediately before the sample that gives the maximum synchronous addition value and the synchronous addition value in the sample after the one are compared,
If there is a difference in these values, it is determined that the A / D conversion timing is shifted, and the A / D conversion timing is corrected.

By such adjustment, the phase difference between the clock of the transmitter and the clock of the receiver can be absorbed without increasing the sampling frequency.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A data conversion device according to an embodiment of the present invention is
As shown in FIG. 1, a clock shift detection circuit 22 that determines the correction direction of the clock phase difference between the transmitting side and the receiving side.
And a timing correction circuit 24 that corrects the A / D conversion timing of the A / D converters 7 and 8 based on the correction value 23 output from the clock shift detection circuit 22. Other configurations are the same as those of the conventional device (FIG. 4).

In the data converter of the embodiment, the A / D converters 7 and 8 start A / D conversion in response to the conversion start timing signal 25 output from the timing correction circuit 24, and I / D conversion is started.
Signal 5 and Q signal 6 are converted to digital signals at a sampling frequency that is an integer (N) times the symbol clock. Then, the I signal 9 and the Q signal 10 over-sampled by the A / D converters 7 and 8 are stored in the memory 11.

Further, the synchronous addition circuit 18 calculates the synchronous addition result 19 by the above equation (1) based on the data for one frame stored in the memory 11 as in the conventional device, and the discrimination point detection circuit 20 is the SUM indicating the maximum value of the synchronization detection result
The leading address of the memory 11 is obtained from the address of the symbol, and the symbol is extracted from the data stored in the memory by the equation (2).

Further, the decoding circuit 14 compares the I signal 12 and the Q signal 13 of the extracted symbol with a threshold value to reproduce the symbol, and decodes the 16QAM signal based on the reproduced symbol.

In this data converter, the process of correcting the timing between the transmitter and the receiver is performed as follows.

The clock shift detection circuit 22 is a synchronous addition circuit.
Using the synchronous addition result 19 obtained in 18, the correction direction and the correction value of the clock phase difference between transmission and reception are determined by the following equation (3). Here, SUM (M) represents the maximum value of the synchronous addition result obtained by the synchronous addition circuit 18, and M is
It shall represent the address on the memory 11 of the sample giving the maximum value SUM (M). Therefore, SUM (M-1)
Represents the result of synchronous addition in the sample of the address (M-1) immediately before the address M, and SUM (M +
1) represents the result of synchronous addition in the sample of the address (M + 1) that is one after the address M.

│SUM (M-1) -SUM (M + 1) │
When <δ, dT = 0 Further, when | SUM (M−1) −SUM (M + 1) |> δ and SUM (M−1)> SUM (M + 1), dT = −1 SUM (M + 1) )> SUM (M−1), dT = 1 (3) where δ: set value dT: correction value, that is, the sample (M−1) immediately before the sample (M) giving the maximum synchronous addition result. ) Synchronous addition result in
The result of synchronization addition in the next sample (M + 1) is compared, and when the difference between them is smaller than the set value, it is considered that the optimum point of the received signal is located substantially in the center of sample (M). , Sampling timing is not corrected.

Further, the difference between them is larger than the set value, and the result of the synchronous addition of the sample (M-1) is the sample (M-1).
+1) is larger than the synchronous addition result, the optimum point of the received signal is the sample (M-1) rather than the center of the sample (M).
Since there is a deviation to the side, the correction is made to accelerate the sampling timing.

On the contrary, when the synchronous addition result of the sample (M + 1) is larger than the synchronous addition result of the sample (M-1), the optimum point of the received signal is closer to the sample (M + 1) side than the center of the sample (M). Since there is a deviation, correction is made so that the sampling timing is delayed.

The timing correction circuit 24 corrects the A / D conversion start timing of the A / D converters 7 and 8 based on the correction value 23.

The timing correction circuit 24 is shown in FIG.
As shown in, the frame counter 26 that counts the number of clocks in one frame, and when this count exceeds a set value, the output level is switched from “L” to “H” and A
And a decoder 28 that outputs a signal 25 that prompts the conversion start of the / D converters 7 and 8.

The correction value output from the clock shift detection circuit 22 increases or decreases the set value of the decoder 28 of the timing correction circuit 24, thereby changing the switching timing of the output level of the decoder 28, and the A / D converter. The conversion start times of 7 and 8 are adjusted.

As described above, the data converter of the embodiment is
When the timing of A / D conversion in the receiver is deviated, it is automatically detected and corrected to prevent an error in decoding from occurring. In the example, 16QA
Although the M type digital communication has been described, the present invention is
Of course, it can be applied to other types of digital communication.

[0029]

As is apparent from the above description of the embodiments, the data converter of the present invention can absorb the phase difference of the clock between the transmitter and the receiver. Therefore A
The performance of the receiver can be improved without increasing the oversampling ratio of the / D converter, and the occurrence of error in decoding can be eliminated.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a data conversion device according to an embodiment of the present invention,

FIG. 2 is a configuration example of a timing correction circuit in the data conversion device,

FIG. 3 is a diagram showing an arrangement of signal points in the 16QAM system;

FIG. 4 is a block diagram showing a configuration of a conventional data conversion device.

[Explanation of symbols]

 1 transmitter 2 transmitting antenna 3 receiving antenna 4 receiver 5 I signal 6 Q signal 7, 8 A / D converter 9 digitized I signal 10 digitized Q signal 11 memory 12 symbol extracted I signal 13 Symbol extracted Q signal 14 Data decoding circuit 15 Decoded data 16 I signal stored in memory 17 Q signal stored in memory 18 Synchronous addition circuit 19 Synchronous addition result 20 Discrimination point detection circuit 21 Start address 22 Clock deviation detection circuit 23 Correction value 24 Timing correction circuit 25 Conversion start timing signal 26 Frame counter 27 Count value 28 Decoder

Claims (1)

[Claims] 1. A / D conversion means for digitizing a received signal at a sampling frequency which is an integral multiple of a symbol clock, storage means for storing a digital value of each sample, and synchronization of the values of the samples at regular intervals. In a data conversion device comprising a synchronous addition means for adding and a reproducing means for reproducing a symbol based on a sample giving a maximum synchronous addition value, the synchronous addition values in samples before and after the sample giving a maximum synchronous addition value And a adjusting means for adjusting the digitization timing in the A / D converting means based on the result of the comparison.