JPH06296126A - Control pulse signal generating circuit - Google Patents

Abstract

PURPOSE:To provide the control pulse signal generating circuit which is able to provide a control pulse signal output in response to a rising of a power supply voltage, whose output is made stable to a predetermined level quickly after the control pulse signal is generated thereby giving no hindrance to the operation of its internal circuit. CONSTITUTION:A voltage depending on a power supply voltage is generated at a node N2. An inverter circuit 13 produces a high level when the power supply voltage Vcc is small and produces a low level when the power supply voltage Vcc is high. A pulse generating section 12 generates a control pulse signal initializing its internal circuit when the power supply voltage gets larger than a predetermined voltage and stops the production of the control pulse signal after lapse of a predetermined time after an output of the inverter circuit 13 changes from the high level to the low level. A transistor(TR) Q4 interrupts a current path in response to the stop of the production of the control pulse signal and a TR Q5 rapidly sets an output of the inverter circuit 13 to a low level thereby stabilizing the internal circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control pulse signal generating circuit used for initializing internal circuits such as flip-flops.

[0002]

2. Description of the Related Art A control pulse signal generating circuit for initial setting outputs a pulse signal having a predetermined pulse width to an internal circuit such as a flip-flop when power is turned on, which requires initial setting.

However, in the configuration of the conventional control pulse generating circuit, the pulse width and the pulse height of the output pulse are changed according to the rise time of the power supply voltage.
If the rise time of the power supply voltage changes, the width and height of the output pulse also change significantly, which is a drawback.

Generally, the rise time of the power supply voltage supplied to the semiconductor integrated circuit depends on the peripheral system, and the change in the rise time due to the difference in the peripheral system is about several hundred nanoseconds to several milliseconds. . Therefore,
A conventional control pulse generation circuit supplies a control pulse signal having a predetermined pulse width and a voltage value of a pulse which can be initialized to an internal circuit except for a rise time of a certain specific system, that is, a certain power supply voltage. I couldn't.

Further, it is necessary that the control pulse signal generating circuit immediately outputs a predetermined level after generating the control pulse signal so as not to disturb the stable operation of the internal circuit. However, the output level of the conventional control pulse signal generation circuit may fluctuate even after the control pulse signal is generated, which may cause the internal circuit to malfunction.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and it is possible to output a control pulse signal for a predetermined time regardless of the rise of the power supply voltage, and An object of the present invention is to provide a control pulse signal generation circuit in which the output is quickly stabilized at a predetermined level after the control pulse signal is generated and the operation of the internal circuit is not hindered.

[0007]

That is, a control pulse signal generating circuit of the present invention is connected between a power supply voltage supply terminal and a first node, a source is connected to the power supply voltage supply terminal side, and a drain is connected. Is connected to the first node side,
At least one P-channel MOS transistor having a gate connected to the drain and a substrate connected to the source, and at least one drain and gate connected to the first node and a source connected to a reference potential. Voltage generating circuit having two N-channel MOS transistors, having a current path from the power-supply voltage supply terminal to the reference potential through the P-channel MOS transistor and the N-channel MOS transistor, and generating a voltage according to the power-supply voltage. And a power supply voltage connected to the first node and supplied to the power supply voltage supply terminal is smaller than a predetermined value, a signal of a first logic level is generated, and the power supply voltage is the predetermined voltage. And a sensing means for generating a signal of a second logic level opposite to the first logic level. And a control signal for initializing an internal circuit when the power supply voltage becomes higher than a predetermined value, and the signal generated by the detection means changes from the first logic level to the second logic level. The signal generation means for stopping the control signal after a lapse of a predetermined period from the change of the logic level to the above is connected to the current path of the voltage generation means, and the power supply voltage becomes larger than the predetermined value. Later, in response to the stop of the control signal from the signal generating means, it is connected between the interrupting means for interrupting the current path, the first node and the power supply voltage supply terminal, and is controlled by the signal generating means. Holding means for holding the signal generated by the sensing means at a second logic level in response to the stoppage of the signal.

[0008]

That is, in the voltage detecting means, the voltage generating means generates a voltage according to the power supply voltage. The detection means generates a signal of a first logic level when the power supply voltage supplied to the power supply voltage supply terminal is lower than a predetermined value, and the first means when the power supply voltage is higher than the predetermined value. Generates a signal of a second logic level opposite to the logic level of. The signal generating means generates a control signal for initializing the internal circuit when the power supply voltage becomes higher than a predetermined value, and the signal generated by the detecting means changes from the first logic level to the second logic level.
The control signal is stopped when a predetermined period of time elapses after the logic level is changed to. After the power supply voltage becomes higher than a predetermined value, the cutoff means cuts off the current path in response to the stop of the control signal from the signal generation means, thereby reducing current consumption. The holding means quickly holds the signal generated by the detecting means at the second logic level in response to the stop of the control signal from the signal generating means, and secures stable operation of the internal circuit.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a control pulse signal generating circuit according to an embodiment of the present invention. The control pulse signal generating circuit is composed of a power supply voltage detecting section 11 and a pulse generating section 12.

In the power supply voltage detector 11, the P channel M is provided between the power supply voltage terminal Vcc and the ground terminal Vss.
The current paths between the sources and drains of the OS transistors Q1 and Q2 and the N-channel MOS transistors Q3 and Q4 are connected in series.

In this case, the back gate (substrate) of the transistor Q1 is connected to the power supply voltage terminal Vcc, and its gate is connected to the node N1 which is a connection point between the transistors Q1 and Q2. The back gate of the transistor Q2 is also connected to the node N1, and the gate of the transistor Q2 has transistors Q2 and Q3.
It is connected to the node N2 which is a connection point with.

That is, since the back gates of the P-channel MOS transistors Q1 and Q2 are separated from each other and the back gates are connected to the sources of the transistors, the transistors due to the substrate bias effect even if the power supply voltage changes. Fluctuations in the threshold voltage of Q1 and Q2 are suppressed.

The gate of the transistor Q3 is also connected to the node N2, and these transistors Q1, Q2 and Q3 form a voltage generator for generating a voltage proportional to the power supply voltage.

Since the output potential from the pulse generator 12 which will be described later is supplied to the gate of the transistor Q4, the transistor Q4 always operates as a triode when the power is turned on. Therefore, when the potential of the power supply voltage terminal Vcc becomes equal to or higher than the sum (absolute value) of the threshold voltages of the transistors Q1, Q2, Q3, the transistors Q1, Q
Each of 2 and Q3 operates as a pentode, and a current proportional to the square of the power supply voltage flows from the power supply voltage terminal Vcc to the ground terminal Vss. As a result, a potential proportional to the conductance ratio of each transistor Q1, Q2, Q3 is applied to each node N1, N2.

A P channel NOS is provided at the node N2.
The drain of the transistor Q5 is connected, the source of the transistor Q5 is supplied to the power supply voltage terminal Vcc, and the gate thereof is supplied with the output potential from the pulse generator 12.

The node N2 is also connected to the other end of the capacitor C1 having one end connected to the ground terminal Vss and the input of the inverter circuit 13. The inverter circuit 13 is a CM including a P-channel MOS transistor Q6 and an N-channel MOS transistor Q7 connected in series between a power supply voltage terminal Vcc and a ground terminal Vss.
It is an OS inverter circuit, and its output is connected to one end of the capacitor C2 as a node N3. And
The other end of the capacitor C2 is connected to the power supply voltage terminal Vcc.

That is, since the node N2 is set to the ground potential Vss by the capacitor C1 and the node N3 is set to the power supply potential Vcc by the capacitor C2, the potential of the node N2 rises as the power supply voltage rises. Then, when the voltage exceeds a predetermined voltage value, that is, the circuit threshold value of the inverter circuit 13, the potential of the node N3 which is the output of the inverter circuit 13 is inverted from the "1" level to the "0" level. This inverted signal is supplied to the power supply voltage detection unit 11
Is sent to the pulse generation unit 12 as a power supply voltage detection signal.

The pulse generator 12 is provided with a plurality of, for example, four CMOS inverter circuits 14 to 17 and capacitors C3 to C6.
Is composed of a P-channel MOS transistor Q8 and an N-channel transistor Q9 connected in series between the power supply voltage terminal Vcc and the ground terminal Vss. The input of the inverter circuit 14 is connected to the output of the power supply voltage detection unit 11, that is, the node N3, and the output is connected to the other end of the capacitor C3 whose one end is connected to the ground terminal Vss as the node N4. .

A P-channel MO connected in series between the power supply voltage terminal Vcc and the ground terminal Vss is connected to the node N4.
The input of an inverter circuit 15 composed of an S-transistor Q10 and an N-channel MOS transistor Q11 is connected. The output of this inverter circuit 15 is a node N5, and the other end of a capacitor C4 whose one end is connected to a power supply voltage terminal Vcc. Connected to the end.

The node N5 is a P-channel MO connected in series between the power supply voltage terminal Vcc and the ground terminal Vss.
The input of an inverter circuit 16 composed of an S-transistor Q12 and an N-channel MOS transistor Q13 is connected, and the output of this inverter circuit 16 serves as a node N6, and the other end of a capacitor C5 whose one end is connected to a ground terminal Vss. It is connected to the. The node N6 is connected to the input of an inverter circuit 17 composed of a P-channel MOS transistor Q14 and an N-channel MOS transistor Q15 connected in series between a power supply voltage terminal Vcc and a ground terminal Vss. The output of the inverter circuit 17 is connected as a node N7 to the other end of the capacitor C6 whose one end is connected to the power supply voltage terminal Vcc.

The potential of the node N7 is output to an internal circuit such as a flip-flop as an output of the control pulse signal generating circuit, and at the same time, the N channel MO of the power supply voltage detecting section 11 is outputted.
It is supplied to the gates of the S transistor Q4 and the P channel MOS transistor Q5, respectively.

That is, in the pulse generator 12 configured as described above, when the potential of the node N3 which is the output of the power supply voltage detector 11 is inverted from the "1" level to the "0" level, the pulse generation is performed. Inverter circuit 1 in section 12
Output nodes N5, N6, N7 of 4, 15, 16, 17
Are capacitors C3, C4, C attached to each output node
The inversion operation is performed in a chain reaction with a certain delay time sequentially from the potential initially set by 5 and C6.

Regarding the node N7 which is the output of the control pulse signal generating circuit, the potential of the node N7 rises when the power is first turned on by the capacitor C6 having one end connected to the power supply voltage terminal Vcc. It is pulled up in association with the change to "1" level from "0" level. Then, the power supply voltage exceeds a predetermined potential, and the potential of the node N3, which is the output of the power supply voltage detection circuit unit 11, is "1".
When the level is inverted to the “0” level, the potential of the node N7 becomes “after a predetermined delay time due to the time constant of the capacitors C3, C4, C5 and C6 connected to the nodes N4, N5, N6 and N7”. It is inverted from the 1 ”level to the“ 0 ”level. That is, the inversion timing of the inversion signal output from the power supply voltage detection unit 11 is delayed by a predetermined time, and the control pulse signal having the pulse width corresponding to this delay time is output from the pulse generation unit 12.

When the potential of the node N7 is inverted in this way, the N channel MO of the power supply voltage detection circuit unit 11 is
Since the S transistor Q4 is turned off, the P channel transistors Q1 and Q2 and the N channel transistor Q
The DC current path formed by Q3 and Q4 is cut off.
Further, the P-channel MOS transistor Q5 is turned on, the potential of the node N2 is rapidly raised to the level of the power supply voltage, and the voltage is held. As a result, the operation of the inverter circuit 13 of the power supply voltage detection unit 11 becomes stable, and the potential of the output node N3 surely becomes "0" level, and the control pulse signal generation circuit has a stable point.

In this way, the control pulse generating circuit
Regardless of the rise time of the power supply voltage, the pulse width in the period from when the level of the power supply voltage reaches a predetermined voltage to when the potential of the node N7 is inverted and the pulse height almost equal to the power supply voltage at this time are set. It becomes possible to output the control pulse signal which has.

2 to 4 show changes in the potential at each node of the control pulse signal generating circuit shown in FIG. 1. FIG. 2 shows the rising state of the power supply voltage supplied to the power supply voltage terminal Vcc. 3 is an enlarged view at time t, and FIG. 4 shows a case where the rising is relatively steep. As can be seen from FIG. 4, when the power source rises rapidly, a predetermined pulse width is obtained after the power source rises. When the power supply rises relatively slowly, as shown in FIGS. 2 and 3, the control pulse signal obtained at the node N7 rises together with the power supply until the power supply starts to rise and reaches a predetermined value. A predetermined pulse width is obtained after reaching a predetermined power supply value. Therefore, since the power supply is set to a predetermined voltage value and a pulse is generated for a predetermined time after the internal circuit starts operating, the internal circuit can be surely initialized. Therefore, it becomes possible to output a control signal having a desired pulse width to an internal circuit such as a flip-flop.

In this embodiment, four inverter circuits 14, 15, 16 and 17 are provided in the pulse generator 12, but the number of inverter circuits provided in the pulse generator 12 is desired. The number of control signals is determined according to the output time of the control signal, and any number may be used. Of course, the pulse width of the control pulse signal can be set arbitrarily by changing the capacitances of the capacitors C1 to C6.

The minimum power supply voltage of the semiconductor integrated circuit can be set by adjusting the gate length and gate width of the P channel channel transistors Q1 and Q2 and the N channel transistor Q3.

[0029]

As described above, according to the present invention, the control pulse signal can be output for a predetermined time regardless of the rise of the power supply voltage, and the control pulse signal is output after the control pulse signal is generated. Quickly stabilizes to a predetermined level,
It is possible to provide a control pulse signal generation circuit that does not hinder the operation of the internal circuit.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a control pulse signal generation circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing an operation of the control pulse signal generation circuit shown in FIG.

FIG. 3 is a diagram showing an operation of the control pulse signal generation circuit shown in FIG. 1.

FIG. 4 is a diagram showing an operation of the control pulse signal generation circuit shown in FIG. 1.

[Explanation of Codes] 11 ... Power supply voltage detection unit, 12 ... Pulse generation unit, 13 to 1
7 ... Inverter circuit, Q1, Q2, Q5, Q6, Q8,
Q10, Q12, Q14 ... P-channel MOS transistors, Q3, Q4, Q7, Q9, Q11, Q13, Q1
5 ... N-channel MOS transistors, C1 to C6 ... Capacitors.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Hideo Kato, No. 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Inside the Tamagawa Plant of Toshiba Corporation (72) Hiroshi Iwahashi Komukai-cho, Kouki-ku, Kawasaki-shi, Kanagawa No. 1 Incorporation company in Toshiba Tamagawa Plant (72) Inventor Masamichi Asano No. 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki City, Kanagawa Prefecture Incorporated company in Toshiba Tamagawa Plant (72) Incorporated Shinichi Kikuchi Higashi, Kawasaki-ku, Kawasaki City, Kanagawa Prefecture 2-11 Tamachi, Toshiba Microcomputer Engineering Co., Ltd. (72) Inventor Akira Narita 1-13-9 Shibuya, Shibuya-ku, Tokyo Shibuya Takugin Building Tosback Computer System Co., Ltd.

Claims (1)

[Claims] 1. A power supply voltage supply terminal is connected between the first node and a source, a source is connected to the power supply voltage supply terminal side,
At least one P-channel MOS transistor having a drain connected to the first node side, a gate connected to the drain, and a substrate connected to the source; and a drain and a gate connected to the first node And at least one N whose source is connected to the reference potential
A voltage generating unit having a channel MOS transistor, having a current path from the power supply voltage supply terminal to the reference potential through the P-channel MOS transistor and the N-channel MOS transistor, and generating a voltage according to the power supply voltage. When the power supply voltage connected to the first node and supplied to the power supply voltage supply terminal is smaller than a predetermined value, a signal of a first logic level is generated, and the power supply voltage is the predetermined value. Voltage detection means having a second logic level opposite to the first logic level, and a voltage detection means having a detection means for generating a signal having a second logic level opposite to the first logic level, and an internal circuit when the power supply voltage exceeds a predetermined value. A control signal for initializing the signal is generated, and the signal generated by the detection means changes from the first logic level to the second logic level, and then a predetermined signal is generated. A signal generation unit that stops the control signal when the period has passed, and is connected to a current path of the voltage generation unit, and the control signal from the signal generation unit after the power supply voltage becomes larger than the predetermined value. A cutoff unit that cuts off the current path in response to the stop of the current path, and is connected between the first node and the power supply voltage supply terminal,
A control pulse signal generation circuit comprising: a holding unit that holds the signal generated by the detection unit at a second logic level in response to the stop of the control signal from the signal generation unit.