JPH06267285A - Non-volatile semiconductor memory and method for using it - Google Patents

Abstract

(57) [Abstract] [Purpose] To increase the storage capacity of EPROM. [Structure] 0V to 10V, 11V, 12V every 1ms
A variable voltage generating circuit 6 generates a stepwise voltage whose level changes stepwise, and this stepwise voltage is applied to the control gate of a predetermined memory cell through the selected word line of the memory cell array 1. Then, the pulse generation circuit 7 is synchronized with the timing when the voltage of the desired level is applied.
To the selected bit line, apply a voltage of 8.5V to 0.8m
It is applied only for s, and hot electrons are injected into the floating gate of the memory cell to change the threshold value of the memory cell. The change state of the threshold value is changed to "01", "10", "1" according to the voltage level of the staircase voltage.
The 1 ”state is set, and the state in which the memory cell is not written is set to the“ 00 ”state. Thus, 4-level data can be stored in one memory cell.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device capable of electrically writing information and a method of using the same.

[0002]

2. Description of the Related Art EPR is a type of non-volatile semiconductor memory device.
OM (Erasable and Programmable Read Only Memory)
There is. This EPROM is a read-only memory (ROM) in which stored information can be erased by irradiation of ultraviolet rays and information can be electrically and repeatedly written.

FIG. 3 shows a state of electrical connection of a typical EPROM for four memory cells.

Each of the memory cells 10 to 13 has floating gates 110 to 113 having no electrodes.
The word line 100 is connected to the control gates of the memory cells 10 and 11, respectively, and the word line 101 is connected to the control gates of the memory cells 12 and 13, respectively. However, in reality, each word line and each control gate are integrally formed of, for example, polysilicon, and the word line itself constitutes the control gate in the region of each memory cell. On the other hand, memory cells 10 and 1
The bit line 102 is connected to the drains of the memory cells 2 and 2, and the bit line 103 is connected to the drains of the memory cells 11 and 13, respectively. Further, the sources of the memory cells 10 to 13 are connected to the common source line 104.

In the EPROM having such a structure, conventionally, for example, when writing to the memory cell 10, the potential of the word line 100 is set to 12 V, the potentials of the other word lines are set to 0 V, and the bit line 102 is used. Is set to 5V, the potentials of the other bit lines are set to 0V, and the potential of the source line 104 is set to 0V.

At this time, assuming that the capacitive coupling coefficient (coupling ratio) between the control gate and the floating gate in each memory cell is 0.6, a potential of about 7 V is induced in the floating gate 110 of the memory cell 10. . As a result, a channel is formed between the drain and source of the memory cell 10, high energy electrons (hot electrons) are generated near the drain due to the high gate voltage and drain voltage, and these hot electrons are generated in the silicon substrate. Is injected into the floating gate 110 across a potential barrier (for example, 3.2 eV in the case of electrons) between the gate oxide film and the gate oxide film.

Since the floating gate 110 is surrounded by an oxide film having a very low conductivity, the electrons injected in this manner are floating even after the voltage of the word line 100 and the bit line 102 is released. Gate 110
It remains semi-permanently in, and the memory state is retained. This storage state is data "0". On the other hand, in a memory cell to which a voltage is not applied to either the word line or the bit line, electrons are not injected into the floating gate, and the storage state becomes data “1”.

When reading data from the memory cell 10, the potential of the word line 100 is set to 5 V, for example.
And the potentials of the other word lines are set to 0V, the potentials of the bit lines 102 are set to 1V, and the potentials of the other bit lines are set to 0V, respectively.
The potential of 04 is set to 0V.

Then, when the memory state of the memory cell 10 is "0" and its threshold voltage is high (for example, 6 to 8 V), no current flows between the drain and source of the memory cell, but the memory state is Is 1 and the threshold voltage is low (for example, 2 to 3 V), a current flows between the drain and source of the memory cell. Then, by comparing this difference in current with the current value of the dummy cell, the storage state of the memory cell 10 is detected and data is read.

[0010]

In the conventional EPROM, as described above, only one memory cell is provided with two storage states, "0" and "1". That is,
The unit memory cell was used only for storing 1-bit (binary) data. Therefore, there is a drawback that the amount of information stored in the entire memory cell array is small.

Therefore, an object of the present invention is to provide a non-volatile semiconductor memory device which can increase its storage capacity without increasing the number of memory cells and a method of using the same.

[0012]

In order to solve the above-mentioned problems, the present invention provides a memory cell having a double gate structure of a control gate and a floating gate by injecting charges into the floating gate of the memory cell. And a drain formed in the memory cell in a nonvolatile semiconductor memory device that changes the threshold voltage of the memory cell and uses the changed state of the threshold voltage for storing information. A bit line connected to the bit line, a write voltage generation circuit that applies a voltage that changes to at least three levels to the word line, and a write pulse generation circuit that applies a pulsed voltage to the bit line at a predetermined timing. Have.

In a preferred aspect of the present invention, the write voltage generating circuit generates a voltage that changes stepwise at a level of 2 ⁿ (n ≧ 2) stages.

In the method of using the nonvolatile semiconductor memory device of the present invention, at least a selected word line of the plurality of word lines forming the column line or the row line of the matrix composed of the plurality of memory cells is at least selected. When a write voltage that changes in three levels is applied and a write voltage of a desired level is applied to the selected word line, a plurality of bit lines that form a row line or a column line of the matrix are applied. A pulsed voltage is applied to one of the selected bit lines, whereby a floating gate of the memory cell selected by the selected word line and the selected bit line is applied to the selected bit line. When the pulsed voltage is applied, a predetermined amount of charge corresponding to the level of the write voltage applied to the selected word line is applied. Type in the selected memory cell, and stores the information corresponding to the level of the write voltage.

In a preferred embodiment of the present invention,
A voltage that changes stepwise at a level of 2 ⁿ (n ≧ 2) is applied to the selected word line.

[0016]

In the non-volatile semiconductor memory device and the method of writing the same according to the present invention, data is written into a unit memory cell by using three or more values of data, for example, a write voltage that changes to a level of 2 ⁿ (n ≧ 2) stages. N bits (2n
Since (value) data can be stored, the storage capacity of the entire device can be increased without increasing the number of memory cells.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings.

FIG. 1A shows an EPRO to which the present invention is applied.
The main structure of M is shown.

In the figure, the configuration of each memory cell that constitutes the memory cell array 1 and the connection between each memory cell and the word line, bit line and source line are the same as those described with reference to FIG. The word line connected to the control gate of each memory cell is connected to the column decoder 2, while the bit line connected to the drain of each memory cell is connected to the row decoder 3 via the row selector 4. .

Then, the address signal input through the address buffer 5 is sent to the decoders 2 and 3, and the decoders 2 and 3 respectively supply column lines (word lines).
The row line (bit line) is selected.

A variable voltage generating circuit 6 for generating a voltage whose level changes stepwise is connected to each word line of the memory cell array 1 through a column decoder 2 and a pulse generating circuit for generating a pulsed voltage is generated. The circuit 7 is connected to each bit line of the memory cell array 1 via the row selector 4. In the figure, reference numeral 8 is a read circuit.

Next, the writing operation of the EPROM of this embodiment will be described with reference to FIGS. 1A and 1B and FIG.

Now, when writing to the memory cell 10 of FIG. 3, as shown in FIG.
The variable voltage generating circuit 6 built in the semiconductor chip generates a stepwise voltage whose level changes stepwisely by 10V, 11V, and 12V for each, and the stepwise voltage is generated by the column decoder 2
Is applied to the selected word line 100, and the potentials of the other word lines are all set to 0V.

Then, for example, 11 V is applied to the word line 100.
A voltage of 8.5 V, for example, is applied from the pulse generation circuit 7 to the bit line 102 selected by the row decoder 3 for 0.8 ms in accordance with the timing at which the voltage of 1 is applied. Set all to 0V. This application time can be set to an appropriate value between 0.5 and 1 ms. Further, the potential of the common source 104 is set to 0V.

As a result, a channel is formed between the drain and source of the memory cell 10, and hot electrons generated near the drain due to the high gate voltage and drain voltage exceed the potential barrier between the silicon and the gate oxide film. Information is written by being injected into the floating gate 110. As a result, the threshold voltage of the memory cell 10 becomes about 4V, and this state is set to the "10" state.

Similarly, the bit line 1 is synchronized with the timing when the voltage of 10 V is applied to the word line 100.
When a pulsed voltage of 8.5 V is applied to 02, the threshold voltage of the memory cell 10 becomes about 3 V, and this state is set to "0".
1 ”state.

Further, when a pulsed voltage of 8.5 V is applied to the bit line 102 at the timing when the voltage of 12 V is applied to the word line 100, the memory cell 10
Has a threshold voltage of about 5 V, and this state is referred to as "11" state.

Then, the state where the memory cell 10 is not written is set to the "00" state. The threshold voltage of the memory cell 10 in this state is about 2V.

As described above, the programming method uses the channel hot electron injection method and utilizes the characteristic that the threshold voltage (V _th ) after programming is changed by the voltage (V _CG ) applied to the control gate. . FIG. 4 shows the relationship between the writing time and the threshold voltage after writing when the voltage applied to the control gate is changed. By applying the stepwise voltage generated from the built-in circuit to the selected word line and controlling the timing of the pulse applied to the bit line, it is possible to set four types of threshold voltage (V _th ) after programming. Become. As for the set value of the threshold voltage, the state where no writing is performed is set to one state, and the other states are set every 3 [V] to 1 [V].

Next, the read operation of the EPROM of this embodiment will be described.

Now, when reading the memory cell 10, 2.5V, 3.5V, and 4.5V from 0V every 1 ms.
A variable voltage generating circuit 6 generates a stepwise voltage whose level changes in a stepwise manner with V, and the stepwise voltage is generated by the word line 100.
Is applied to all the other word lines to 0V.
Further, the potential of the bit line 102 is set to, for example, 1V, the potentials of the other bit lines are set to 0V, and the potential of the common source 104 is set to 0V.

If a current flows between the drain and source of the memory cell 10 when the voltage of 2.5 V is applied to the word line 100, the read circuit 8 is set to "0".
The data of 0 "is output. In addition, 2.
When no current flows between the drain and the source when the voltage of 5 V is applied, and when a current flows when the voltage of 3.5 V is applied, the read circuit 8 outputs the data "01". Further, when no current flows between the drain and the source even when the voltage of 3.5 V is applied to the word line 100, and when the current first flows when the voltage of 4.5 V is applied, the read circuit 8 Outputs the data of "10". Then, when no current flows even when the voltage of 4.5 V is applied, the reading circuit 8 outputs "1".
The data of 1 "is output.

As described above, the EPR of this embodiment is
In the OM, four "00" to "11" are stored in one memory cell.
A value, or 2-bit data, can be stored and read.

It should be noted that the erasing of the stored state is performed collectively for all the memory cells by irradiation of ultraviolet rays, which is well known in the prior art.

Further, specific voltage values are shown in the above embodiments. These voltage values are determined by the structure of the memory cell,
In particular, it should be appropriately changed depending on the capacitance of the gate oxide film and the interlayer insulating film and the value of the capacitive coupling coefficient (coupling ratio).

Next, using the equivalent circuit of the memory cell shown in FIG. 2, it will be explained in principle that the threshold voltage after writing changes depending on the voltage applied to the control gate.

Now, the potentials of the control gate, floating gate, drain, source and substrate are respectively set to V _CG ,
V _FG , V _D , V _S, and V _SUB, and the capacitances between the control gate and the floating gate, between the floating gate and the substrate, between the floating gate and the drain, and between the floating gate and the source are C ₂ and C, respectively.
₁ , C ₄ and C ₃ .

If the amount of charge accumulated in the floating gate is Q, then Q = C ₂ (V _FG −V _CG ) + C ₁ (V _FG −V _SUB ) + C ₃ (V _FG ) according to the law of conservation of charge. −V _S ) + C ₄ (V _FG −V _D ) ... (1)

When V _S = V _SUB = 0, V _FG = (C ₂ · V _CG + C ₄ · V _D + Q) / C _T (2) where C _T = C ₁ + C ₂ + C ₃ It becomes + C ₄ .

When the threshold voltages of the transistor viewed from the control gate and the floating gate are V _T and V _FT , respectively, when Q = 0, V _FT = (C ₂ · V _T + C ₄ · V _D ). / C _T (3) When Q = ΔQ, V _FT ′ = (C ₂ · V _T ′ + C ₄ · V _D + ΔQ) / C _T (4) holds, respectively.

Since the threshold voltage of the transistor seen from the floating gate is constant regardless of the value of Q, V _FT = V _FT ′.

Therefore, from the formula (4) -the formula (3), C ₂ (V _T ′ −V _T ) / C _T = ΔQ / C _T (5)

Therefore, if V _T −V _T ′ = ΔV _T , then C ₂ · ΔV _T = −ΔQ (6)

By the way, by increasing V _CG by a small amount, V _{CG
When CG} + ΔV _CG , Q also becomes Q + ΔQ, so (2)
The formula is V _FG + ΔV _FG = {C ₂ (V _CG + ΔV _CG ) + C ₄ · V _D + (Q + ΔQ)} / C _T (7)

[0045] Thus, (7) - the equation _{(2), ΔV FG = (C 2 ·} ΔV CG + ΔQ) / C T ... (8).

By substituting the equation (6) into the equation (8), ΔV _FG = C ₂ (ΔV _CG −ΔV _T ) / C _T (9)

Here, ΔV _FG = 0 after a sufficient time has elapsed for injecting charges into the floating gate.

Therefore, ΔV _CG = ΔV _T (10)

From this, it can be seen that the threshold voltage after writing changes depending on the voltage applied to the control gate.

[0050]

According to the present invention, a unit memory cell of a nonvolatile semiconductor memory device such as an EPROM has three or more values, for example, n.
Since (n ≧ 2) -bit data can be stored, a large storage capacity can be obtained without particularly increasing the number of memory cells.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a configuration of main parts of an EPROM according to an embodiment of the present invention and a timing chart showing an applied voltage during writing.

FIG. 2 is an equivalent circuit diagram of a unit memory cell of an EPROM.

FIG. 3 is an electrical connection diagram of four memory cells of an EPROM.

FIG. 4 is a graph showing the relationship between the writing time and the threshold voltage after writing when the voltage applied to the control gate is changed.

[Explanation of symbols]

1 memory cell array 2 column decoder 3 row decoder 6 variable voltage generation circuit 7 pulse generation circuit 8 read circuit 10, 11, 12, 13 memory cell 100, 101 word line (control gate) 102, 103 bit line 104 source line 110, 111 , 112, 113 Floating gate

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasuo Sato 5-10-1 Fuchinobe, Sagamihara City Electronics Research Laboratories, Nippon Steel (72) Inventor Yuichi Egawa 5-10-1, Fuchinobe, Sagamihara Electronics Co., Ltd. Electronics Research Laboratory

Claims (4)

[Claims] 1. A threshold voltage of a memory cell is changed by injecting charges into the floating gate of a memory cell having a double gate structure of a control gate and a floating gate, and the change state of the threshold voltage is changed. In a non-volatile semiconductor memory device that uses data for storing information, a word line connected to the control gate, a bit line connected to a drain formed in the memory cell, and a voltage changing to at least three levels. A non-volatile semiconductor memory device, comprising: a write voltage generating circuit for applying a pulse voltage to the word line; and a write pulse generating circuit for applying a pulsed voltage to the bit line at a predetermined timing. 2. The write voltage generating circuit is 2 ⁿ (n
2. The non-volatile semiconductor memory device according to claim 1, wherein a voltage that changes stepwise at a level of ≧ 2) is generated. 3. A write voltage that changes in at least three levels is applied to a selected word line among a plurality of word lines that form a column line or a row line of a matrix composed of a plurality of memory cells. When a write voltage of a desired level is applied to the selected word line, a pulsed voltage is applied to a selected bit line of the plurality of bit lines forming a row line or a column line of the matrix. As a result, the selected voltage is applied to the floating gate of the memory cell selected by the selected word line and the selected bit line when the pulsed voltage is applied to the selected bit line. A predetermined amount of charge corresponding to the level of the write voltage applied to the selected word line is injected, and the write voltage is applied to the selected memory cell. Using the non-volatile semiconductor memory device according to claim 1, wherein the level that so as to store the information corresponding to the. 4. The selected word line has 2 ⁿ (n ≧ n)
4. The method of using a nonvolatile semiconductor memory device according to claim 3, wherein a voltage that changes stepwise is applied to the level of 2).