KR920011000B1 - Non-erasible semiconductor memory circuit - Google Patents

Abstract

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Description

Nonvolatile Semiconductor Memory

1 and 2 are memory circuit diagrams of respective embodiments according to the present invention.

3 and 4 are circuit diagrams detailing some of the illustrated embodiment circuits of FIGS. 1 and 2.

FIG. 5A is a pattern plan view of the memory cell portion of the embodiment circuit shown in FIGS. 1 and 2. FIG.

FIG. 5B is a cross-sectional view when the pattern plan view of FIG. 5A is cut along a line A-A '. FIG.

Fig. 5C is a cross sectional view when the pattern plan view of Fig. 5A is cut along the line B-B '.

6 is an equivalent circuit diagram of a memory cell unit shown in FIG. 5;

FIG. 7 is an equivalent circuit diagram of a capacitance system of the memory cell unit shown in FIG.

FIG. 8 is a circuit diagram in the case where the memory cell portion shown in FIG. 6 is arranged in the form of a 4-bit matrix.

FIG. 9 is a table showing voltage compression of the erase gate and the floating gate in the memory cell unit shown in FIG.

10 is a conventional memory circuit diagram.

* Explanation of symbols for main parts of the drawings

11 floating gate 12 eliminating gate

13 control gate 14 P-type substrate

15 source 16: drain

17 connection part 18 data line

19 to 23 gate insulating film 24 field insulating film

25 interlayer insulating film 30 memory cell

31: memory cell array 32: row decoder

33: thermal decoder 34-1 to 34n: thermal select transistor

35 bus line 36 data input circuit

37: sense amplifier circuit 38: data output circuit

39: erase booster circuit 40-1 to 40-k: hang decoder

42-1 to 42k: block memory cell array 43-1 to 43-k: erase gate decoder

44,45: address buffer 46-1,46-k: erase gate decoder

47: address buffer for erasing 50: decoder

WL1-1 to WLk-1: word line DL1 to DLn: data line

CL1 to CLn: Heat select line EL1 to ELk: Small psoriasis

M1 to M4: Memory cells RA1 to RAj: Hang address

[HE]: step-up voltage

[Industrial use]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory capable of electrically erasing data, and in particular, to shorten the voltage stress time of an unselected memory cell, thereby preventing false writes and erases, thereby improving reliability. The present invention relates to a nonvolatile semiconductor memory capable of doing so.

[Traditional Technology and Problems]

EEPROM (Electrically Erasable and Programmable ROM), which can erase data and erase data electrically, can be erased by electric signal when assembled on sidewalks unlike UV erasure type EPROM. Therefore, the demand for control, IC card (memory card), etc. is increasing rapidly. In particular, a memory cell having a configuration as shown in FIG. 5 is used as an EEPROM capable of realizing a large capacity. FIG. 5A is a pattern plan view, and FIG. 5B is a pattern plan view of FIG. 5C is a cross-sectional view when the pattern plan view of FIG. 5A is cut along the line B-B '.

In FIG. 5, reference numeral 11 denotes a floating gate composed of a polysilicon layer of a first layer, an erase gate composed of a polycrystalline silicon layer of a second layer, and 13 a control gate composed of a polycrystalline silicon layer of a third layer. In this case, they are also used as word lines of the memory cells of the control gate 13.

In Fig. 5, reference numeral 14 denotes a P-type substrate, 15 and 16 denote sources and drains of an N ⁺ type diffusion layer formed on the P-type substrate 14, 17 denotes a connection portion, and 18 denotes this connection portion 17. A data line made of an aluminum layer connected to the drain 16 by a medium, 19 is a gate insulating film of the floating gate transistor portion, 20 is a gate insulating film formed between the floating gate 11 and the erase gate 12, and 21 is a floating gate 11 ) And a gate insulating film formed between the control gate 13 and the gate insulating film 21 is composed of a three-layer structure film of an oxide-nitride-oxide structure. Reference numeral 22 denotes a gate insulating film formed between the erase gate 12 and the control gate 13, and this insulating film also has an ONO structure. Reference numeral 23 denotes a gate insulating film of the select transistor portion which uses the polysilicon layer of the third layer as a gate electrode, 24 is a field insulating film, and 25 is an interlayer insulating film.

The equivalent circuit of the memory cell shown in FIG. 5 is shown in FIG. 16 and the equivalent circuit of the capacitance system is shown in FIG.

In Fig. 6, reference numeral V _D denotes a drain voltage, V _S denotes a source voltage, V _FC denotes a floating gate voltage, V _EG denotes an erase gate voltage, and V _CG denotes a control gate voltage. In Fig. 7, reference numeral C _FC denotes a capacitance between the floating gate 11 and the control gate 13, C _FE denotes a capacitance between the floating gate 11 and the erase gate 12, and C _FD denotes a floating gate ( 11) represents the capacitance between the drain 16 and C _FS , respectively, and the other capacitance seen from the floating gate 11. In such a capacity system, the initial value Q (I) of the charge amount accumulated in all capacitances is given by the following equation.

If the sum of all capacities is C _T , C _T is given by the following equation.

Therefore, the floating gate voltage V _FG is given by the following equation.

를 대입하면, 상기 (3)식은 다음과 같이 고쳐쓸 수 있다.here,

By substituting, Equation (3) can be rewritten as follows.

Incidentally, although the above-described memory cells are actually arranged in a matrix state in the memory, a 4-bit memory cell array will be described as shown in FIG. 8 for simplicity of explanation.

FIG. 8 is a circuit diagram of a memory cell array having four memory cells M1 to M4, wherein the drains of the four memory cells M1 to M4 are connected to one of the two data lines DL1 and DL2. The control gate is connected to one of the two word lines WL1 and WL2, and is commonly connected to the erase gate erase line EL of the mode memory cells M1 to M4. The ground voltage OV is applied to the sources of all the memory cells M1 to M4, for example.

Next, the data erase operation of the memory cell array configured as described above will be described.

Data erasing is performed collectively for all the memory cells M1 to M4. Therefore, the source voltage V _S , the drain voltage V _D , and the control gate low voltage V _CG of the memory cell are all set to OV (i.e., the data lines DL1 and DL2 and the word lines WL1 and WL2). OV, only the erase gate voltage V _EG is set to high potential, for example, + 20V. At this time, due to the channel effect of Fowler-Nordheim, it is emitted to the elimination gate by the emission of the electron field in the floating gate, and the floating gate is charged to the electric potential, for example, the voltage in the floating gate [V _FG (I)]. ] Is charged to + 3V (at this time, the threshold voltage Vth of the floating gate transistor is set to 1V), and an inversion layer is generated below the floating gate, so that the threshold voltages of all the memory cells are lowered. This state is referred to as data # 1 ', whereby the erase operation is performed.

Next, the case where data is written into one memory cell of the memory cell array, for example, memory cell M1, will be described.

First, the control gate voltage V _CG of the selected memory cell M1, that is, the word line WL1 is, for example, at a high potential of +12.5 V, and the drain voltage V _D , that is, the data line DL1, is +10 V, for example. The voltages are set to the high potentials of, while the voltages of the source voltage V _S and the potential of the data line DL2 and the word line WL2 are set to OV. For example, + 5V is applied to the erase gate.

When the voltage is applied as described above, the voltage of the floating gate is increased in the selected memory cell M1 due to the ratio of the erase gate, so that the writing becomes easy. Thus, the thermoelectric effect is increased near the drain of the selected memory cell M1. Electrons generated by impact ionization are injected into the floating gate. In this state, the floating gate voltage V _FG is negatively charged. For example, if the voltage V _FG (I) in the floating gate is -3V, the threshold voltage of the memory cell becomes high.

This state is referred to as data # 0 ', whereby the data write operation is executed. On the other hand, in the non-selected memory cells M2 to M4, the hot electron effect does not occur and data is not written.

Next, voltage pressing on the unselected memory cells M2 to M4 at the time of data writing will be described.

Since V _EG · C _FE and VD · C _FD in the above formula (4) are sufficiently smaller than V _CG · V _FC at the time of data writing, the above formula (4) can be changed as follows during data writing.

Here, the capacitance ratio C _FC / C _{T is set} to 0.6, for example, and the voltage in the floating gate of the memory cell in the # 1 state is [V _FG (I)] = + 3V. Consider the case where [V _FG (I)] = -3V. The case where the stored data of the unselected memory cell M2 on the same word line WL1 as the selected memory cell M1 is # 1 will also be considered.

First, since the control gate voltage V _CG of the memory cell M2 / is 12.5V, the floating gate V _FG becomes 10.5V according to Equation (5), and the erase gate voltage V _EG is 5V. The erase gate voltage V _EG seen from the floating gate becomes -5.5V. However, when the erase gate 5V is applied, when the electric field of the floating gate of the floating gate of the non-selected memory cell M2 on the same word line as the selected memory cell M1 is relaxed, there is a problem of malfunction due to writing. As a result of this, Fig. 9 shows the voltage pressure of the floating gates of the erase gates applied to the four memory cells M1 to M4 shown in FIG. In Fig. 8, the voltage pressure of the non-selected memory cells to the floating gate is maximized because the unselected memory cells M3 and M4 in which the control gate is connected to the word line WL2 different from the selected memory cell M1. This is the case when the stored data of) is '0'. That is, as can be seen from FIG. 9, in the non-selected memory cells M3 and M4, a voltage of +8 V is applied between the floating gate and the erase gate when data is written into the selected memory cell M1, and thus, the memory cell M2. In contrast to this, the non-selected memory cells M3 and M4 are in a weakly erased state, whereby electrons in the floating gates are easily released to the erase gates, which causes decay.

FIG. 10 is a circuit diagram showing the structure of a conventional memory using the memory cell, connected to any one of the n-drain data lines DL1 to DLn of each of the memory cells 30 in the memory cell array 31 shown in FIG. The control gate is connected to one of the m word lines WL1 to WLm. The erase gates of all the memory cells 30 are connected to the erase line EL in common, and a reference voltage, for example, OV is applied to the source of each memory cell 30.

At this time, since the erase gates of all the memory cells 30 in the memory cell array 31 are commonly connected, the erase gate voltage VEG is applied to the erase gates of all the memory cells 30 at the time of data erasing. In Fig. 10, reference numeral 32 is a row decoder, 33 is a column decoder, 34-1 to 34-n are column select transistors, 35 is a bus line, 36 is a data input circuit, 37 is a sense amplifier circuit, 38 Is a data output circuit, 39 is an erase booster circuit, and 41 is an address buffer.

Here, considering the case where the data write time per memory cell is t and all bits are written, the compression time when the control gate is OV in the non-selected state, that is, the weak erase state described in FIG. 9, is maximum. Where {(m−1) × n} × t (where m is the number of lines and n is the number of columns).

However, in the conventional technology as described above, when a random voltage is applied to the erase gate during data writing, the write efficiency of the selected memory cell is increased and the writing of unselected memory cells on the same word line can be alleviated. In the case of an unselected memory cell on another word line, the erasing gate voltage V _EG is applied to the erasing gate despite the OV being applied to the control gate. Compared with the non-selected memory cell on the word line, it becomes larger and is easy to be erased. In addition, it was confirmed that the probability of occurrence of erase was increased in proportion to the pressure time of the voltage. This compression time depends on the memory capacity of the memory. As the memory capacity becomes larger, the compression time becomes longer, which causes problems in reliability. For example, in the case of a memory having a storage capacity of 1 M bits (128 K words x 8 bits configuration), in the configuration of FIG. 10, n (number of columns) = 128, m (number of lines) = 1024, and writing time of 1 bit Is 1ms, the maximum time that the voltage is applied to the non-selected memory cell on the same word line as the selected memory cell is 1ms x 127 = 127ms. The maximum time taken for the voltage pressurization is 1 ms x (1024-1) x 128 = 130944 ms # 131 s, which is a very long time.

[Purpose of invention]

The present invention has been invented to solve the above-mentioned problems, and since the voltage applied to the non-selected memory cell is shortened by plural-blocking the memory cell array, the memory cell does not malfunction when data is written. It is an object to provide a volatile semiconductor memory.

[Configuration of Invention]

The nonvolatile semiconductor device of the present invention for achieving the above object includes a floating gate and a control gate and an erasing gate capacitively coupled to the floating gate, respectively, so that a transistor capable of electrically changing data and storing the same as a nonvolatile memory cell. In an installed nonvolatile semiconductor memory, a memory cell array in which the memory cells are arranged in a matrix form is divided into a plurality of blocks, and common and unique erase lines are provided for each block, and data is stored only in the erase lines of the selected block. A predetermined voltage is applied at the time of writing.

[Action]

In the nonvolatile semiconductor memory of the present invention configured as described above, since a positive voltage is applied only to the erase line of the block selected at the time of data writing, and the erase line of the non-select block is maintained with OV, the memory cell in the non-select block has a voltage. There is no pressure. Therefore, the voltage pressing time of the erase gate with respect to the floating gate of the non-selected memory cell can be shortened, so that the erasure of the non-selected memory cell hardly occurs when data is written, thereby improving the reliability of the memory. .

EXAMPLE

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention devised in view of the above-mentioned problems, and this memory is an EEPROM capable of reading / writing 1 bit, and this memory is a memory cell of FIG. The memory cells 30 in the array 31 are arranged in a matrix of rows and columns, which are divided into a plurality of blocks, and reference numerals of the divided blocks are denoted by 42-1 to 42-k. .

In the memory shown in FIG. 1, the control gates of the memory cells arranged in the same row are common to the word lines WL1-1 to WLk-1 selected by the row decoders 40-1 to 40-k, respectively. The drains of the memory cells arranged in the same column are connected to one of the data lines DL1 to DLn in common. The erase gates of the memory cells in the same block memory cell array are all connected in common, and each block has an output and a block of the address buffer 45 for selecting a block in the erase gate decoders 43-1 to 43-k. The output of the address buffer 44 for selecting the word line WL is inputted to select one word line among the word lines WL1-1 to WLK-1. The output of the address buffer 45 is also input to 34k, and the word line and the erase line are always selected for the same block.

The data lines DL1 to DLn have a common bus via the column select transistors 34-1 to 34-n to which the column select lines CL1 to CLn selected by the column decoder 33 are connected to their gates. It is connected to the line 35. The bus line 35 is connected with a data input circuit 36 for outputting data of # 0 or # 1 of a high voltmeter set in accordance with externally input data Din. The bus line 35 is outputted to the bus line 35 in accordance with the memory data of the memory cells selected by the row decoders 40-1 to 40-k and the column decoder 33. And a sense amplifier circuit 37 for detecting a read potential of # 1, and the detection data of the sense amplifier circuit 37 is supplied to the data output circuit 38, and the read data Dout is supplied. It is output from the data output circuit 38 to the outside of the memory.

Next, the operation of the memory configured as described above will be described.

First, data writing is performed by selecting one memory cell 30 in the memory cell array 31 by the row decoders 40-1 to 40-k and the column decoder 33. At this time, the selected word line among the word lines WL1-1 to WLk-L is set to a potential of + 12.5V, and a high potential of + 10V is output from the data input circuit 36 when writing " 0 " And any one of the column selection transistors 34-1 to 34-n whose potential is selectively turned on by the output of the column decoder 33, and any one of the selected data lines DL1 to DLn. The drain of the selected memory cell 30 is supplied. Accordingly, electrons are injected into the floating gate of the memory cell selected by the thermoelectronic effect described with reference to FIG. 8 to complete writing of the data # 0.

On the other hand, when the data # 1 'is to be written, since the potential of OV is output from the data input circuit 36, the electrons do not move in the selected memory cell 30 so that the data of # 1' is maintained.

Next, the voltage state of the erase gate at the time of data writing is considered. First, the erase gate decoder to which the same address as the row decoder block including the selected word line is input is selected, and then to only the erase line of any one of the block memory cell arrays 42-1 to 42-k including the selected memory cell. + 5V is applied by the selected erase gate decoder, and OV is applied to other unselected erase lines. However, at the time of erasing the entire memory, a boosted voltage [HE], for example, + 20V, is output from the erase booster circuit 39 and input to all erase gate decoders 43-1 to 43-k. 43-1 to 43-k are all in a selected state, and all of the erase lines EL1 to ELk become the boost voltage [HE] so that all the bits are erased collectively. At this time, the word lines WL1-1 to WLk-L and the data lines DL1 to DLn are both OV.

The erase gate decoders 43-1 to 43-k can be realized by, for example, the circuit shown in FIG. Here, Vcc is a reference voltage of 5V normally, Vss is a reference voltage of OV normally, and Vpp is a high voltage of 12.5V, for example. [HE] is an output of the erase booster circuit 39. When erased, for example, a boost voltage of +20 V is output, and a power supply voltage (5 V) is output at the time of writing.

An output terminal of the decoder 50 constituted of NAND is connected to the transfer gates T1 and T2, and an inverter formed of a feedback circuit is connected to the output of the transfer gate T2, and the output of the inverter is the erase line EL. Is connected to. The transistors T1 and T2 and T5 and T6 are composed of depleted N-channel transistors, and are high voltage relaxation transfer gates for alleviating the potential difference applied to the gate oxide film when [HE] is a boost voltage. . The output of the circuit shown in FIG. 3 is input to the erasing line EL (any one of EL1 to ELk).

Here, the case of the present invention will be discussed with respect to the compression time of the weak erase state described in FIG.

In the memory circuit of FIG. 1, the erasing gate becomes 5V when data is written, which is a period during which writing is performed to any one of the same block memory cell arrays 42-1 to 42-k, that is, n ×. L (number of columns) x number of rows in a block. For example, in a memory cell on a word line different from the selected memory cell, the time taken for the pressing voltage causing the erasure is [(L-1) × n] × t, if the write time per bit is t. do. In addition, since m (the number of destinations) in FIG. 10 is related to m = L x k (k is the number of blocks), the pressing time is reduced to about 1 / k as compared with the conventional example.

In this embodiment, the EEPROM that reads / writes one bit of data has been described. However, the memory cell array 31, the bus lines 35, the data input circuits 36, the sensor amplifier circuits 37, and the data output circuits are described. A plurality of parallel arrangements (38) (8-bit configuration, 16-bit configuration, etc.) can also be configured as an EEPROM that reads / writes multiple bits of data in parallel.

In the case of 1M bit (128K word x 8-bit configuration) as in the conventional example, when the number of memory cells in one block memory cell array is 1K byte, the number of data lines n = 128, 1 The number L of word lines in a block is eight and the number k of blocks is 128. Accordingly, the total compression time to be applied to an unselected memory cell on a word line different from the selected memory cell is 1 ms x (8- 1) x 128 = 896 ms = 0.9 s, and compared with the conventional example, the compression time is greatly reduced to 0.9 / 131 ≒ 1/145, thereby solving the problem of erasing.

As another embodiment of the present invention of FIG. 2, the operation at the time of data writing in this embodiment is the same as that of the embodiment of FIG. 1, except that the erasing address buffer 47 is provided. In the present embodiment, during erasing, one of the erase gate decoders 46-1 to 46-k is selected and driven by the output of the erasing address buffer 47 to which the erasing addresses EA1 to EAi are input. . Also, the erase gate decoders 46-1 to 46-k have a boost circuit built in, so that the boost voltage is output to any of the erase lines EL1 to ELk from the erase gate decoder being selected and driven as the erase gate voltage V _EG . Data of all memory cells in the selected block memory cell array are erased, while memory cells in the unselected block memory cell array are not erased.

In addition, all the erase gate decoders 46-1 to 46k can also be selected collectively. In this case, all of the memory cells 30 of the memory cell array 31 are collectively erased.

On the other hand, the erasing gate decoders 46-1 to 46-k of the present embodiment can be realized by, for example, a circuit as shown in Fig. 4. Here, øV _pp denotes a signal which vibrates between OV and V _pp at a constant cycle during erasing. (Signal output by the charge pump circuit).

In the erase gate decoder selected by the erasing addresses EA1 to EAi at the time of data erasing, a high voltage V _pp is generated by a boost circuit composed of the transistors T10, T11, T12 and the capacitor C1. The boosted voltage is output to the erase line EL (any one of EL1 to ELk) as the erase gate voltage V _EG .

As described above, the present embodiment can erase only the block designated by the erasing addresses EA1 to ELi, so that the boosting circuit can be made small.

The erasing addresses EA1 to EAi can be arbitrarily selected. For example, the block selection addresses RA1 to RAi may be used. Alternatively, the circuit of FIG. 3 may be used as the erase gate decoders 46-1 to 46-k of FIG. In this case, the erasing boosting circuit 39 of FIG. 1 may be provided while the erasing address signals EA1 to EAi are input as shown in FIG. The circuit of FIG. 4 may be used as the erasing gate decoders 43-1 to 43-k of FIG.

[Effects of the Invention]

As described above, according to the present invention, it is possible to prevent writing of unselected memory cells provided on the same word line as the selected memory cell without lowering the write efficiency of the selected memory cell. In addition, since the voltage pressing time of the erase gate with respect to the floating gate of the non-selected memory cell on a word line different from that of the selected memory cell can be shortened, misunderstanding can be prevented and data reliability can be improved. do. In addition, the voltage pressing time of the erase gate in the floating gate can be shortened, and the deterioration of the gate insulating film due to the write / erase cycle can be suppressed, and the data retention characteristic can be improved by repeating the write / erase cycle frequently. Will be.

Claims (2)

A transistor comprising a floating gate 11 and a control gate 13 and an erasing gate 12 capacitively coupled to the floating gate 11, respectively, to electrically change data and to write the nonvolatile memory cell 30. In a nonvolatile semiconductor memory, a memory cell array 31 in which the memory cells 30 are arranged in a matrix form is divided into a plurality of blocks 42-1 to 42-k. The common and unique erase lines EL1 to ELk are provided for each of the blocks 42-1 to 42-k, and a predetermined voltage is applied only to the erase lines of the selected block during data writing. Volatile Semiconductor Memory. 2. A nonvolatile semiconductor memory according to claim 1, wherein said memory cells (30) are arranged in a matrix form and these memory cells (30) are block-by-row units.

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