JPH06249949A - Agc circuit each frequency - Google Patents

Abstract

PURPOSE:To extract Doppler echoes without being masked by reverberation even if S/R ratio is poor. CONSTITUTION:An optimum AGC for reverberation characteristic is performed for each frequency and convergence time can be reduced by loading a value corresponding to the reverberation characteristics for each frequency from a ROM 15 as the initial value of an AGC (Auto Gain Control) circuit 6, thus extracting Doppler echoes without being masked by reverberation owing to the reverberation suppression effect.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an AG for reverberation suppression in an active sonar device which emits a sound wave into water and detects and displays a target object from its echo.
The present invention relates to a C (AutoGain Control) circuit.

[0002]

2. Description of the Related Art FIG. 4 is a processing block diagram of an AGC circuit which is executed for each frequency in a reception processing circuit of a conventional active sonar apparatus shown in FIG.

In the conventional active sonar apparatus, a sound wave is emitted from the wave transmitter 1 in water, the echo sound (echo) from the target 2 is received by the wave receiver 3, and the preprocessor 4 performs frequency conversion or the like. After being processed, the reception data 101 for each frequency divided into each frequency by the frequency analysis circuit 5 is given to the frequency-based AGC circuit 6. In the frequency-based AGC circuit 6, AGC is performed on the reception data 101 for each frequency as follows.

The received data 101 for each frequency is multiplied by K in the multiplier 7 (K is a constant determined by a time constant: K <1) and applied to the adder 8. The previous moving average value 102 is stored in the register 10 which receives the output signal of the adder 8,
This value is multiplied by (1−K) (K is a constant determined from a time constant: K <1) in the multiplier 9 and is given to the adder 8. The adder 8 adds the received data multiplied by K and the previous moving average value multiplied by (1-K).

The new moving average value 103 output from the adder 8 is stored in the register 10 and the divider 11
Is output to. The divider 11 receives the received data 10 for each frequency.
1 is divided by the new moving average value 103, and the result is output to the post-processor 12 as AGC output data 104 for each frequency. The above operation is performed by the AGC circuit 6 for each frequency, but when the received data 101 for each frequency is processed for the first time, the initial value (constant data) of the register 10 is set to the initial value setting unit 1.
Load from 4.

In the post-processor 12, the AGC output data 104
Format conversion and the like are performed and output as video data to the display unit 13. The display device 13 displays the input video data as an image.

[0007]

In the conventional AGC circuit that is implemented for each frequency, the initial value of the register for storing the moving average value of the AGC circuit is the same for each frequency, so it is optimal for reverberation characteristics. AGC was not performed, and the reverberation suppression time was different for each frequency. The frequency characteristic of reverberation is sin (2πfT) / (2) depending on the transmission pulse width (T) and the transmission frequency (f) from the transmitter as shown in FIG.
πfT) and its level fluctuates and decays with time.

Therefore, when the S / R ratio (signal-to-reverberation ratio) is poor, the reverberation sound (echo) having Doppler is masked by the reverberation until the reverberation level of each frequency converges by AGC, and extraction is difficult.

An object of the present invention is to provide a frequency-based AGC circuit capable of extracting a reverberant sound (echo) having Doppler without being masked by reverberation even when the S / R ratio is poor.

[0010]

According to the present invention, in the frequency-based AGC circuit which is implemented for each frequency in the reception processing circuit of the active sonar device, the reception data is multiplied by K (K is a constant determined from the time constant: A first multiplier for K <1), a second multiplier for multiplying the previous moving average value by (1-K), received data multiplied by K, and a previous moving average value for (1-K) times. For storing the data for setting the initial value of the register, the register for providing the second moving average value to the second multiplier, and the data for setting the initial value of the register. And a divider for dividing received data by output data of the adder to obtain a frequency-based AGC circuit.

In the present invention, instead of the ROM, an initial value setting register for storing data or n
It is also possible to use an average value detection circuit that can store a number (n is a natural number) of received data and can detect the average value of these n.

[0012]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. Target 2 by emitting sound waves from the transmitter 1 into the water
After receiving the echo (echo) from the receiver 3 by the wave receiver 3 and being processed by the preprocessor 4 such as frequency conversion, the frequency analysis circuit 5
Received data for each frequency divided into 10
1 is output to the frequency-based AGC circuit 6. AG by frequency
The C circuit 6 receives the received data 10 for each frequency as follows.
AGC is performed for 1.

The received data 101 for each frequency is multiplied by K in the multiplier 7 (K is a constant determined by a time constant: K <1) and output to the adder 8. The previous moving average value 102 is stored in the register 10, and this value is multiplied by (1-K) by the multiplier 9 (K is a constant determined by a time constant: K <1) and output to the adder 8. The adder 8 adds the previous moving average value multiplied by the received data multiplied by K (1-K).

The new moving average value 103 output from the adder 8 is stored in the register 10 and the divider 11
Is output to. The divider 11 receives the received data 10 for each frequency.
1 is divided by the new moving average value 103, and the result is output to the post-processor 12 as AGC output data 104 for each frequency.

The above operation is carried out by the AGC circuit for each frequency. When the received data 101 for each frequency is processed first, the initial value is set in the register 10 as data corresponding to the transmission pulse width, the transmission frequency and the reception level. ROM where is located
Load from 14.

In the post-processor 12, the AGC output data 104
Format conversion and the like are performed and output as video data to the display unit 13. The display device 13 displays the input video data as an image.

FIG. 2 shows a frequency-dependent A according to another embodiment of the present invention.
It is a block diagram of a GC circuit. In the embodiment shown in FIG. 2, the ROM 15 is replaced with the initial value setting register 16 in the embodiment shown in FIG.
Is stored in the initial value setting register 16, and the initial value of the register 10 is set as the value of the first received data 101 stored in the initial value setting register 16.

FIG. 3 is a block diagram of an AGC circuit for each frequency according to still another embodiment of the present invention. The embodiment shown in FIG. 3 has n ROMs 15 (n is a natural number) in the embodiment of FIG. The received data 101 for each frequency is accumulated and replaced with an average value detection circuit 17 that detects the average value, and the received data 101 for each frequency is stored in this average value detection circuit 17, and the initial value of the register 10 is set. Is the value of the detection result of the average value detection circuit 17.

[0020]

As described above, according to the present invention, the initial value of the register for storing the moving average value in the AGC circuit executed for each frequency is set to the transmission pulse width, the transmission frequency and the reception frequency corresponding to each frequency. By setting the set value according to the wave level, the first received data, or the average value of the first received data, the optimum AGC for the reverberation characteristic is performed for each frequency, and the convergence time can be shortened. Therefore, the present invention
With this reverberation suppressing effect, there is an effect that even when the S / R ratio is poor, the reverberant sound (echo) having Doppler can be extracted without being masked by the reverberation.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing another embodiment of the present invention.

FIG. 3 is a block diagram showing still another embodiment of the present invention.

FIG. 4 is a block diagram showing a conventional AGC circuit.

5 is a diagram for explaining frequency characteristics and level characteristics of reverberation in the conventional AGC circuit of FIG.

[Explanation of symbols]

 1 wave transmitter 3 wave receiver 4 pre-processor 5 frequency analysis circuit 6 frequency-specific AGC circuit 7 multiplier 8 adder 9 multiplier 10 register 11 divider 12 post-processor 15 ROM 16 initial value setting register 17 average value Detection circuit 101 Received data for each frequency 102 Previous moving average value 103 New moving average value 104 AGC output data

Claims (3)

[Claims] 1. An AGC circuit for each frequency, which is implemented for each frequency in a reception processing circuit of an active sonar device, in which received data is multiplied by K (K is a constant determined from a time constant: K <
1) and the previous moving average value to (1-
K) times the second multiplier, K times the received data and (1
-K) an adder for adding the previous moving average value multiplied by this value, a register provided with the output data of this adder and giving the previous moving average value to the second multiplier, and an initial register of this register AGC for each frequency, comprising a ROM storing data for setting a value and a divider for dividing received data by output data of the adder
circuit. 2. An AGC circuit for each frequency, which is executed for each frequency in a reception processing circuit of an active sonar device, in which received data is multiplied by K (K is a constant determined from a time constant: K <
1) and the previous moving average value to (1-
K) times the second multiplier, K times the received data and (1
-K) an adder for adding the previous moving average value multiplied by this value, a register provided with the output data of this adder and giving the previous moving average value to the second multiplier, and an initial register of this register An AGC circuit for each frequency comprising an initial value setting register for storing data for setting a value and a divider for dividing received data by output data of the adder. 3. In a frequency-based AGC circuit that is executed for each frequency in a reception processing circuit of an active sonar device, reception data is multiplied by K (K is a constant determined from a time constant: K <
1) and the previous moving average value to (1-
K) times the second multiplier, K times the received data and (1
-K) an adder for adding the previous moving average value multiplied by this value, a register provided with the output data of this adder and giving the previous moving average value to the second multiplier, and an initial register of this register N for setting a value (n is a natural number)
2. An AGC circuit for each frequency, comprising: an average value detection circuit capable of storing the received data of 1. and detecting the n average values; and a divider for dividing the received data by the output data of the adder.