JPH06118905A - LCD drive circuit - Google Patents

Abstract

(57) [Abstract] [Object] The present invention relates to a configuration of a drive circuit in an active matrix liquid crystal display (LCD), and a circuit configuration of a decoding unit in a drive circuit of an LCD adapted to multi-gradation display. It is an object of the present invention to achieve simplification and eventually to reduce the chip area of the data driver, and also to reduce the cost of the LCD. A decoder 80 includes a plurality of decoders D ₁ to D ₁ to which image data is divided into a plurality of groups and each of which is partially decoded.
The selector 90 is divided into a plurality of selectors S _{1 to} Sn so as to correspond to each of the plurality of divided decoders, and the plurality of divided selectors are divided into the reference power source 50 and the liquid crystal panel 10. It is configured to be connected in cascade between.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a liquid crystal display device (LC
Regarding D), especially active matrix type LCD
In regard to the configuration of the drive circuit in. LCD is the conventional C
It is expected as a display device replacing RT, and is expected to develop into a large-scale market. Therefore, the technological development is actively done. In particular, LCDs (Active Matrix LCDs) that use thin film transistors (TFTs) are capable of high-quality display in principle, and have a high display speed. It is expected to become the mainstream display for displays.

[0002]

2. Description of the Related Art FIG. 4 shows the structure of an LCD as an example of a conventional type, and FIG. 5 shows the structure of the main part thereof. In the illustrated example, the structure of a TFT type LCD using a digital driver method as a display control mode is shown, and the number of pixels is shown as 4 × 4 for simplification of description. Actually, the typical number of pixels is about 640 × 480,
Moreover, since it is necessary to have pixels for red (R), green (G) and blue (B) for color display, the number of pixels is further tripled.

In the figure, 10 indicates a liquid crystal display unit (liquid crystal panel), and P11 to P44 in the liquid crystal display unit represent the minimum display units called pixels. Each of the pixels P11 to P44 has a plurality of data lines X1 to X4 and a plurality of gate lines Y1 to Y4.
A transfer gate transistor (TFT) arranged at the intersection of 4 and transmitting voltage information on the corresponding data line when the corresponding gate line is selected, and information transmitted via the corresponding TFT are stored. It is made up of a liquid crystal capacitor. In this figure, the arrangement of pixels in the horizontal direction (for example, P11 to P14) is called one line, and the data for display on the LCD is written for each line, and this is repeated about 60 times per second, and Show as an image with no flicker to the eyes.

In FIG. 4, HS is a horizontal synchronizing signal, VS
Is a vertical sync signal, D1 to DN are image data, and CL
K indicates a timing signal (clock) given in synchronization with the image data. Note that N represents the number of bits for gradation display. Further, the clock CLK can be internally generated by measuring the cycle of the horizontal synchronization signal HS, and is not essentially required as an interface.

Reference numeral 40 denotes a control circuit for controlling the entire LCD, which generates various control signals for writing the image data D1 to DN in response to the horizontal synchronizing signal HS, the vertical synchronizing signal VS and the clock CLK. Reference numeral 50 denotes a reference power source that generates a plurality of types of reference voltages V1 to VM. Two
Reference numeral 0 denotes a data driver, which includes a shift register 21, memories 61 to 64 each having an N-bit capacity, and memories 71 to 74 each having an N-bit capacity.
, Decoders 81 to 84, and selectors 91 to 94, and are integrated into a normal circuit. Note that the reference power supply 50 is not normally included in the integrated circuit. This is because the data driver 20 required for the LCD is usually composed of a plurality of ICs, whereas one reference power supply 50 is commonly provided.

In the data driver 20, the shift register 21 starts its operation for each line by the start signal T1 supplied from the control circuit 40, and advances by the clock CK1 similarly supplied by the control circuit 40 to make a timing signal. Generate TS1 to TS4. Memories 61 to 6
Reference numeral 4 denotes timing data TS1 to TS for displaying data DT1 to DTN supplied through the control circuit 40, respectively.
Captured in response to 4 (that is, writing of data). Further, the memories 71 to 74 respond to the timing signal T2 from the control circuit 40 with the data in the memories 61 to 64 after the data is written in the memories 61 to 64 and before the data of the next line arrives. Import (write data). The decoders 81 to 84 respectively include the memories 71 to 7
The digital data stored in 4 is decoded. The selectors 91 to 94 selectively output any of the plurality of types of reference voltages V1 to VM output from the reference power supply 50, based on the decoding results of the corresponding decoders 81 to 84. That is, the selectors 91 to 94 function as a kind of digital-analog conversion circuit for generating analog signals corresponding to the digital data stored in the memories 71 to 74. In this way, one of the M types of voltages V1 to VM is selected and output to the data lines X1 to X4. M type reference voltages V1 to VM and memories 71 to
The relationship with the N-bit data stored in 74 is represented by M = 2 ^N when the data is a binary number. For example, when N = 3, M = 8, and when N = 4, M = 16.

Reference numeral 30 denotes a gate driver, which is composed of a shift register 31 and drivers DV1 to DV4 provided corresponding to the gate lines Y1 to Y4.
The shift register 31 starts its operation by the start signal T3 supplied from the control circuit 40, and the control circuit 4 similarly.
A signal for driving the TFT of each line of the liquid crystal panel 10 is sequentially generated by stepping by the clock CK2 supplied from 0. The start signal T3 has the same cycle as the vertical synchronizing signal VS, and the clock CK2 has the same cycle as the horizontal synchronizing signal HS. The drivers DV1 to DV4 are
It functions as a binary output circuit that performs level conversion from the output of the shift register 31 to a voltage that can control ON / OFF of the TFT and outputs the voltage to the corresponding gate lines Y1 to Y4. As a result, the TFT that is an analog switch
The switch function can be turned on / off by controlling the gate voltage of each of the data lines, and the signal voltage of the image data output from the data driver 20 on the data lines X1 to X4 can be written in the liquid crystal capacitance line by line through the TFT. it can.

FIG. 5 shows details of the decoder 81 and the selector 91 in FIG. In the configuration shown in the figure, the decoder 81 decodes the digital data D0 to D3 stored in the corresponding memory 71, and based on the decoding result, only one analog switch in the selector 91 is turned on to turn on the reference voltage V1 to V1. An example of selecting one voltage from V16 is shown. That is, this case corresponds to the case where N is 4 described above.

In the examples shown in FIGS. 4 and 5, the number of pixels is shown as 4 × 4 for simplification of description, but as described above, in an actual LCD, the horizontal direction is 640 lines and the vertical direction is 480 lines. Total of 640 × 480 = 30720
Driving 0 pixels is a typical example, and a data driver for this purpose needs a very large scale. Moreover, for color display, red (R), green (G) and blue (B)
Since it is necessary to have another pixel, the total number of pixels is three times this. In the configuration of FIG. 5, the number of bits is 4 (D0 to D
3), the data driver has a voltage value of 16 (V1 to V16), but the number of gradations is 4096 colors for normal OA (R
× G × B = 16 × 16 × 16).

[0010]

Generally, the data driver occupies a large part in price among the elements constituting the LCD, and is an important element for lowering the price of the LCD. Therefore, in order to achieve the price reduction, L
It is necessary to adopt a circuit system that can reduce the chip area when SI is used.

However, in the conventional configuration, as shown in FIG.
It was necessary to use 8 inverters, 8 NAND gates and 16 NOR gates. That is, there is a problem that the number of gates used is relatively large, which complicates the circuit configuration of the decoding unit. This is not preferable because it increases the circuit scale of the data driver, which in turn leads to an increase in the chip area of the entire LCD and an increase in cost.

In view of the above problems in the prior art, an object of the present invention is to simplify the circuit configuration of the decoding section in the LCD drive circuit adapted for multi-gradation display, and further to reduce the chip area of the data driver. , LCD again
It is to realize cost reduction.

[0013]

In order to solve the above problems, according to the present invention, a reference power source 50 for generating a plurality of reference voltages V1 to VM as shown in the principle configuration diagram of FIG.
And a decoder 80 and a selector 90 provided for each data line Xj, and the selector selects one of the plurality of reference voltages based on the result obtained by decoding the digital image data. In the drive circuit of the liquid crystal display device for driving the liquid crystal panel 10 by supplying each of the selected reference voltages to the corresponding data line as an image data voltage, the decoder divides the image data into a plurality of groups. A plurality of decoders D _{1 to} D for performing partial decoding of each
and a plurality of selectors S ₁ so as to correspond to each of the plurality of divided decoders.
To Sn, and a plurality of divided selectors are cascade-connected between the reference power source and the liquid crystal panel to provide a drive circuit for a liquid crystal display device.

[0014]

According to the above-described structure, the decoder 80 and the selector 90 of the conventional structure, which are provided corresponding to each data line Xj, are respectively composed of a plurality of decoders D _{1 to} Dn and a plurality of selectors S ₁ to S ₁ corresponding to them. Each of the decoders D _{1 to} Dn is divided into Sn and stored in the memory 70.
Partial decoding is performed on a group of bits (N ₁ bit, N ₂ bit, ..., N n bit data) divided into multiple sets of bit image data, and based on the results of each partial decoding. Each selector cooperates to select one of the plurality of reference voltages V1 to VM and send it to the corresponding data line Xj as an image data voltage.

That is, in the past, one decoder realized the required function, but in the present invention, a plurality of decoders D are used.
_{Since the} same function is achieved by the cooperative action of _{1 to} Dn, the circuit configuration of each decoder can be simplified and the circuit scale of the entire decoding section can be relatively reduced. . This contributes to reduction of the chip area of the LCD drive circuit and cost reduction.

Details of other structural features and operations of the present invention will be described using embodiments described below with reference to the accompanying drawings.

[0017]

FIG. 2 shows the structure of an LCD as an embodiment of the present invention. As shown in FIG. 2, the feature of the present embodiment is that, for each of the data lines X1 to X4, the circuit portion for decoding the N-bit image data stored in each of the memories 71 to 74 is provided with a lower bit group data ( Two decoders 81A and 81A for dividing into P bits) and upper bit group data (Q bits) and partially decoding each
B, 82A and 82B, 83A and 83B, 84A
And 84B, respectively, and two selectors 91A for selecting any one of the plurality of reference voltages V1 to VM corresponding to the two decoders.
And 91B, 92A and 92B, 93A and 93
B, 94A and 94B respectively. Here, each two selectors are connected in cascade. The other circuit configuration and its operation are the same as those in the case of FIG. 4, and therefore their explanations are omitted.

FIG. 3 shows a circuit configuration of the decoder and the selector. The decoder divided into two has the same configuration for each data line, and the two cascade-connected selectors also have the same configuration for each data line.
In the illustrated example, for simplification, only the configurations of the decoders 81A and 81B and the selectors 91A and 91B corresponding to the data line X1 are shown.

The decoders 81A and 81B have the same structure. That is, the decoder 81A (81
B) shows two inverters GA1 and GA2 (G) which respond to 2-bit data D1 and D0 (D3 and D2), respectively.
B1, GB2) and inverters GA1, GA2 (GB
1, GB2) in response to each output of the decode signal E (A)
And a NOR gate GA3 (GB3) that outputs a decode signal F (B) in response to the output of the inverter GA1 (GB1) and the data D0 (D2).
4 (GB4) and the decode signal G in response to the output of the data D1 (D3) and the inverter GA2 (GB2).
A decode signal H in response to NOR gate GA5 (GB5) outputting (C) and data D1, D0 (D3, D2)
NOR gate GA6 (GB6) for outputting (D).

Further, the selector 91A has 16 analog switches SA1 to SA16, and each switch is divided into four groups. 4 for each group
Individual switches SA1-SA4, SA5-SA8, SA9
To SA12 and SA13 to SA16 are turned on / off in response to the decode signals E to H from the decoder 81A, and four types of reference voltages V1 to V4 and V5 to V5, respectively.
Any one of 8, V9 to V12, and V13 to V16 is selectively output.

The selector 91B is the selector 91A.
Of the four reference voltages selectively output for each group of 4 analogs in response to the decode signals A to D from the decoder 81B, and connected to the corresponding data line X1. It has switches SB1 to SB4. According to the configuration of the present embodiment, as shown in FIG. 2, the two decoders (for example, 81A and 81B) provided for each of the data lines X1 to X4 have the N-bit stored in the corresponding memory 71. Partial decoding is performed on the lower bit group and the upper bit group that are divided into two sets of image data, and corresponding selectors (91A and 91B) cooperate with each other based on the results of the partial decoding. Any one of the plurality of reference voltages V1 to VM is selected and sent to the corresponding data line (X1).

As described above, although one decoder conventionally realizes a required function, in the present embodiment, the same function can be achieved by the cooperation of two decoders. The configuration can be simplified.
Comparing the configurations of the decoders 81A and 81B shown in FIG. 3 with the configuration of the decoder 81 shown in FIG.
Whereas the inverter for 16 gradations was composed of 8 NAND gates and 16 NOR gates,
In this embodiment, it is understood that the same function (decoder for 16 gradations) can be realized by four inverters and eight NOR gates, and the circuit scale can be greatly reduced.

Further, in order to realize the same 16 gradations, the selector 91 requires 16 analog switches in the conventional example, whereas the selectors 91A and 91B require 20 analog switches in this embodiment. And That is, it is necessary to increase the number of four analog switches as compared with the conventional example. However, since the analog switch can be realized with a relatively small chip area, as a whole, the reduction of the chip area by reducing the circuit scale of the decoders 81A and 81B is larger than the increase of the chip area by increasing the number of analog switches. , Is advantageous in terms of effect. Therefore, the chip area of the decoder driver can be significantly reduced. At the same time, this also contributes to cost reduction.

In the above-described embodiment, the case where the image data is divided into two sets of data of the lower bit group and the upper bit group and decoded for each data line has been described, but the partial decoding mode is two sets. Not limited to. As is clear from the gist of the invention, it is obvious that the same effect can be expected if the image data is divided into a plurality of sets and each of them is partially decoded.

[0025]

As described above, according to the present invention, it is possible to simplify the structure of the decoding section in the LCD drive circuit adapted for multi-gradation display, thereby reducing the chip area of the data driver. LCD at the same time
It is possible to realize the cost reduction.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of a drive circuit of a liquid crystal display device according to the present invention.

FIG. 2 is a configuration diagram of an LCD as one embodiment of the present invention.

3 is a configuration diagram of a main part of FIG.

FIG. 4 is a configuration diagram of an LCD as a conventional example.

5 is a configuration diagram of a main part of FIG.

[Explanation of symbols]

10 ... liquid crystal panel 20A ... data driver 50 ... reference supply 80 ... decoder 90 ... selector D ₁ ~Dn, 81A~84A, 81B~84B ... divided decoder S ₁ ~Sn, 91A~94A, 91B~94B ... divided Selectors V1 to VM ... Reference voltage generated from reference power source Xj ... Data line

Claims (3)

[Claims] 1. A reference power supply (50) for generating a plurality of reference voltages (V1 to VM) and a decoder (80) and a selector (90) provided corresponding to each data line (Xj).
And selecting one of the plurality of reference voltages by the selector based on a result obtained by decoding the digital image data by the decoder, and displaying each of the selected reference voltages on a corresponding data line. In a drive circuit of a liquid crystal display device for driving a liquid crystal panel (10) by supplying it as a data voltage, the decoder divides the image data into a plurality of sets and performs a plurality of partial decoders (D ₁ to D ₁ to Dn), and a plurality of selectors (S ₁ to S ₁ -D ₁₎ corresponding to each of the plurality of divided decoders.
Sn), and a plurality of the divided selectors are cascade-connected between the reference power source and the liquid crystal panel. 2. The plurality of decoders provided for each data line are first and second decoders (81A to 84A, 81B to 84B) that respond to a high-order bit group and a low-order bit group of the image data, respectively. And the plurality of selectors are first and second selectors (91A to 94) provided corresponding to the first and second decoders.
A, 91B-94B) is included, The drive circuit of the liquid crystal display device of Claim 1 characterized by the above-mentioned. 3. The first and second decoders (81)
A, 81B) are 2-bit data (D1,
D0; D3, D2) and two inverters (GA1, GA2; GB1, GB2) respectively, and two signals each based on each output of the inverter and all combinations extracted from the 2-bit data. Four NOR gates that respond respectively (GA3 to GA6; GB3 to GB
6) and the first selector (91A) is divided into four groups and each group is responsive to each output (E-H) of the four NOR gates of the first decoder. Four types of reference voltages (V1 to V4; V5 to V8; V9 to V12; V1
3 to V16), which has 16 analog switches (SA1 to SA16) for selecting any one of them, and the second selector (91B) has four types selectively output for each group of the first selector. Of the four analog switches (SB1) for selectively selecting one of the reference voltages of the second decoder in response to the outputs (A to D) of the four NOR gates of the second decoder and connecting it to the corresponding data line. ~
SB4) is included, The drive circuit of the liquid crystal display device of Claim 2 characterized by the above-mentioned.