JP2014164099A - Display panel drive circuit and electronic apparatus - Google Patents

Abstract

In an external circuit, it is unnecessary to generate a driving pattern supplied in parallel to pixels in a plurality of columns of a display panel.
A display panel driving circuit includes a plurality of registers each holding a plurality of subfield pattern data, a subframe counter that generates a count value by counting a subframe synchronization signal, and a clock signal. A clock counter that generates a count value according to the above, a selection circuit that selects one register according to the count value generated by the subframe counter, and a subfield that sequentially reads subfield pattern data from the register according to the count value generated by the clock counter A pattern generation circuit; and a pixel circuit that generates a drive pattern by performing a logical operation on the subframe image data and the subfield pattern data.
[Selection] Figure 1

Description

  The present invention relates to a display panel driving circuit for driving a display panel such as a liquid crystal on silicon (LCOS) panel. Furthermore, the present invention relates to an electronic device such as a video projector and an electronic viewfinder using such a display panel driving circuit.

  The LCOS panel is a reflective liquid crystal display panel with a structure in which liquid crystal is sealed between a single crystal silicon substrate and a glass substrate, and uses advanced silicon technology that is more advanced than liquid crystal display and plasma display technologies. Thus, a higher resolution image can be provided.

  As a structure of the LCOS panel, for example, circuit elements and wirings are formed on a single crystal silicon substrate, and further, individual electrodes (reflection electrodes) connected to the wirings through an insulating film are provided. A transparent common electrode is provided on a glass substrate facing the individual electrodes with the liquid crystal layer interposed therebetween. The liquid crystal can be driven by applying a voltage between the individual electrode and the common electrode.

  As an LCOS panel driving method, an analog driving method and a digital driving method are used. In the analog driving method, the gradation of an image is controlled by applying a continuous voltage generated according to image data to the liquid crystal. The analog drive system has the advantage that the gray scale can be reproduced finely because it continuously controls the gray scale, but it has a weak point that it is not suitable for high-speed operation.

  On the other hand, in the digital drive system, the tone of the image is controlled by applying a pulse train including a plurality of pulses of a constant voltage to the liquid crystal and changing the arrangement combination (drive pattern) of these pulses according to the image data. The The digital drive system is suitable for high-speed operation and has an advantage that the contrast can be increased, but has a weak point that the operating frequency must be increased in order to increase the gradation steps.

  In addition, subframe driving is also performed in which an image of one frame is divided into a plurality of subframes, subframe image data representing the subframes is generated, and the LCOS panel is driven. As a related technique, Patent Document 1 discloses that an image display device that divides an image of one frame into a plurality of subframes and sequentially time-divides each subframe to drive while maintaining high-gradation and high-quality image display. An image output apparatus for further reducing cost by suppressing an increase in circuit scale is disclosed.

  This image output apparatus divides pixel data for one frame into a plurality of subframes, and outputs subframe generation means for sequentially outputting each subframe, and time-divides the output period of each subframe into a plurality of fields. Field data generating means for generating output pixel data for each output and outputting them sequentially. The output pixel data is converted into an analog pixel signal by a source driver in the LCOS, and the analog pixel signal is supplied to the pixel transistor of the display unit.

Japanese Patent Laying-Open No. 2005-208407 (paragraphs 0009, 0013, 0032-0033)

  However, when the display panel is digitally driven, the field frequency becomes high. Conventionally, the drive pattern for driving the pixels of the plurality of columns of the display panel is an on / off signal from an external circuit to the display panel drive circuit. Had been supplied to. In this case, since the drive pattern is supplied in parallel to the pixels in a plurality of columns of the display panel, the number of wiring connections becomes very large. In addition, it is difficult to adjust the timing for supplying the drive pattern in accordance with the subframe image data.

  Accordingly, an object of the present invention is to eliminate the need to generate a driving pattern supplied in parallel to pixels in a plurality of columns of a display panel in an external circuit, and to reduce the number of wiring connections. Another object of the present invention is to make it possible to dynamically change the driving pattern in synchronization with the subframe period, and to change the driving pattern in response to a temperature change, etc. Is to prevent this from occurring.

  In order to solve the above problems, a display panel driving circuit according to a first aspect of the present invention is formed on a semiconductor substrate constituting a display panel, and represents a subframe obtained by dividing an image of one frame. A display panel driving circuit for driving a display panel based on frame image data and subfield pattern data representing a change in pixel value in one subframe period, and a plurality of registers each holding a plurality of subfield pattern data A subframe counter that generates a count value by counting a subframe synchronization signal, a clock counter that generates a count value by counting a clock signal, and a plurality of values according to the count value generated by the subframe counter. One register out of registers A sub-field pattern generation circuit for sequentially reading out sub-field pattern data from a register selected by the selection circuit according to a count value generated by the clock counter, sub-frame image data, and sub-field pattern data And a pixel circuit that generates a drive pattern for driving the pixels of the display panel by performing a logical operation.

  According to the first aspect of the present invention, since the drive pattern is generated in the display panel drive circuit, it is not necessary to supply the drive pattern from the external circuit to the display panel drive circuit, and the number of wiring connections can be reduced. . In addition, since the drive pattern can be dynamically changed in synchronization with the subframe period, when the drive pattern is changed in response to a temperature change or the like, it is possible to prevent the displayed image from feeling uncomfortable. It becomes possible.

  A display panel driving circuit according to a second aspect of the present invention is formed on a semiconductor substrate constituting a display panel, and includes subframe image data representing a subframe obtained by dividing one frame image, and one subframe. A display panel driving circuit for driving a display panel based on subfield pattern data representing a change in pixel value in a frame period, the receiving circuit receiving subfield pattern data for each subframe, and the receiving circuit receiving the subfield pattern data A register that holds subfield pattern data, a clock counter that generates a count value by counting clock signals, and a subfield pattern generation circuit that sequentially reads subfield pattern data from the register according to the count value generated by the clock counter , By performing a logical operation between the sub-frame image data and the sub-field pattern data, and a pixel circuit for generating a driving pattern for driving the pixels of the display panel.

  According to the second aspect of the present invention, not only the number of wires between the external circuit and the display panel drive circuit can be reduced, but also the number of registers can be reduced. In addition, since the drive pattern can be dynamically changed in synchronization with the subframe period, when the drive pattern is changed in response to a temperature change or the like, it is possible to prevent the displayed image from feeling uncomfortable. It becomes possible.

  In the display panel driving circuit according to the first aspect of the present invention, the subframe synchronization signal and the subfield pattern data are received in a time division manner, the received subframe synchronization signal is supplied to the subframe counter, and the received subframe synchronization data is received. A receiving circuit that supplies field pattern data to a plurality of registers may be further provided. In that case, the number of wires between the external circuit and the display panel driving circuit can be further reduced.

  In the above, the pixel circuit may further include a drive power supply circuit that applies an output potential based on the drive pattern to the individual electrode of the pixel of the display panel and generates a power supply voltage supplied to the pixel circuit according to the drive voltage data. . In that case, since the output potential of the pixel circuit applied to the individual electrode of the pixel of the display panel can be changed according to the temperature of the display panel or the gradation of the image, more accurate gradation Can be reproduced.

  Furthermore, an electronic apparatus according to one aspect of the present invention includes any one of the display panel driving circuits described above, a display panel that displays an image according to a plurality of potentials applied to individual electrodes of a plurality of pixels from the display panel driving circuit, and It comprises. Thereby, in the electronic device, the number of wiring connections can be reduced. In addition, since the drive pattern can be dynamically changed in synchronization with the subframe period, when the drive pattern is changed in response to a temperature change or the like, it is possible to prevent the displayed image from feeling uncomfortable. It becomes possible.

1 is a block diagram including a display panel drive circuit according to a first embodiment of the present invention. The figure which shows the relationship between a flame | frame, a sub-frame, and a subfield. The figure which shows the 1st example of the change of the brightness | luminance by a drive pattern. The figure which shows the 2nd example of the change of the brightness | luminance by a drive pattern. The figure which shows the example of a command and subfield pattern data. FIG. 2 is a circuit diagram illustrating a configuration example of a pixel circuit illustrated in FIG. 1. FIG. 3 is a timing chart for explaining an operation example of the liquid crystal panel drive circuit shown in FIG. 1. The block diagram containing the display panel drive circuit which concerns on the 2nd Embodiment of this invention. The block diagram containing the display panel drive circuit which concerns on the 3rd Embodiment of this invention. The block diagram containing the display panel drive circuit which concerns on the 4th Embodiment of this invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same reference number is attached | subjected to the same component, and the overlapping description is abbreviate | omitted.
FIG. 1 is a block diagram showing a configuration of an electronic apparatus using the display panel drive circuit according to the first embodiment of the present invention. This electronic device is an electronic device such as a video projector or an electronic viewfinder, and FIG. 1 shows only a portion related to image display.

  As shown in FIG. 1, the electronic device includes a display control circuit 10, a display panel drive circuit 20, and a display panel 50. Here, the display panel 50 has a structure in which liquid crystal is sealed between a semiconductor substrate such as single crystal silicon and a glass substrate, and may typically be an LCOS panel. The display panel drive circuit 20 is formed on a semiconductor substrate constituting the display panel 50, and a part of the display panel drive circuit 20 is formed in the display area of the display panel 50.

  The display control circuit 10 includes a subframe image data generation circuit 11, a subfield pattern memory 12, an encoder 13, and a display timing generation circuit 14. The subframe image data generation circuit 11 inputs image data from the outside, and divides one frame image into a plurality of subframes, thereby generating subframe image data representing these subframes.

  The subfield pattern memory 12 is composed of a RAM or the like, and stores subfield pattern data representing various types of preset subfield patterns. Here, the subfield pattern is an array combination of pulses representing a change in pixel value in one subframe period.

  FIG. 2 is a diagram illustrating the relationship among frames, subframes, and subfields. As shown in FIG. 2, for example, an image is represented by 60 frames per second. One frame is composed of a plurality of (for example, 20) subframes. Further, by changing the pixel value of each pixel in one subframe according to the subfield pattern, a finer gradation can be reproduced.

  In FIG. 2, the pixel value of the pixel P in one subframe is changed between the low level and the high level according to the subfield pattern “1101...”. Since the brightness of the liquid crystal appears integrated to the human eye, the desired gradation of the pixel P is reproduced in one frame. Since the change in the pixel value is performed within a period during which one pixel is written to the liquid crystal, if the pixel value changes faster than the response speed of the liquid crystal, the change in luminance in the liquid crystal is not completed, and the transition of the change The status will be displayed.

  In the present embodiment, subfield patterns are not generated based on image data input from the outside, but various subfield patterns are set in advance. Then, for each pixel of the display panel 50, a logical pattern of the subframe image data and the subfield pattern data is performed to generate a drive pattern for driving the pixel.

  For this purpose, the sub-frame image data generation circuit 11 shown in FIG. 1 analyzes the image data for one frame so that one frame image can be reproduced using various preset sub-field patterns. Subframe image data is generated. The display panel drive circuit 20 drives the display panel 50 by generating a drive pattern based on the subframe image data and the subfield pattern data. This will be described in detail later.

  FIG. 3 is a diagram illustrating a first example of a change in luminance according to a drive pattern for a certain pixel. In FIG. 3, the drive pattern “0011” is used to represent the first gradation of the subframe period (A), and the drive pattern “0000” is represented to represent the first gradation of the subframe period (B). ”Is used, and the drive pattern“ 1111 ”is used to represent the first gradation of the subframe period (C). According to each drive pattern, the luminance of the pixel of the display panel 50 changes as shown in FIG.

  FIG. 4 is a diagram illustrating a second example of a change in luminance due to a drive pattern for a certain pixel. In FIG. 4, the symbol “R” represents a period in which the potential applied to the individual electrode of the pixel of the display panel 50 is reset. In FIG. 4, since the potential applied to the individual electrode of the pixel of the display panel 50 is reset at the beginning of each subframe period, the luminance of the pixel of the display panel 50 temporarily decreases.

  FIG. 5 is a diagram illustrating an example of a command and subfield pattern data. When the number of bits of the subfield pattern data is 4 bits, five types of subfield patterns may be used. For example, five types of subfield patterns “0000”, “0001”, “0011”, “0111”, and “1111” are used. Considering a logical operation performed later, the subfield pattern “0000” does not need to be transferred, and FIG. 5 shows an example in which four types of subfield patterns are transferred.

  As shown in FIG. 5, following the command 1 which is an instruction for changing the first subfield pattern, the subfield pattern data “0001” is transferred, and the instruction is for changing the second subfield pattern. Subsequent to command 2, subfield pattern data “0011” is transferred. Further, following the command 3 which is an instruction to change the third subfield pattern, the subfield pattern data “0111” is transferred, and following the command 4 which is an instruction to change the fourth subfield pattern. Subfield pattern data “1111” is transferred.

  Referring again to FIG. 1, the display timing generation circuit 14 receives a reference clock signal, a horizontal synchronization signal, a vertical synchronization signal, and the like, and generates various timing signals. As various timing signals, for example, a subframe synchronization signal representing subframe switching timing, a scanning timing signal representing writing line switching timing in the display panel 50, and timing for generating individual data bits of the subfield pattern. For example, a clock signal indicating

  For example, the encoder 13 shown in FIG. 1 transfers the subfield pattern data stored in the subfield pattern memory 12 to the display panel drive circuit 20 when the electronic device is activated. Also, the encoder 13 adjusts the detected temperature range to correct the luminance change due to the temperature of the display panel 50 when the temperature of the display panel 50 detected by a temperature sensor (not shown) exceeds a predetermined range. The corresponding subfield pattern data may be transferred to the display panel drive circuit 20. Here, the encoder 13 may transfer the subfield pattern data serially together with the command.

  The display panel drive circuit 20 includes a decoder 21, a plurality of subfield pattern registers (hereinafter also simply referred to as “registers”) 22a, 22b, 22c,..., A subframe counter 23, a clock counter 24, and a register. A selection circuit 25, a subfield pattern generation circuit 26, a data line drive circuit 27, a scanning line drive circuit 28, a common potential generation circuit 29, a drive power supply circuit 30, and a plurality of pixel circuits 40 are included. . Those pixel circuits 40 are provided corresponding to a plurality of pixels of the display panel 50.

  The decoder 21 receives the subfield pattern data transferred together with the command from the encoder 13, and sequentially supplies the received subfield pattern data to the registers 22a, 22b, 22c,. Thereby, for example, the register 22a holds the subfield pattern data “0001”, the register 22b holds the subfield pattern data “0011”, and the register 22b holds the subfield pattern data “0111”.

  In this way, the registers 22a, 22b, 22c,... Each hold subfield pattern data representing a plurality of different gradations. In order to represent a plurality of different gradations, the number of bits of the subfield pattern data may be 2 bits or more, for example, 40 bits or more.

  The subframe counter 23 generates a subframe count value by counting the subframe synchronization signal supplied from the display control circuit 10. Further, the subframe counter 23 is reset in synchronization with the vertical synchronization signal supplied from the display control circuit 10.

  The clock counter 24 generates a clock count value by counting the clock signal supplied from the display control circuit 10. The clock counter 24 is reset in synchronization with the subframe synchronization signal supplied from the display control circuit 10.

  The register selection circuit 25 selects one register from a plurality of registers 22a, 22b, 22c,... According to the subframe count value generated by the subframe counter 23. For example, the register selection circuit 25 selects the register 22a when the subframe count value is “0”, selects the register 22b when the subframe count value is “1”, and selects the subframe count value. When “2” is “2”, the register 22c is selected, and so on.

  The subfield pattern generation circuit 26 sequentially reads the subfield pattern data from the register selected by the register selection circuit 25 according to the clock count value generated by the clock counter 24, thereby generating a subfield pattern. The subfield pattern generation circuit 26 supplies the read subfield pattern data to the plurality of pixel circuits 40 through the subfield pattern supply line SL.

  If the number of bits of the subfield pattern data is “N”, for example, the subfield pattern generation circuit 26 reads the first bit of the subfield pattern data when the clock count value is “0”, and the clock count value When “1” is “1”, the second bit of the subfield pattern data is read. Similarly, the subfield pattern generation circuit 26 reads the Nth bit of the subfield pattern data when the clock count value is “N−1”.

  The data line driving circuit 27 distributes and supplies the subframe image data supplied from the display control circuit 10 to the plurality of data lines DL of the display panel 50 according to the scanning timing signal. Sub-frame image data for one column (column) is sequentially supplied to the pixel circuit 40 for one column in the vertical direction in FIG. 1 via one data line DL.

  The scanning line driving circuit 28 generates a plurality of scanning signals for sequentially selecting a plurality of lines of the display panel 50 according to the scanning timing signal, and the generated scanning signals are used as the plurality of scanning lines (gates) of the display panel 50. Line) Supply to GL. One scanning signal is supplied to the pixel circuit 40 for one line in the horizontal direction in FIG. 1 via one scanning line GL.

The common potential generation circuit 29 generates a common potential COM that is supplied to the common electrode of the display panel 50. The drive power supply circuit 30 generates a power supply voltage (V _DD −V _SS ) supplied to the plurality of pixel circuits 40. For example, as shown in FIG. 1, the drive power supply circuit 30 may generate one power supply potential V _DD and the other power supply potential _VSS as the ground potential.

  The pixel circuit 40 drives the pixels of the display panel 50 by performing a logical operation on the subframe image data supplied from the data line driving circuit 27 and the subfield pattern data supplied from the subfield pattern generation circuit 26. A driving pattern is generated. Further, the pixel circuit 40 applies an output potential based on the drive pattern to the individual electrodes of the pixels of the display panel 50.

  FIG. 6 is a circuit diagram showing a configuration example of the pixel circuit shown in FIG. In the display panel 50, a plurality of pixels are arranged in a two-dimensional matrix. In FIG. 6, pixel circuits for 2 × 2 pixels are shown. These pixel circuits are connected to data lines DL1 and DL2, scanning lines GL1 and GL2, and a subfield pattern supply line SL. In the following, the pixel circuit in the first row and the first column will be described as an example.

As shown in FIG. 6, the pixel circuit 40 includes an N-channel transistor 41, two inverters 42 and 43, and an AND circuit 44. The capacitance formed between the individual electrode and the common electrode in the liquid crystal pixel of the display panel 50 is indicated by the reference symbol “C”. The inverters 42 to AND circuit 44 are supplied with power supply potentials V _DD and V _SS from the drive power supply circuit 30 (FIG. 1).

  The source of the transistor 41 is connected to the data line DL 1, the gate is connected to the scanning line GL 1, and the drain is connected to the input terminal of the inverter 42. The output terminal of the inverter 42 is connected to the input terminal of the inverter 43. The output terminal of the inverter 43 is connected to the input terminal of the inverter 42 and to the first input terminal of the AND circuit 44. Subfield pattern data is supplied to the second input terminal of the AND circuit 44 via the subfield pattern supply line SL, and the output terminal is connected to the individual electrode of the pixel of the display panel 50. On the other hand, the common potential COM is applied to the common electrode of the display panel 50 from the common potential generation circuit 29 (FIG. 1).

  In the pixel circuit 40 configured as described above, when the scanning signal supplied to the scanning line GL1 is activated to a high level, the transistor 41 is turned on, and the subframe image data supplied to the data line DL1 is converted into an inverter. 42 input terminals. This subframe image data is inverted twice by the inverters 42 and 43 and output from the output terminal of the inverter 43. Since the output signal of the inverter 43 is positively fed back to the input terminal of the inverter 42, the output level of the inverter 43 is maintained even when the transistor 41 is turned off.

  The AND circuit 44 generates a drive pattern by obtaining a logical product of the subframe image data output from the inverter 43 and the subfield pattern data supplied via the subfield pattern supply line SL, and based on the drive pattern The output potential is applied to the individual electrodes of the pixels of the display panel 50. As a result, the liquid crystal of the pixel is driven by the potential difference between the output potential of the AND circuit 44 applied to the individual electrode and the common potential COM applied to the common electrode.

  FIG. 7 is a timing chart for explaining an operation example of the liquid crystal panel drive circuit shown in FIG. As shown in FIG. 7, one frame period represented by the vertical synchronization signal is divided into a plurality of subframe periods. Here, in order to simplify the description, a case where one frame is divided into four and subframes 1 to 4 are generated will be described.

  In order to scan a plurality of lines of the display panel 50 in one subframe period, a scanning timing signal is generated. One cycle of the scanning timing signal corresponds to one pixel writing period because data is simultaneously written to pixels for one line of the display panel 50. If the sub-field pattern generated in this one-pixel writing period is “0110” and the sub-frame image data is high level “H”, the drive pattern output from the AND circuit 44 (FIG. 6) is “ LHHL "and the potential of the individual electrode changes in the same manner. On the other hand, if the sub-frame image data is at the low level “L”, the drive pattern output from the AND circuit 44 is “LLLL”, and the potentials of the individual electrodes change similarly.

  Since the gradation of the subfield pattern selected by the register selection circuit 25 changes depending on the subframe, the display control circuit 10 generates display data by generating appropriate subframe image data according to the temporal position of the subframe. A desired gradation can be reproduced in an image for one frame displayed on the panel 50.

  As described above, according to the first embodiment of the present invention, since the drive pattern is generated in the display panel drive circuit 20, it is not necessary to supply the drive pattern from the external circuit to the display panel drive circuit 20, and the wiring connection The number can be reduced. In addition, since the drive pattern can be dynamically changed in synchronization with the subframe period, when the drive pattern is changed in response to a temperature change or the like, it is possible to prevent the displayed image from feeling uncomfortable. It becomes possible.

Next, a second embodiment of the present invention will be described.
FIG. 8 is a block diagram showing a configuration of an electronic apparatus using the display panel drive circuit according to the second embodiment of the present invention. In the second embodiment, the display control circuit 10a further includes a drive voltage control circuit 15, and the drive power supply circuit 30a is used in the display panel drive circuit 20a. Other points are the same as those of the first embodiment shown in FIG.

  The drive voltage control circuit 15 of the display control circuit 10a generates and generates drive voltage data in order to change the power supply voltage supplied to the pixel circuit 40 according to the temperature of the display panel 50 or the gradation of the image. Is supplied to the display panel drive circuit 20a.

  For example, the drive voltage control circuit 15 supplies drive voltage data to the display panel drive circuit 20a when the electronic device is activated. In addition, the drive voltage control circuit 15 detects the detected temperature in order to correct the luminance change due to the temperature of the display panel 50 when the temperature of the display panel 50 detected by a temperature sensor (not shown) exceeds a predetermined range. The drive voltage data stored corresponding to the range may be supplied to the display panel drive circuit 20a. Alternatively, the drive voltage control circuit 15 generates drive voltage data according to the gradation of the image, and supplies the drive voltage data to the display panel drive circuit 20a during the vertical synchronization period, horizontal synchronization period, or subframe synchronization period. You may do it.

The drive power supply circuit 30a of the display panel drive circuit 20a includes a drive voltage register 31, a DAC (digital / analog converter) 32, and a regulator 33, and is supplied to the plurality of pixel circuits 40 in accordance with the drive voltage data. A power supply voltage (V _DD −V _SS ) is generated. For example, as shown in FIG. 8, the drive power supply circuit 30a may generate one power supply potential V _DD and the other power supply potential _VSS as a ground potential.

  The drive voltage register 31 stores drive voltage data supplied from the drive voltage control circuit 15. The DAC 32 converts the drive voltage data stored in the drive voltage register 31 into an analog drive voltage. The regulator 33 buffers the drive voltage output from the DAC 32 and generates a power supply voltage supplied to the plurality of pixel circuits 40.

  According to the second embodiment of the present invention, the output potential of the pixel circuit 40 applied to the individual electrodes of the pixels of the display panel 50 can be changed according to the temperature of the display panel 50 and the gradation of the image. In the display panel 50, more accurate gradation can be reproduced.

  In the second embodiment, the drive voltage data may be changed according to the subframe count value generated by the subframe counter 23 without providing the drive voltage control circuit 15. In that case, since the subfield pattern changes for each subframe and the power supply voltage supplied to the plurality of pixel circuits 40 also changes, it is finer than the case where only the subfield pattern is changed. It is possible to reproduce gradation.

Next, a third embodiment of the present invention will be described.
FIG. 9 is a block diagram showing a configuration of an electronic apparatus using the display panel drive circuit according to the third embodiment of the present invention. In the third embodiment, a transmission circuit 61 is used in the display control circuit 10b, and a reception circuit 71 is used in the display panel drive circuit 20b. Other points are the same as those of the first embodiment shown in FIG.

  The transmission circuit 61 of the display control circuit 10b transmits the subframe synchronization signal generated by the display timing generation circuit 14 to the display panel drive circuit 20b in time division with the subfield pattern data stored in the subfield pattern memory 12. To do. For example, the transmission circuit 61 may transmit a subframe synchronization signal in a subframe synchronization period and transmit subfield pattern data in other periods. Here, the transmission circuit 61 may transmit the subfield pattern data serially together with the command.

  The reception circuit 71 of the display panel drive circuit 20b receives the subframe synchronization signal and the subfield pattern data transmitted from the transmission circuit 61 in a time division manner. The reception circuit 71 supplies the received subframe synchronization signal to the subframe counter 23 and the clock counter 24, and sequentially supplies the received subfield pattern data to the plurality of registers 22a, 22b, 22c,.

  According to the third embodiment of the present invention, the display circuit driving circuit 20b is provided with the receiving circuit 71 that receives the subframe synchronization signal and the subfield pattern data transmitted from the display control circuit 10b in a time-sharing manner. The number of wirings between the control circuit 10b and the display panel drive circuit 20b can be further reduced.

  In the third embodiment, the drive voltage control circuit 15 (FIG. 8) may be provided in the display control circuit 10b, and the drive power supply circuit 30a (FIG. 8) may be used in the display panel drive circuit 20b. In that case, the transmission circuit 61 of the display control circuit 10b transmits the drive voltage data generated by the drive voltage control circuit 15 to the display panel drive circuit 20b in a time division manner with the subframe synchronization signal and the subfield pattern data. .

  The receiving circuit 71 of the display panel driving circuit 20b receives the driving voltage data, the subframe synchronization signal, and the subfield pattern data in a time division manner. The reception circuit 71 supplies the received drive voltage data to the drive power supply circuit 30a, supplies the received subframe synchronization signal to the subframe counter 23 and the clock counter 24, and receives the received subfield pattern data from the plurality of registers 22a, 22b, 22c,... Are sequentially supplied.

Next, a fourth embodiment of the present invention will be described.
FIG. 10 is a block diagram showing a configuration of an electronic apparatus using the display panel drive circuit according to the fourth embodiment of the present invention. In the fourth embodiment, the transmission circuit 62 is used in the display control circuit 10c, and the reception circuit 72 is used in the display panel drive circuit 20c. Further, since only one subfield pattern register 22 is used in the display panel drive circuit 20c, the subframe counter 23 and the register selection circuit 25 in FIG. 1 are not necessary. Other points are the same as those of the first embodiment shown in FIG.

  The transmission circuit 62 of the display control circuit 10c transmits the subframe synchronization signal generated by the display timing generation circuit 14 to the display panel drive circuit 20c in time division with the subfield pattern data stored in the subfield pattern memory 12. To do. At that time, the transmission circuit 62 transmits the subfield pattern data for each subframe. That is, the transmission circuit 62 transmits subfield pattern data for the next subframe during the period in which one subframe is displayed. Here, the transmission circuit 62 may transmit the subfield pattern data serially together with the command.

  The reception circuit 72 of the display panel drive circuit 20c receives the subframe synchronization signal and subfield pattern data transmitted from the transmission circuit 62 in a time division manner. At that time, the reception circuit 72 receives the subfield pattern data transmitted from the transmission circuit 62 for each subframe. That is, the receiving circuit 72 receives subfield pattern data for the next subframe during a period in which one subframe is displayed. The receiving circuit 72 supplies the received subframe synchronization signal to the clock counter 24 and supplies the received subfield pattern data to the subfield pattern register 22.

  The subfield pattern register 22 holds the subfield pattern data received by the receiving circuit 72. The subfield pattern generation circuit 26 sequentially reads the subfield pattern data from the subfield pattern register 22 according to the clock count value generated by the clock counter 24, and uses the read subfield pattern data as the subfield pattern supply line SL. Are supplied to a plurality of pixel circuits 40 via The subsequent operation is the same as that of the first embodiment shown in FIG.

  According to the fourth embodiment of the present invention, not only the number of wirings between the display control circuit 10c and the display panel drive circuit 20c can be reduced, but also the number of registers can be reduced. In addition, since the drive pattern can be dynamically changed in synchronization with the subframe period, when the drive pattern is changed in response to a temperature change or the like, it is possible to prevent the displayed image from feeling uncomfortable. It becomes possible.

  In the fourth embodiment, the drive voltage control circuit 15 (FIG. 8) may be provided in the display control circuit 10c, and the drive power supply circuit 30a (FIG. 8) may be used in the display panel drive circuit 20c. In that case, the transmission circuit 62 of the display control circuit 10c transmits the drive voltage data generated by the drive voltage control circuit 15 to the display panel drive circuit 20c in a time division manner with the subframe synchronization signal and the subfield pattern data. .

  The reception circuit 72 of the display panel drive circuit 20c receives the drive voltage data, the subframe synchronization signal, and the subfield pattern data in a time division manner. The reception circuit 72 supplies the received drive voltage data to the drive power supply circuit 30a, supplies the received subframe synchronization signal to the clock counter 24, and supplies the received subfield pattern data to the register 22.

  The present invention is not limited to the embodiments described above, and many modifications can be made within the technical idea of the present invention by those having ordinary knowledge in the technical field.

  DESCRIPTION OF SYMBOLS 10, 10a, 10b, 10c ... Display control circuit, 11 ... Sub-frame image data generation circuit, 12 ... Subfield pattern memory, 13 ... Encoder, 14 ... Display timing generation circuit, 15 ... Drive voltage control circuit 20, 20a, 20b, 20c ... display panel drive circuit, 21 ... decoder, 22, 22a, 22b, 22c ... subfield pattern register, 23 ... subframe counter, 24 ... clock counter, 25 ... register selection circuit, 26 ... subfield pattern generation circuit , 27 ... Data line drive circuit, 28 ... Scan line drive circuit, 29 ... Common potential generation circuit, 30, 30a ... Drive power supply circuit, 31 ... Drive voltage register, 32 ... DAC, 33 ... Regulator, 40 ... Pixel circuit, 41 ... N-channel transistors, 42, 43 Inverter, 44 ... AND circuit, 50 ... Display panel, 61, 62 ... Transmitter circuit, 71, 72 ... Receiver circuit, DL, DL1, DL2 ... Data line, GL, GL1, GL2 ... Scan line, SL ... Subfield pattern supply line

Claims (5)

Based on subframe image data representing a subframe obtained by dividing one frame of an image formed on a semiconductor substrate constituting the display panel, and subfield pattern data representing a change in pixel value in one subframe period A display panel driving circuit for driving the display panel,
A plurality of registers each holding a plurality of subfield pattern data;
A subframe counter that generates a count value by counting the subframe synchronization signal;
A clock counter that generates a count value by counting the clock signal;
A selection circuit for selecting one of the plurality of registers according to a count value generated by the subframe counter;
A subfield pattern generation circuit for sequentially reading subfield pattern data from a register selected by the selection circuit according to a count value generated by the clock counter;
A pixel circuit that generates a drive pattern for driving the pixels of the display panel by performing a logical operation of the subframe image data and the subfield pattern data;
A display panel driving circuit comprising: Based on subframe image data representing a subframe obtained by dividing one frame of an image formed on a semiconductor substrate constituting the display panel, and subfield pattern data representing a change in pixel value in one subframe period A display panel driving circuit for driving the display panel,
A receiving circuit for receiving subfield pattern data for each subframe;
A register for holding subfield pattern data received by the receiving circuit;
A clock counter that generates a count value by counting the clock signal;
A subfield pattern generation circuit for sequentially reading subfield pattern data from the register according to a count value generated by the clock counter;
A pixel circuit that generates a drive pattern for driving the pixels of the display panel by performing a logical operation of the subframe image data and the subfield pattern data;
A display panel driving circuit comprising:   A receiving circuit for receiving the subframe synchronization signal and the subfield pattern data in a time division manner, supplying the received subframe synchronization signal to the subframe counter, and supplying the received subfield pattern data to the plurality of registers; The display panel drive circuit according to claim 1, further comprising: The pixel circuit applies an output potential based on a driving pattern to individual electrodes of pixels of the display panel,
The display panel drive circuit according to claim 1, further comprising a drive power supply circuit that generates a power supply voltage to be supplied to the pixel circuit according to drive voltage data. A display panel drive circuit according to any one of claims 1 to 4,
A display panel for displaying an image according to a plurality of potentials applied to individual electrodes of a plurality of pixels from the display panel driving circuit;
An electronic device comprising:

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