JPH06105776B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a direct contact region.

[Prior Art] One of semiconductor devices has an SRAM (Static Random Access Memory) Since SRAM memory cells are composed of flip-flops, the stored information in the SRAM disappears with time while the power is turned on. There is nothing to do. Therefore SR
In AM, unlike in DRAM (Random Access Memory), it is not necessary to rewrite the stored information, that is, to perform refrewing. In addition, SRAM generally consumes less power during operation / data retention and can operate at high speed. From these advantages
SRAM is used in many fields. Even in such an SRAM, the storage capacity is increasing, that is, the number of memory cells on one chip is steadily increasing. Along with this, miniaturization of memory cells is essential. The SRAM memory cells are roughly classified into a CMOS type composed of two P-channel transistors and four N-channel transistors,
It is divided into a high resistance load type composed of four N-channel transistors and two high resistances. The latter is advantageous for large-capacity SRAM because it enables a three-dimensional structure compared to the former. Therefore, this type is mainly used for SRAM with a capacity larger than 64k SRAM.

FIG. 4 is a circuit diagram showing an equivalent circuit of a high resistance load type memory cell. Referring to the figure, this circuit is an N channel MOS
Access transistors 1a and 1b, which are transistors
Inverter transistors 2a and 2b which are N-channel MOS transistors, high resistances 3a and 3b, bit lines 4 and 5 when signals complementary to each other are transmitted, and word line 8 connected to the gates of transistors 1a and 1b. , A cross-coupled wiring 6a connecting the source (or drain) of the transistor 1a and the gate of the transistor 2b,
Cross-couple wiring 6b connecting the source (or drain) of transistor 1b and the gate of transistor 2a
And the source (or drain) of transistor 1a, the source (or drain) of transistor 2a, and high resistance
Storage node 7a, which is the common connection point of 3a, and transistor 1b
Source (or drain), the source (or drain) of the transistor 2b, and the storage node 7b which is a common connection point of the high resistance 3b. The transistor 1a is provided between the storage node 7a and the bit line 4 and
1b is provided between the storage node 7b and the bit line 5. In addition, the circuit composed of the transistors 7a and 7b cross-coupled as described above and the high resistances 3a and 3b includes a V _cc wiring 41 to which a power supply voltage V _cc is applied and a ground wiring 40 to which a ground potential is applied. It is provided between. At the time of data writing, access transistors 1a and 1b are rendered conductive by the voltage applied to the word line, and the signal voltages applied to bit lines 4 and 5 are transmitted to storage nodes 7a and 7b, respectively. Since the signal voltages are complementary to each other, either one of the inverter transistors 2a or 2b becomes conductive and the other becomes non-conductive. Therefore, storage nodes 7a and 7b
Holds the complementary signal voltage applied to bit lines 4 and 5, and the data writing is completed. When the data writing is completed, the access transistor becomes non-conductive again. In addition,
At the time of data reading, access transistors 1a and 1b are both rendered conductive and the voltages held at storage nodes 7a and 7b are taken out from bit lines 4 and 5, respectively.

In order to miniaturize the memory cell having the above structure on one chip, it is necessary to pay attention to the following points. First,
It is necessary to minimize the number of aluminum wires. Further, it is necessary to minimize the wiring resistance of the bit lines 4 and 5 and the word line 8 in order to reduce the delay of the access time required for writing and reading data.
Further, since this memory cell is composed of a flip-flop, it is important to make the memory cell symmetrical as much as possible in order to stabilize the memory cell. Therefore, the layout of the cross-coupled wirings 6a and 6b, which is difficult to be symmetrically arranged, is important.

Taking the above into consideration, when this memory cell is formed on the P-type semiconductor substrate, the first multi-layer structure is used in which the bit lines 4 and 5 are the aluminum wiring layers and the word lines 8 are the gate electrodes of the transistors 1a and 1b. First crystalline silicon layer, _Vcc wiring 41
The low resistance portion of the second polycrystalline silicon layer formed on the upper portion of the polycrystalline silicon layer via an insulating layer, and the ground wiring 40 as an n ⁺ diffusion layer or a source (or drain) of the transistors 2a and 2b. 1 polycrystalline silicon layer, high resistance 3a
And 3b are the high resistance portion of the second polycrystalline silicon layer, one of the cross-coupled wiring portions 6a and 6b is an n ⁺ diffusion layer, and the other one is the first polycrystalline silicon layer or the second polycrystalline silicon layer. Use of a low resistance part makes layout easier.

In such a case, storage nodes 7a and 7b have n ⁺ diffusion layers,
It becomes a common connection region with the first and second polycrystalline silicon layers.

Generally, when many wirings must be provided in a small area, the connection between the polycrystalline silicon layer that forms the gate of a transistor and the diffusion layer that forms the source and drain of another transistor is led by a metal wiring layer such as aluminum. Done without doing. That is, the gate of a transistor is connected to the source or drain of another transistor by so-called direct contact, which is a direct contact between the polycrystalline silicon layer and the diffusion layer. Therefore, such miniaturization of the direct contact region is important in miniaturizing the semiconductor device. Therefore, in manufacturing a semiconductor device, a hole is formed in the first polycrystalline silicon layer and the n ⁺ diffusion layer in order to minimize the direct contact region, and a second polycrystalline silicon layer is formed so as to cover the hole. A shared direct contact that is formed and used as a wiring is often used. Therefore, the storage node 7a of the memory cell shown in FIG.
7b is also formed by this shared type direct.

FIG. 5 is a diagram showing an example of an actual layout when the memory cell shown in FIG. 4 is formed on a P-type semiconductor substrate using the shared direct contact as described above. In the figure, the numbers in parentheses are the numbers of the corresponding parts in FIG.

As shown, the word line 8 is common with the first polycrystalline silicon layer 51 (hatched portion in the drawing) forming the gates of the access transistors 1a and 1b. The gates of the inverter transistors 2a and 2b are also formed of the first polycrystalline silicon layer 51. However, a portion corresponding to the gates of the inverter transistors 2a and 2b of the first polycrystalline silicon layer,
It is not connected to the portions corresponding to the gates of access transistors 1a and 1b. The _Vcc wiring 41 and the high resistances 3a and 3b are formed by the second polycrystalline silicon layer 52 (the portion surrounded by the broken line in the figure) (however, the second polycrystalline silicon layer in the portion which should become the _Vcc wiring 41). Has a low resistance), and high resistances 3a and 3b are inverter transistors 1a and 3b, respectively.
Located at the top of 1b. The cross-coupled wiring 6a is common with the n ⁺ diffusion layer region 53 (the portion surrounded by the solid line in the figure) forming the source and drain of the access transistor 1b,
The cross-coupled wiring 6b is commonly connected at the direct contact portion D1 to the first polycrystalline silicon layer 51 forming the gate of the inverter transistor 2a and the n ⁺ diffusion layer region 53 forming the source and drain of the access transistor 1a. It is formed by the second polycrystalline silicon layer 52.
Storage nodes 7a and 7b are direct contact portions D1 and D2, respectively, in which first and second polycrystalline silicon layers 51 and 52 and n ⁺ diffusion region 53 overlap each other. Note that a transistor used in a memory cell has a so-called LDD (lightly
It has a doped drain) structure.

Hereinafter, a conventional method of manufacturing a semiconductor device including a shared direct contact region will be described with reference to FIG. FIG. 6 is a partial sectional view of the memory cell laid out as shown in FIG. 5, taken along the line aa 'in FIG.

First, the field oxide film 54 is selectively formed on the P-type substrate 63. At this time, in order to prevent polarity reversal of the P-type substrate 63, P-type impurities are implanted under the field oxide film 54 to form a P ⁺ isolation region 58.

Next, a thin oxide film to be the gate oxide film 56 is formed on the P-type substrate 63 excluding the field oxide film 54, and then the first polycrystalline silicon layer is formed on the thin oxide film and the field oxide film 54. Deposit polycrystalline silicon to be 51. Further, phosphorus is introduced into the deposited polycrystalline silicon by phosphorus deposition to lower the resistance. After patterning the low-resistance polycrystalline silicon and the thin oxide film thus formed by the usual lithography,
Anisotropic etching is performed to remove unnecessary portions to obtain first polycrystalline silicon layer 51 and gate oxide film 56. This completes the gate electrodes of transistors 1a and 2a.

Next, using the first polycrystalline silicon layer 51 as a mask, the P-type substrate 63 is formed.
A small amount of phosphorus is added on top by ion implantation to form the n ⁻ diffusion layer region 55.

Next, a high temperature oxide film is formed by CVD (chemical vapor deposition) on the entire surface of the P-type substrate 15 including the first polycrystalline silicon layer 51. Then, the generated high temperature oxide film is anisotropically etched until the first polycrystalline silicon layer 51 is exposed. As a result, a high temperature oxide film remains on the peripheral side wall (end in the figure) of the first polycrystalline silicon layer 51. This is a side spacer (sidewall insulating film) 62.

Next, a large amount of arsenic is added to the P type substrate 63 by ion implantation using the side spacer 62 as a mask to form it in the n ⁺ diffusion layer region 53.

Next, the n ⁻ diffusion layer 55 and the n ⁺ diffusion layer 53 are activated by heat treatment. I complete the sources and drains of transistors 1a and 2a.

After that, an insulating oxide film to be the interlayer oxide film 60 is formed by CVD or the like on the entire surface of the P type substrate 63 including the first polycrystalline silicon layer 51 and the n ⁺ diffusion layer region 53. Next, after patterning by ordinary lithography, the unnecessary insulating oxide film is removed by dry etching to obtain an interlayer oxide film 60.

Next, a polycrystalline silicon layer to be the second polycrystalline silicon layer 52 is formed on the entire surface of the P-type substrate 65 including the interlayer oxide film 60 by CVD.
To form. Thereby, the first polycrystalline silicon layer
51 and the n ⁺ diffusion layer region 53 are connected via this polycrystalline silicon layer (the portion of the direct contact portion D1). Subsequently, a portion of the polycrystalline silicon layer that should have a high resistance is masked, and a large amount of arsenic is added to the other portions by ion implantation to reduce the resistance of the portion. As a result, this polycrystalline silicon layer has a high resistance 3a and V _cc.
Separated into the luck that will be the wiring. Then, an unnecessary portion of this polycrystalline silicon layer is removed by etching to obtain a second polycrystalline silicon layer 52. This completes the high resistance 3a and _Vcc wiring 41.

Finally, the protective film PSG (phospho-silicat) is formed by CVD.
e glass) film 61 is formed. Finally, this is reflowed by heat treatment to smooth the surface.

As described above, the semiconductor device including the direct contact region is completed.

[Problems to be Solved by the Invention] The conventional shared type direct contact has the following problems because it is formed by the above steps.

As can be seen from FIG. 6, side spacers, which are insulating films, remain in the direct contact region. Therefore, the contact area between the first and second polycrystalline silicon layers and the n ⁺ diffusion layer region in the direct contact is effectively reduced by the side spacer. Therefore, the contact resistance of the direct contact increases. In the case of SRAM memory cells, this causes problems such as a signal being hard to be transmitted to the storage node. It goes without saying that such an increase in the resistance of the portion that should be electrically conducted is not preferable not only for the SRAM memory cell but also for the semiconductor device using the direct contact. In the conventional example, the side spacer is LD
Although it is formed to obtain the D-structure transistor, the purpose of forming the side spacer is not limited to this.

Conventionally, a method of removing the side spacers remaining in the direct contact by wet etching using fluorine water or the like has been considered. However, it is difficult to remove only the side spacers by such a method, and the periphery of the side spacers is inevitably etched. For this reason, the direct contact area becomes large and it becomes difficult to completely cover the direct contact portion when forming the second polycrystalline silicon layer after forming the interlayer oxide film.

An object of the present invention is to solve the above problems and provide a method of manufacturing a semiconductor device including a direct contact region that does not affect the contact resistance of the side spacer.

[Means for Solving the Problems] In order to achieve the above-mentioned object, a method for manufacturing a semiconductor device according to the present invention includes: a first element formation region in which a first field effect transistor is formed; And a second element formation region in which the field effect transistor of 2 is formed,
A step of forming an isolation layer between the first and second element formation regions, a gate electrode of a first field effect transistor provided on the first element formation region via a gate insulating film, Forming a first conductive layer extending from the gate electrode on the separation layer and the second element formation region and having an end portion provided on the second element formation region with an insulating film interposed therebetween; Using the gate electrode portion of the first conductive layer as a part of the mask, the pair of source / drain regions of the first field effect transistor are formed with the low impurity diffusion regions in the first element formation region, and the first conductive layer is formed. Forming a low impurity diffusion region of one of the source / drain regions of the second field effect transistor by using the end of the layer as a part of the mask; and forming a side wall and an end of the gate electrode part of the first conductive layer. Form side spacers on the side walls The step of forming side spacers on the side wall of the gate electrode portion and the side wall of the end portion of the first conductive layer and the side spacer formed on the side wall of the gate electrode portion and the gate electrode portion of the first conductive layer. As a part of the mask, a high impurity diffusion region of a pair of source / drain regions of the first field effect transistor is formed in the first element formation region, and an end portion of the first conductive layer and a side wall of this end portion are formed. Forming a high impurity diffusion region of one of the source / drain regions of the second field effect transistor by using the side spacer formed on the mask as a part of the mask, and on the surface of the semiconductor substrate including on the first conductive layer. And a step of forming an interlayer insulating film on the second conductive layer, and an end portion of the interlayer insulating film, the first conductive layer, and a side spacer formed on the side wall of this end portion, which should be a region to be directly contacted by the second conductive layer. Removing the support, and generating an exposed surface to one of the source / drain regions of the first conductive layer and the second field effect transistor, the second
Activating one of the source / drain regions of the field-effect transistor to diffuse the source / drain region of the second field-effect transistor to near the exposed surface of the first conductive layer; Forming a second conductive layer that directly connects the exposed surface of one of the source / drain regions of the field effect transistor and the exposed surface of the first conductive layer.

[Operation] The method for manufacturing a semiconductor device according to the present invention includes the step of removing the side spacers located in the direct contact region. Therefore, the side spacer does not remain in the direct contact region, and the area occupied by the insulating film in the manufactured direct contact region is eliminated. Furthermore, since the method for manufacturing a semiconductor device according to the present invention includes a step of diffusing one source / drain region of the second field effect transistor to the vicinity of the exposed surface of the first conductive layer, direct contact after manufacturing is performed. The contact area between the second conductive layer and the diffusion layer in the region is expanded.

[Embodiment] FIGS. 1 and 2 are views showing an embodiment of the present invention. FIG. 1 (a) is a partial plan view of a semiconductor device laid out by using a shared direct contact, and in particular, like the conventional example shown in FIG. 6, an inverter serving as a first field effect transistor. Transistor TR1
Gate electrode (formed of the first conductive layer) and the access transistor TR which becomes the second field effect transistor
2 shows a portion where the second source / drain region is in direct contact with the second conductive layer. Referring to the figure, the first polycrystalline silicon layer 9 serving as the first conductive layer is formed on the first element formation region of the semiconductor substrate, which is the P-type silicon substrate 15, as shown in FIG. A gate electrode of the LDD transistor TR1 which is an inverter transistor provided through the oxide film 16 and a P-type silicon substrate which is a P-type silicon substrate 15 from this gate electrode.
The surface of 15 extends over the isolation layer, which is the field oxide film 14 formed between the first and second element formation regions, and the second element formation region of the P-type silicon substrate 15, An end portion 9a provided via an insulating film is formed on the second element formation region. The side spacers 10 are formed on the sidewalls of the gate electrode portion of the transistor TR1 and the sidewalls of the end portion 9a of the first polycrystalline silicon layer 9. P on both sides of the gate electrode portion of the transistor TR1 in the first polycrystalline silicon layer 9
Type silicon substrate 15 provided on the surface of n ⁺ diffusion layer region 12a
Is a pair of source / drain regions of the transistor TR1, and is an n ⁺ diffusion layer region provided on the surface of the P-type silicon substrate 15 on the side wall of the end portion 9a of the first polycrystalline silicon layer 9.
12b forms one source / drain region of the transistor TR2. Further, the gate electrode of the transistor TR1 and one source / drain region of the transistor TR2 are 12b,
A direct contact portion 11 is formed to connect to the second polycrystalline silicon layer 13 formed of the second conductive layer in which the high resistance body is formed, at a common connection point. A field oxide film 14 is formed between the circuit elements TR1 and TR2 and other circuit elements (not shown) to form them separately. However, unlike the prior art, the portions of the first polycrystalline silicon layer 9a and the side spacers 10a included in the direct contact portion 11 are removed in the manufacturing process. Further, an n-type diffusion layer region (n ⁺⁺ diffusion layer region 21) is formed on the entire surface of the substrate 15 including the direct contact portion 11.

FIG. 1 (b) shows a straight line b- in the portion shown in FIG. 1 (a).
It is sectional drawing at the time of cutting in b '. As shown in the figure,
Unlike the conventional case, no side spacer remains in the direct contact portion 11. Therefore, the connection area in the direct contact is not effectively reduced by the side spacer unlike the conventional case. For this reason, the contact resistance in the direct contact becomes smaller than in the conventional case. Further, the entire surface n ⁺⁺ diffusion layer region 21 of the substrate 15 included in the direct contact portion 11 is formed. Here, the n ^{+ +} diffusion layer region 21 is a part of the n ⁺ diffusion layer region 12b which is one source / drain region of the transistor TR2. Therefore, in direct contact 11, the contact area between second polycrystalline silicon layer 13 and n ⁺ diffusion layer region 12b becomes larger than in the conventional case. Therefore, the contact resistance between them is also smaller than in the conventional case. That is, the contact resistance between the first and second polycrystalline silicon layers and the n ⁺ diffusion layer region 12b in direct contact is smaller than that in the conventional case.

FIG. 2 is a sectional view showing a manufacturing process of a semiconductor device including the direct contact portion 11 as shown in FIG. 1 (b).

Considering FIG. 2A, first, the field oxide film 14 is formed on the P-type silicon substrate 15 by LOCOS (selective oxidation method). At this time, boron is added below the field oxide film 14 by ion implantation to form a P ⁺ isolation region 18. This is to prevent the polarity reversal of the substrate 15 as in the conventional case. Next, so that the threshold voltage of the transistors TR1 and TR2 becomes a desired value, the transistor TR of the substrate 15 is
A channel dove region (not shown) in which boron is added by ion implantation to a portion to be under the gate electrode of 1 and TR2
To form. Next, a thin oxide film 16 to be a gate oxide film having a thickness of about 20 nm is formed on the substrate 15 excluding the field oxide film 14 by thermal oxidation. Then, the first by CVD
Substrate 15 made of polycrystalline silicon to be the polycrystalline silicon layer of
After depositing on the entire upper surface, phosphorus of high concentration is injected into this by phosphorus devotion to reduce the resistance.
Next, after patterning by ordinary lithography, the deposited polycrystalline silicon layer 9 is etched with a fluorine-based gas to remove unnecessary portions, and a first polycrystalline silicon layer and a gate oxide film are obtained. This allows the transistor
The TR1 and TR2 gate electrodes are completed.

Next, referring to FIG. 2 (b), phosphorus having a concentration of about 1 × 10 ¹³ cm ⁻² is implanted into the substrate 15 by ion implantation using the first polycrystalline silicon layer 9 as a mask, and n ⁻ diffusion layer is formed. Form 17. The illustrated n ⁻ diffusion layer 17 is a low impurity diffusion region for forming one source / drain region of the transistor TR2, and a low impurity diffusion region for forming a pair of source / drain regions of the transistor TR1. Are not shown. Then, the first polycrystalline silicon layer 9 is formed by CVD.
An insulating oxide film (not shown) having a thickness of about 300 nm is deposited on the entire surface of the substrate 15 including the upper part, and this is changed by a mixed gas of CHF ₃ and oxygen until the first polycrystalline silicon layer 9 is exposed. Isotropically etched. As a result, the side spacers 10 are formed on the peripheral side wall of the first polycrystalline silicon layer 9, that is, the side wall of the gate electrode portion of the transistor TR1 and the side wall of the end portion 9a.

Next, referring to FIG. 2 (c), the first polycrystalline silicon layer 9 and the side spacers 10 are implanted into the substrate 15 by arsenic having a concentration of about 3 × 10 ₁₅ cm ^-2 by ion implantation using a mask. n ⁺
A diffusion layer region 12 is formed. Note that the illustrated n ⁺ diffusion layer 12
Is a high impurity diffusion region for forming one source / drain region of the transistor TR2,
The high impurity diffusion regions for forming the two pairs of source / drain regions are not shown. Subsequently, the ions added by the ion implantation are activated by high temperature heat treatment. This completes the sources and drains of transistors TR1 and TR2. Next, an interlayer oxide film 19 having a thickness of about 200 nm is formed by CVD on the first polycrystalline silicon layer 9, the field oxide film 14 and the n ⁺ diffusion layer region 12. Next, a resist film is formed on the entire surface of the oxide film 19, and patterning is performed by ordinary lithography to remove the resist film in the portion that will become the direct contact portion 11. As a result, the resist film with the pattern as shown
You get 24. At this time, it is desirable to set the position of the direct contact portion 11 as follows in consideration of a deviation between a desired resist pattern and an actually obtained resist pattern during lithography. That is, the contact area between the first polycrystalline silicon layer 9 and the substrate 15 and the contact area between the side spacer 10 and the n ⁺ diffusion layer 12 and the substrate 15 are substantially equal to each other in the region to be the direct contact portion 11. The direct contact portion 11 is set to the position (see FIG. 2 (c)). By doing so, even if the portion to be the direct contact portion 11 in the obtained resist pattern, that is, the portion where the resist film is removed is slightly deviated from the predetermined position, the second polycrystalline silicon formed later is formed. It is possible to prevent a situation in which the first polycrystalline silicon layer 9 and the n ⁺ diffusion layer 12 to be brought into contact with the layer are not protruded from the direct contact portion 11 and are not in contact with the second polycrystalline silicon layer.

Next, referring to FIGS. 2C and 2D, the oxide film 19 is etched with a mixed gas of CHF ₃ and oxygen using the patterned resist film 24 as a mask. The silicon layer is etched with a high selectivity to the oxide film. As a result, after the interlayer oxide film 19 of the direct contact portion 11 is removed, the first polycrystalline silicon layer is removed, and the side spacer 10 formed of an oxide film having a large selection ratio to the polycrystalline silicon layer is formed. Remain. As a result, only the portion 9a of the first polycrystalline silicon layer 9 corresponding to the direct contact portion 11 is removed. At this time, the n ⁺ diffusion layer region 12 in which the side spacers 10 are not formed is made of silicon and has a low selectivity with respect to polycrystalline silicon, and therefore is exposed to the etching gas and is abraded. As a result, a deletion area 22 is formed.

Next, referring to FIG. 2 (e), the side spacers 10 remaining in the direct contact are removed by using a mixed gas of CHF ₃ and oxygen. As a result, only the portion 10a of the side spacer 10 corresponding to the direct contact portion 11 is removed. Then, using the interlayer oxide film 19 as a mask, phosphorus or arsenic is ion-implanted into the substrate 15 from the direct contact portion to form the n ⁺⁺ region 21. Next, high temperature heat treatment activates the impurity ions implanted in the n ⁺⁺ region 21. As a result, the direct contact part 11
The n-type diffusion layer region is expanded over the entire surface of the substrate 15 inside. Note that this also has the effect of avoiding the occurrence of problems due to the deleted area 22. That is, when the second polycrystalline silicon layer 13 is formed without reforming the n-type diffusion layer as described above, the substrate 15 and the second polycrystalline silicon layer 13 are brought into direct contact with each other in the deleted region 22 and bonded. A leak occurs.

Next, referring to FIG. 2 (f), a second polycrystalline silicon layer 13 is formed by depositing on the polycrystalline silicon interlayer oxide film 19 containing a high concentration of phosphorus and on the direct contact portion 11. As a result, the first and second polycrystalline silicon layers 9 and 13 are connected to the n ⁺⁺ diffusion layer region 21 at the direct contact portion 11.

Finally, a PSG film 20 as a protective film is formed on the entire surface of the substrate 15 including the second polycrystalline silicon layer 13 to obtain the sectional shape shown in FIG. 1 (b).

FIG. 3 is a diagram showing another embodiment of the present invention.

Similar to FIG. 1 (b), FIG. 3 (a) is a sectional view of the portion shown in FIG. 1 (a). Referring to the figure, the direct contact portion 11 in this embodiment is different from the previous embodiment in that phosphorus-doped polycrystalline silicon is provided between the second polycrystalline silicon layer 13 and the n ⁺⁺ diffusion layer region 21. It has a layer 23.
Polycrystalline silicon doped with phosphorus has a smaller resistance value than polycrystalline silicon containing no impurities. Therefore,
By providing the phosphorus-doped polycrystalline silicon layer 23,
The contact resistance between the second polycrystalline silicon layer 13 and the n ⁺⁺ diffusion layer region 21 can be reduced. Further, since the step difference between the direct contact portion 11 and the interlayer oxide film 19 becomes small, the thickness thereof tends to be uniform when the second polycrystalline silicon layer 13 is formed.

FIG. 3B is a sectional view showing a state in which the above direct contact is being formed. Next, the step of forming the direct contact as described above will be briefly described with reference to FIG. First, the n ⁺⁺ diffusion layer region 21 is formed on the substrate 15 by the same process as in the previous embodiment (see FIG. 2 (e)). Next, unlike the previous embodiment, as shown in FIG. 3B, phosphorus-doped polycrystalline silicon is formed on the interlayer oxide film 19 and the n ⁺ diffusion layer region 21. After that, this is etched back to leave only the direct contact portion 11 to form a phosphorus-doped polycrystalline silicon layer 23. After that, as in the first embodiment, the second
The polycrystalline silicon layer 13 and the PSG film 20 of
The cross-sectional shape shown in FIG.

In this embodiment, the conductive layer provided between the n ⁺⁺ diffusion layer region and the second polycrystalline silicon layer is formed of phosphorus-doped polycrystalline silicon, but other conductive materials may be used.
For example, after forming the n ⁺⁺ diffusion layer, the high-concentration silicon layer may be formed only in the direct contact portion by selective epitaxial growth, and this may be used as the conductive layer.

Similarly, after forming the n ⁺⁺ diffusion layer region, a tungsten layer is formed only on the direct contact portion 11 by CVD using a WF ₆ gas capable of precipitating tungsten only on silicon. You may use as.

In all of the above-described embodiments, the gate electrode of the transistor is formed of a single layer of polycrystalline silicon, but in order to reduce the gate resistance, it is formed of two layers of a polycrystalline silicon layer and a refractory metal layer such as tungsten silicide. To form. It may have a polycide structure. Of course, also in this case, the structure of the direct contact can be the same as that of the above embodiment. Although the above-mentioned embodiment uses a P-type substrate, it goes without saying that a P-well may be used and the same effect as that of the above-described embodiment can be obtained when an N-type substrate or N-well is used.

[Effects of the Invention] Since the method for manufacturing a semiconductor device including the direct contact region according to the present invention is configured by the above steps, the following effects are brought about.

That is, the contact resistance in the direct contact becomes small, and the electrical connection between the layers to be connected can be ensured. Further, since the area of the direct contact does not increase in the manufacturing process, it becomes possible to obtain a semiconductor integrated device that can sufficiently cope with miniaturization.

[Brief description of drawings]

1 and 2 are partial plan views and partial cross-sectional views of a semiconductor device showing one embodiment of the present invention, and FIG. 3 is a partial cross-sectional view of a semiconductor device showing another embodiment of the present invention, FIG. Is SRAM
5 is a circuit diagram showing an equivalent circuit of the memory cell of FIG. 5, FIG. 5 is a plan view showing a layout when the circuit shown in FIG. 4 is formed on a semiconductor substrate, and FIG. 6 corresponds to a part of FIG. FIG. In the figure, 9 is a first polycrystalline silicon layer, 10 is a side spacer, 11 is a direct contact, 12 is an n ⁺ diffusion layer region, 13 is a second polycrystalline silicon layer, 14 is a field oxide film, and 15 is P. Mold substrate, 16 gate oxide film, 17 n ^- diffusion layer region, 19 interlayer oxide film, 21 n ⁺⁺ diffusion layer, 22 removal region, 2
3 is a phosphorus-doped polycrystalline silicon layer. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor device, wherein direct contact is made between a gate electrode of a first field effect transistor and one source / drain region of a second field effect transistor by a second conductive layer, The first element formation region having the first field effect transistor formed therein and the second element formation region having the second field effect transistor formed therein are formed on the surface of the semiconductor substrate. And a step of forming a separation layer between the first element formation region and the second element formation region, and a gate electrode of the first field effect transistor provided on the first element formation region via a gate insulating film, A first conductive layer is formed that extends from the gate electrode onto the separation layer and the second element formation region and has an end portion provided on the second element formation region with an insulating film interposed therebetween. And forming a low impurity diffusion region of a pair of source / drain regions of the first field effect transistor in the first element formation region using the gate electrode portion of the first conductive layer as a part of a mask. Forming a low impurity diffusion region of one of the source / drain regions of the second field effect transistor by using an end of the first conductive layer as a part of a mask; and a gate of the first conductive layer. A step of forming a side spacer on a side wall of the electrode portion and a side wall of an end portion; and a step of forming the side spacer formed on the side wall of the gate electrode portion and the gate electrode portion of the first conductive layer as a part of the mask. A high impurity diffusion region of a pair of source / drain regions of the first field effect transistor is formed in the element forming region, and is formed on an end portion of the first conductive layer and a side wall of the end portion. Forming a high impurity diffusion region of one of the source / drain regions of the second field effect transistor using the side spacer as a part of a mask.
A step of forming an interlayer insulating film on the surface of the semiconductor substrate including the first conductive layer; and the interlayer insulating film, which is to be a region to be directly contacted by the second conductive layer, the first conductive layer. And removing the side spacers formed on the end of the conductive layer and the side wall of the end to form an exposed surface in one of the source / drain regions of the first conductive layer and the second field effect transistor. And activating one of the source / drain regions of the second field effect transistor so that one of the source / drain regions of the second field effect transistor is exposed to the exposed surface of the first conductive layer. Diffusing to the vicinity, and forming the second conductive layer that directly connects the exposed surface of one source / drain region of the second field effect transistor and the exposed surface of the first conductive layer. The method of manufacturing a semiconductor device including a.