JP3363750B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to an SRAM (Static Random).
The present invention relates to a technique effectively applied to a semiconductor integrated circuit device having an access memory).

[0002]

2. Description of the Related Art An SRAM as a semiconductor memory device has a flip-flop circuit and two transfer MISFETs (Metal Insulators) at the intersection of a word line and one complementary data line.
latorSemiconductor Field Effect Transistor).

The flip-flop circuit of the SRAM memory cell is configured as an information storage unit and stores 1-bit information. The flip-flop circuit of this memory cell is
As an example, a pair of CMOS (Complementary Metal Oxid)
e Semiconductor) Inverter. CMOS
Each of the inverters is an n-channel drive MIS
It is composed of an FET and a p-channel type load MISFET. The transfer MISFET is of n-channel type. That is, this memory cell has six MISFs.
So-called full CMOS (Full Complem) using ET
entary Metal Oxide Semiconductor) type.

Regarding the complete CMOS type SRAM, JP-A-6-302786 and JP-A-7-992.
55, JP-A-8-17944, etc.

A pair of Cs forming a flip-flop circuit
Mutual input / output terminals of the MOS inverter are cross-coupled via a pair of wirings (hereinafter, referred to as local wirings). The source region of one transfer MISFET is connected to the input / output terminal of one CMOS inverter, and the other CMO is connected.
The other transfer MISF is connected to the input / output terminal of the S inverter.
The source region of ET is connected. One transfer MISF
One of the complementary data lines is connected to the drain region of ET, and the other of the complementary data lines is connected to the drain region of the other transfer MISFET. A pair of transfer MISF
A word line is connected to each gate electrode of ET,
The word line controls conduction and non-conduction of the transfer MISFET.

FIG. 10 shows a conventional complete CMOS type SRAM.
3 shows a pattern layout of the memory cell. As shown, a driving MIS that constitutes one of the CMOS inverters.
The gate electrode FG ₁ common to the FET Qd ₁ and the load MISFET Qp ₁ has the gate electrode FG ₁ and the local wiring L.
A drive electrode MISFETQd is formed which has a lead electrode for connecting with ₂ and constitutes the other CMOS inverter.
₂ and the load MISFET Qp _{2 have} a common gate electrode FG
The _2, lead electrodes for connecting the gate electrode FG ₂ and the local wiring L ₁ is formed.

The extraction electrode of the common gate electrode FG ₁ and the local wiring L _{2 of} the driving MISFET Qd ₁ and the load MISFET Qp ₁ which form one of the CMOS inverters.
Is connected through a contact hole CN _1a , and the local wiring L ₂ is connected to the drain region of the drive MISFET Qd ₂ and the load MI that constitute the other CMOS inverter.
A contact hole C is formed in the drain region of the SFET Qp _2.
N _1b and contact hole CN _1c are connected to each other.

Similarly, the driving MISFET Qd ₂ and the load MISFET Q which form the other CMOS inverter.
The extraction electrode of the common gate electrode FG ₂ of p ₂ and the local wiring L ₁ are connected through a contact hole CN _2a , and the local wiring L ₁ is connected to the drain region and the load of the driving MISFET Qd ₁ forming one CMOS inverter. Is connected to the drain region of the MISFET Qp ₁ for use through a contact hole CN _2b and a contact hole CN _2c , respectively.

By the way, the layout area is reduced to reduce the occupied area of the memory cell of the complete CMOS type SRAM with the increase in capacity of the semiconductor memory device. However, in a highly integrated SRAM of 64 Mbits or more, a layout with dimensions below the processing limit of the photolithography technique is required.

As one of the measures against this, a driving MISFE which constitutes one of the CMOS inverters provided separately is provided.
TQD ₁ common contact hole CN _1a for connecting the lead electrode and the local wiring L ₂ of the gate electrode FG _1, the other of the load MISFET Qp ₂ constituting the CMOS inverter drain region and the local interconnect of the load MISFET Qp ₁ L _The contact hole CN _1c for connecting ₂ and ₂ is used as one contact hole, and similarly, the driving MISFE for forming one separately provided CMOS inverter.
A contact hole CN _2b connecting the drain region of TQd ₁ and the local wiring L ₁ , a driving MISFET Qd ₂ and a load MISFE which form the other CMOS inverter.
A method of reducing the size of the memory cell is being considered by using the contact hole CN _2a connecting the extraction electrode of the common gate electrode FG ₂ of the TQp ₂ and the local wiring L ₁ as one contact hole.

Next, the drain region of the driving MISFET Qd ₁ forming one CMOS inverter and the driving MISFET Qd forming the other CMOS inverter.
₂ and the load MISFET Qp _{2 have} a common gate electrode FG
_A method of forming a contact hole provided in contact with both of the two lead electrodes will be briefly described with reference to FIGS. 11 to 13.

First, as shown in FIG. 11, a field insulating film 1 for element isolation formed of a silicon oxide film on the main surface of a semiconductor substrate 14 made of p-type silicon single crystal.
After forming 5, the gate insulating film 16 is formed on the surface of the semiconductor substrate 14. Next, the driving MISFET Qd ₁ and the load MISFE which form one of the CMOS inverters.
Common gate electrode FG ₁ of TQp ₁ and the other CMO
The common gate electrode FG ₂ of the driving MISFET Qd ₂ and the load MISFET Qp ₂ which form the S inverter is formed. The lead electrode of the gate electrode FG ₂ is provided on the field insulating film 15.

Next, the driving MISFETs Qd ₁ and Qd ₂
Source region, a low-concentration n ⁻ type semiconductor region 17 forming a part of the drain region, and, although not shown, a low-concentration n ⁻ type semiconductor region 17 forming a part of the source region and the drain region of the load MISFETs Qp ₁ and Qp ₂ . A p ⁻ type semiconductor region is formed.

Next, the CVD (Chem
The silicon oxide film deposited by the ical vapor deposition method is entirely etched by anisotropic etching by the RIE (Reactive Ion Etching) method to leave the silicon oxide film on the sidewalls of the gate electrodes FG ₁ and FG ₂ . This silicon oxide film serves as the sidewall spacer 18 for forming the offset region.

Next, the driving MISFETs Qd ₁ and Qd ₂
Of the high-concentration n ⁺ type semiconductor region 19 which constitutes the other part of the source region and the drain region, and the source region and the other part of the drain region of the load MISFETs Qp ₁ and Qp _{2 which} are not shown. A high-concentration p ⁺ type semiconductor region is formed.

Next, an interlayer insulating film 21 composed of a silicon nitride film 20 and a silicon oxide film is sequentially formed on the semiconductor substrate 14. The silicon nitride film 20 is provided as an etching stopper for the interlayer insulating film 21, and has a thickness that does not penetrate when the interlayer insulating film 21 is etched.

Next, as shown in FIG. 12, using the patterned photoresist 22 as a mask, the interlayer insulating film 2 is formed.
1 is etched, and then, as shown in FIG. 13, the silicon nitride film 20 is etched. As a result, the driving MISFET Q that constitutes one of the CMOS inverters
The drain region of d ₁ and the driving MISFET Qd ₂ and the load MISFET which form the other CMOS inverter
A contact hole C _1a is formed in contact with both the common gate electrode FG ₂ of Qp ₂ and the extraction electrode.

Thereafter, although not shown, the semiconductor substrate 14
The wiring material deposited above is processed to form metal wiring.

[0019]

However, the driving MISFET Qd which constitutes one of the CMOS inverters.
The drain region of ₁ and the drive MISFET Qd ₂ and the load MISFET Q that form the other CMOS inverter
In forming the contact hole C _1a in contact with both the common gate electrode FG ₂ of p ₂ and the extraction electrode, the present inventor has found the following problems.

That is, in the region where the silicon nitride film 20 is directly deposited on the surface of the field insulating film 15 for element isolation, the etching selection ratio of the silicon nitride film 20 to the silicon oxide film forming the field insulating film 15 is small. When forming the contact hole C _1a , the silicon oxide film forming the field insulating film 15 is over-etched.

The field insulating film 1 is formed at the end of the element isolation region.
When the silicon oxide film forming 5 is cut by the above-described over-etching, the drain region (n of the driving MISFET Qd ₂ forming one CMOS inverter is formed.
Semiconductor substrate 1 in which ⁺ type semiconductor region 19) is not formed
The contact hole C _1a reaches 4 and the metal wiring is connected to the drain region (n ⁺ type semiconductor region 19) of the driving MISFET Qd ₂ and the p type semiconductor substrate 14, and a junction leak occurs at the end of the element isolation region. Occurs.

An object of the present invention is to provide a technique capable of improving the reliability of a semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0024]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, according to the method for manufacturing a semiconductor integrated circuit device of the present invention, the source region or the drain region of the first MISFET and the second M region adjacent to the first MISFET are formed.
When forming a contact hole in contact with both gate electrodes provided on a field insulating film for element isolation of an ISFET, first, a field insulating film made of a silicon oxide film was formed on the main surface of a semiconductor substrate. After the first
The gate insulating films of the MISFET and the second MISFET are formed, and then the gate electrodes of the first MISFET and the second MISFET are formed. Then the first M
After forming a semiconductor region having a low impurity concentration which constitutes a part of the source region and the drain region of the ISFET and the second MISFET, the first MISFET and the second MIS are formed.
First sidewall formed of a silicon oxide film on the side wall of the FET
Side wall spacers are formed, and then the first M
A semiconductor region having a high impurity concentration that forms another part of the source region and the drain region of the ISFET and the second MISFET is formed. Next, after an interlayer insulating film composed of a silicon nitride film and a silicon oxide film is sequentially formed on the semiconductor substrate, the interlayer insulating film is etched to form a source region or a drain region of the first MISFET and a first MISFET. A part of the contact hole is formed on the gate electrode of the second MISFET, and then the first MISFET is formed.
And a second sidewall spacer made of a silicon nitride film is further formed on the sidewall of the first sidewall spacer provided on the sidewall of the second MISFET to form a source region or a drain of the first MISFET. The other part of the contact hole that contacts both the region and the gate electrode of the second MISFET is formed.

According to the above means, the first MISFE
Source region or drain region of T and second MISF
When forming a contact hole in contact with both the gate electrode of ET and the gate electrode of ET, a second sidewall spacer made of a silicon nitride film is formed on the sidewall of the gate electrode of the second MISFET, and the second sidewall spacer under the second MISFET is formed. Since the field insulating film is prevented from being exposed to the etching plasma, the silicon oxide film forming the field insulating film is not etched.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

FIG. 1 is an equivalent circuit diagram of the SRAM memory cell of the present embodiment. As shown in the figure, the memory cell of the SRAM of this embodiment has a pair of driving MISFETs Qd ₁ arranged at the intersection of a pair of complementary data lines (data line DL, data line bar DL) and a word line WL. , Qd
₂ , a pair of load MISFETs Qp ₁ and Qp ₂ and a pair of transfer MISFETs Qt ₁ and Qt ₂ . Driving MISFETs Qd ₁ and Qd ₂ and transfer Q
t ₁ and Qt ₂ are composed of an n-channel type and have a load MIS.
FETs Qp ₁ and Qp ₂ are of p-channel type. That is, this memory cell is a complete CMOS type using four n-channel type MISFETs and two p-channel type MISFETs.

Six MISFs constituting the above memory cell
Of ET, drive MISFET Qd ₁ and load MIS
The FET Qp ₁ constitutes a CMOS inverter (INV ₁ ), and the driving MISFET Qd ₂ and the load MISFET
Qp ₂ constitutes a CMOS inverter (INV ₂ ). This pair of CMOS inverters (INV ₁ , IN
V ₂ ) between the mutual input / output terminals (storage nodes A and B)
Cross-coupling is performed through a pair of local wirings L ₁ and L ₂ to form a flip-flop circuit as an information storage unit that stores 1-bit information.

One of the input / output terminals (storage node A) of the flip-flop circuit is connected to the source region of the transfer MISFET Qt ₁ , and the other input / output terminal (storage node B) is connected to the source region of the transfer MISFET Qt _2. Has been done. The drain region of the transfer MISFET Qt ₁ is connected to the data line DL, and the drain region of the transfer MISFET Qt ₂ is connected to the data line bar DL.

Further, one end of the flip-flop circuit (the source region of each of the load MISFETs Qp ₁ and Qp ₂ ) is connected to the power supply voltage (V _cc ) and the other end (driving _MIS FET).
Source regions of the SFETs Qd ₁ and Qd ₂ ) are connected to the reference voltage (V _ss ). Power supply voltage ( _Vcc )
Is, for example, 5 V, and the reference voltage (V _ss ) is 0, for example.
V (GND voltage).

The operation of the above circuit will be described. One CM
When the storage node A of the OS inverter (INV ₁ ) is at high potential (“H”), the driving MISFET Qd ₂
Is turned on, the other CMOS inverter (INV
The storage node B of ₂ ) becomes low potential ("L"). Therefore, the driving MISFET Qd ₁ is turned off, and the high potential (“H”) of the storage node A is held. That is, a latch circuit in which a pair of CMOS inverters (INV ₁ and INV ₂ ) are cross-coupled to each other causes mutual storage nodes A and B.
The state is held, and information is held while the power supply voltage is applied.

[0034] Each of the gate electrodes of the transfer MISFET Qt _1, Qt ₂ is the word line WL is connected, transfer MISFET Qt ₁ by the word line WL, Qt ₂
The conduction and non-conduction of are controlled. That is, the word line WL
Is high potential (“H”), transfer MISFET
Since Qt ₁ and Qt ₂ are turned on and the latch circuit and the complementary data line (data line DL, bar DL) are electrically connected, the potential state (“H” or “H” of storage nodes A and B).
L ″) appears on the data lines DL and DL and is read as information of the memory cell.

In order to write information in the memory cell, the word line WL is set to the "H" potential level and the transfer MISFET Qt.
₁ and Qt ₂ are turned on to transmit the information of the data line DL and the bar DL to the storage nodes A and B. Further, in order to read the information of the memory cell, the information of the storage nodes A and B in which the word line WL is at the “H” potential level and the transfer MISFETs Qt ₁ and Qt ₂ are in the ON state is transmitted to the data line DL and bar DL. To do.

Next, a specific structure of the memory cell will be described with reference to plan views of a semiconductor substrate showing approximately one memory cell shown in FIGS.

As shown in FIG. 2, the six MISFETs constituting the memory cell are formed in the active region surrounded by the field insulating film 2 provided on the main surface of the p ⁻ type semiconductor substrate 1. ing. Driving MISFETs Qd ₁ and Qd ₂ and n-channel type transfer MISFETs
Each of Qt ₁ and Qt ₂ is formed in the active region of the p-type well 3 and is a p-channel type load MISF.
ETQp ₁ and Qp ₂ are formed in the active region of the n-type well 4.

The transfer MISFETs Qt ₁ and Qt ₂ have a gate electrode FG ₃ integrally formed with the word line WL. The gate electrode FG ₃ (word line WL) is composed of, for example, a polycide film in which a polycrystalline silicon film and a refractory metal silicide film are laminated, and is formed on a gate insulating film composed of a silicon oxide film. .

The source region and drain region of each of the transfer MISFETs Qt ₁ and Qt ₂ are p-type wells 3.
And an n ⁺ type semiconductor region having a high impurity concentration and an n ⁻ type semiconductor region having a low impurity concentration formed in the active region. That is, the source region and the drain region of each of the transfer MISFETs Qt ₁ and Qt ₂ have an LDD structure.

The driving MISFET Qd ₁ and the load MISFET Qp ₁ which compose one CMOS inverter of the flip-flop circuit have a common gate electrode FG ₁ , and the driving M which composes the other CMOS inverter.
The ISFET Qd ₂ and the load MISFET Qp ₂ have a common gate electrode FG ₂ .

These gate electrodes FG ₁ and FG ₂ are the gate electrodes FG _{3 of the} transfer MISFETs Qt ₁ and Qt _2.
It is composed of the same polycide film as the (word line WL) and is formed on the gate insulating film. The gate electrode FG
₁ , FG ₂ and the gate electrode FG ₃ (word line WL) in the polycrystal silicon film below the polycide film,
An n-type impurity (for example, phosphorus) is introduced.

The source region and drain region of each of the driving MISFETs Qd ₁ and Qd ₂ are a low impurity concentration n ⁻ type semiconductor region and a high impurity concentration n ⁺ type semiconductor region formed in the active region of the p type well 3. It is composed of. That is, the source region and the drain region of each of the driving MISFETs Qd ₁ and Qd ₂ have an LDD structure.

In addition, the load MISFETs Qp ₁ and Qp ₂
Each of the source region and the drain region is composed of a low impurity concentration p ⁻ type semiconductor region and a high impurity concentration p ⁺ type semiconductor region formed in the active region of the n type well 4. That is, the load MISFETs Qp ₁ and Qp ₂
Each of the source region and the drain region has a LDD structure.

Drive MISFET Qd ₁ and load MIS
The common gate electrode FG ₁ of the FET Qp _{1 has} a lead electrode for connecting the gate electrode FG ₁ and the local wiring L ₂ formed by the first-layer metal wiring M ₁ and is for driving. MISFET Qd ₂ and load MISF
The common gate electrode FG ₂ of the ETQp _{2 has} a lead electrode for connecting the gate electrode FG ₂ and the local wiring L ₁ formed by the first-layer metal wiring M ₁ .

Driving MISFET Qd ₁ and load MIS
Common gate electrode FG ₁ of the FET Qp ₁ and driving MIS
FETQd ₂ and the common gate electrode FG ₂ and for the transfer of the load MISFETQp ₂ MISFETQt _1, Qt ₂
A silicon nitride film and a first interlayer insulating film are formed in the upper layer of the gate electrode FG ₃ (word line WL).

As shown in FIG. 3, a first-layer metal wiring M ₁ is formed on the first-layer interlayer insulating film, and the local wiring L is formed by the first-layer metal wiring M ₁ . ₁ ,
L ₂ is constructed. The first interlayer insulating film is, for example, a silicon oxide film and BPSG (Boron-doped Phospo Sil).
The metal wiring M ₁ of the first layer is formed of, for example, a tungsten (W) film.

The local wiring L ₁ is driven by the driving MIS through a contact hole C _1a formed in the first interlayer insulating film.
Common extraction electrode of the gate electrode FG ₂ of the FET Qd ₂ and the load MISFET Qp ₂ and the driving MISFET
Contact hole C connected to the drain region of Qd ₁
It is connected to the drain region of the load MISFET Qp ₁ through _1b .

Similarly, the local wiring L ₂ is connected to the lead electrode of the common gate electrode FG ₁ of the drive MISFET Qd ₁ and the load MISFET Qp ₁ through the contact hole C _2a formed in the first-layer interlayer insulating film. MI for load
It is connected to the drain region of the SFET Qp ₂ and connected to the drain region of the driving MISFET Qd ₂ through the contact hole Cab.

Therefore, the driving M is formed by the first-layer metal wiring M ₁ formed on the first-layer interlayer insulating film.
Drain region of ISFET Qd ₁ , MISFET for load
The drain region of Qp ₁ , the common gate electrode FG _{2 of} the driving MISFET Qd ₂ and the load MISFET Qp ₂ , and the source region of the transfer MISFET Qt ₁ are electrically connected.

Similarly, by the first-layer metal wiring M ₁ , the drain region of the driving MISFET Qd ₂ , the drain region of the load MISFET Qp ₂ and the driving MISFE are formed.
The common gate electrode FG _{1 of} TQd ₁ and the load MISFET Qp ₁ and the source region of the transfer MISFET Qt ₂ are electrically connected.

Further, through the contact hole C ₃ formed in the first-layer interlayer insulating film, the first-layer metal wiring M ₁ has the source regions of the driving MISFETs Qd ₁ and Qd ₂ and the load MISFET Qp. ₁ , Qp ₂ source regions and transfer MISFETs Qt ₁ ,
It is connected to each drain region of Qt ₂ .

As shown in FIG. 4, a second-layer metal wiring M ₂ is formed on the first-layer metal wiring M ₁ via a second-layer interlayer insulating film. . The interlayer insulation of the second layer is made of, for example, a laminated film of a silicon oxide film and a BPSG film, and the metal wiring M ₂ of the second layer is made of, for example, a W film.

The metal wiring M ₂ of the second layer is formed on the drain regions of the transfer MISFETs Qt ₁ and Qt ₂ through the first through hole T _1a formed in the interlayer insulating film of the second layer. Arranged first layer metal wiring M ₁
It is connected to the.

Further, the second-layer metal wiring M ₂ constitutes a reference voltage line (VSS), and is driven through the first through hole T _1b formed in the second-layer interlayer insulating film. Are connected to the first-layer metal wiring M ₁ arranged on the source regions of the respective MISFETs Qd ₁ and Qd ₂ . Further, the second-layer metal wiring M ₂ constitutes a power supply voltage line (V _cc ), and the load MIS is formed through the first through hole T _1c formed in the second-layer interlayer insulating film.
The FETs Qp ₁ and Qp ₂ are connected to the first-layer metal wiring M ₁ arranged on the respective source regions.

_On the upper layer of the second-layer metal wiring M _2, a third-layer metal wiring M ₃ is formed via a third-layer interlayer insulating film. The third-layer interlayer insulating film is composed of, for example, a laminated film of a silicon oxide film, SOG (Spin On Glass) and a silicon oxide film, and the third-layer metal wiring M ₃ is composed of, for example, an aluminum alloy film. ing.

The metal wiring M ₃ of the third layer constitutes data lines DL and bars DL.
The bar DL is provided with transfer MISFETs Qt ₁ , through the second through holes T ₂ formed in the third interlayer insulating film.
It is connected to the second-layer metal wiring M ₂ arranged on each drain region of Qt ₂ .

Next, a method of manufacturing the memory cell of the present embodiment configured as described above will be described with reference to FIGS. In the drawing, the drain region of the driving MISFET Qd _{1 along} the line AA ′ in FIGS. 2 to 4 and the driving MI.
A sectional view of the essential part of the semiconductor substrate showing the manufacturing method of the contact hole C _1a provided in contact with both the lead electrode of the common gate electrode FG ₂ of the SFET Qd ₂ and the load MISFET Qp ₂ is shown. The process up to forming the wiring is shown in the figure.

First, as shown in FIG. 5, a p-type epitaxial silicon layer 5 is grown on a semiconductor substrate 1 made of p ^-- type single crystal silicon, and then an element isolation region on the main surface of the semiconductor substrate 1 is grown. Then, a field insulating film 2 made of a silicon oxide film is formed. Then, in a well-known manner,
A p-type well 3 and an n-type well (not shown) are formed in the semiconductor substrate 1. Next, a gate insulating film 6 made of a thin silicon oxide film is formed on the main surfaces of the p-type well 3 and the n-type well surrounded by the field insulating film 2.

Next, the driving MISFET Qd ₁ and the common gate electrode FG ₁ of the load MISFET Qp _1, the common gate electrode FG ₂ and the transfer MISFET Qt ₁ of the drive MISFET Qd ₂ and load MISFET Qp _2,
A gate electrode FG ₃ (word line WL) of Qt ₂ is formed.

For the gate electrodes FG ₁ and FG ₂ and the gate electrode FG ₃ (word line WL), a polycrystalline silicon film and a tungsten silicide (WSi ₂ ) film in which phosphorus is introduced by the CVD method are formed on the entire surface of the semiconductor substrate 1. After the sequential deposition, the polycrystalline silicon film and the WSi ₂ film are sequentially processed by dry etching using a photoresist pattern (resist pattern) as a mask.

Next, as shown in FIG. 6, n-type impurities (for example, phosphorus (P) and arsenic (As)) are added to the p-type well 3 by ion implantation using the resist pattern as a mask, and p-type is added to the n-type well. Type impurities (for example, boron fluoride (B
F ₂ )) is introduced. After that, C is formed on the entire surface of the semiconductor substrate 1.
A silicon oxide film deposited by the VD (Chemical Vapor Deposition) method is patterned by RIE to form a common gate electrode FG _{1 for} the driving MISFET Qd ₁ and the load MISFET Qp _{1, and} a common gate electrode for the driving MISFET Qd ₂ and the load MISFET Qp _2. The electrode FG ₂ and the gate electrode FG _{3 of the} transfer MISFETs Qt ₁ and Qt _2.
First sidewall spacers 7 are formed on the respective sidewalls of the (word line WL). Next, an n-type impurity (for example, P, As) is introduced into the p-type well 3 and a p-type impurity (for example, BF ₂ ) is introduced into the n-type well by ion implantation using the resist pattern as a mask.

Next, the n-type impurities and the p-type impurities are thermally diffused, and a driving MISFET is formed on the main surface of the p-type well 3.
Qd ₁ and Qd ₂ and transfer MISFETs Qt ₁ and Qt
₂ of the source and drain regions (n ⁻ type semiconductor region 8 and n ⁺ type semiconductor region 9) are formed, and the source and drain regions of the load MISFETs Qp ₁ and Qp ₂ are formed on the main surface of the n type well. (Not shown).

Next, as shown in FIG. 7, a silicon nitride film 10 and a first interlayer insulating film 11 are sequentially formed on the entire surface of the semiconductor substrate 1. The first interlayer insulating film 11 is
For example, it is composed of a laminated film of a silicon oxide film and a BPSG film. The thickness of the silicon nitride film 10 is determined by the distance L between the end of the first sidewall spacer 7 and the end of the field insulating film 2. For example, the distance L is about 0.2 μm.
In this case, the thickness deposited on the sidewalls of the gate electrodes FG ₁ and FG ₂ is 200 nm or more so that the distance L can be covered.

Then, as shown in FIG. 8, the first interlayer insulating film 11 and the silicon nitride film 10 are sequentially etched using the resist pattern 12 formed on the first interlayer insulating film 11 as a mask. To do.

First, the first interlayer insulating film 11 is selectively etched with respect to the silicon nitride film 10, and then,
For example, by performing anisotropic etching using a CHF ₃ + O ₂ gas system with a narrow electrode RIE etching apparatus, the _first electrodes provided on the sidewalls of the gate electrodes FG ₁ and FG ₂ and the gate electrode FG ₃ (word line WL) are formed. Second sidewall spacers 13 formed by the silicon nitride film 10 are further formed on the sidewalls of the sidewall spacers 7. At this time, the thickness of the silicon nitride film 10 is about 200 n.
If m, the sidewall length of the second sidewall spacer 13 is about 0.2 μm which is the distance L between the end of the first sidewall spacer 7 and the end of the field insulating film 2.
Is almost the same as. Therefore, the silicon oxide film forming the field insulating film 2 is not exposed to etching plasma, and the silicon oxide film forming the field insulating film 2 is not etched.

By the above etching, the driving MISF is formed.
The drain region of ETQd ₁ and the driving MISFET Qd
₂ and the load MISFET Qp _{2 have} a common gate electrode FG
Contact holes C _1a in contact with both the _second lead electrode
And a contact hole C _1b in contact with the drain region of the load MISFET Qp ₁ is formed.

Similarly, a contact hole C _2a is formed so as to be in contact with both the lead electrode of the common gate electrode FG ₁ of the driving MISFET Qd ₁ and the load MISFET Qp ₁ and the drain region of the load MISFET Qp ₂ . A contact hole C _2b is formed in contact with the drain region of MISFET Qd ₂ .

Further, the driving MISFETs Qd ₁ and Qd
Each source region of ₂ , load MISFETQ
Source areas of p ₁ and Qp ₂ and transfer MI
A contact hole C ₃ is formed in contact with the drain regions of the SFETs Qt ₁ and Qt ₂ .

Next, as shown in FIG. 9, a first layer wiring material (not shown) is deposited on the entire surface of the semiconductor substrate 1. This wiring material is composed of a metal film, for example, a W film. Next, the wiring material is patterned by dry etching using the resist pattern as a mask to form the first-layer metal wiring M ₁ . As a result, the drive MI
Drain region of SFET Qd ₁ and load MISFET
A local wiring L ₁ that connects the drain region of Qp ₁ and the common gate electrode FG _{2 of} the driving MISFET Qd ₂ and the load MISFET Qp ₂ is formed.

Similarly, the drain region of the drive MISFET Qd ₂ , the drain region of the load MISFET Qp ₂ , the drive MISFET Qd ₁ and the load MISFET Q.
The local wiring L connecting to the common gate electrode FG ₁ of p _1
2 is formed.

Further, the driving MISFETs Qd ₁ and Qd
Each source region of ₂ , load MISFETQ
Source areas of p ₁ and Qp ₂ and transfer M
The first-layer metal wiring M ₁ is also formed in the contact hole C ₃ in contact with the drain regions of the ISFETs Qt ₁ and Qt ₂ .

Next, a second layer formed of a laminated film in which a silicon oxide film and a BPSG film are sequentially deposited on the entire surface of the semiconductor substrate 1.
An interlayer insulating film of the layer is deposited.

After that, the first through holes T _1a , T _1b and T _1c are formed in the second interlayer insulating film by dry etching using the resist pattern as a mask. The first through hole T _1a is formed above the drain regions of the transfer MISFETs Qt ₁ and Qt ₂ , and the first through hole T _1b is above the source regions of the driving MISFETs Qd ₁ and Qd _2. The first through hole T _1c formed is formed above the source regions of the load MISFETs Qp ₁ and Qp ₂ .

Next, the second layer wiring material is deposited on the entire surface of the semiconductor substrate 1. This wiring material is composed of a metal film, for example, a W film. Next, this wiring material is patterned by dry etching using a resist pattern as a mask, and a power supply voltage line (V _cc ) and a reference voltage line (VSS)
Forming the second-layer metal wiring M ₂ which forms Further, a first through hole T _1a formed above the drain regions of the transfer MISFETs Qt ₁ and Qt ₂ is formed.
The second-layer metal wiring M ₂ is also formed therein.

Next, a third interlayer insulating film made of a laminated film in which a silicon oxide film, an SOG film and a silicon oxide film are sequentially deposited is deposited on the entire surface of the semiconductor substrate 1.

After that, a second through hole T ₂ is formed in the third interlayer insulating film by dry etching using the resist pattern as a mask. This second through hole T ₂
Are formed above the drain regions of the transfer MISFETs Qt ₁ and Qt ₂ .

Next, a third layer wiring material is deposited on the entire surface of the semiconductor substrate 1. This wiring material is composed of a metal film, for example, an aluminum alloy film. Next, this wiring material is patterned by dry etching using the resist pattern as a mask to form a third-layer metal wiring M ₃ that constitutes the data lines DL and bars DL.

Finally, a final passivation film is deposited on the third-layer metal wiring M ₃ to complete the memory cell of this embodiment.

As described above, according to the present embodiment, the drain region of the driving MISFET Qd ₁ and the driving MIS.
A contact hole C _1a in contact with both the FET Qd ₂ and the lead-out electrode of the common gate electrode FG ₂ of the load MISFET Qp ₂ , and a lead-out electrode of the common gate electrode FG ₁ of the drive MISFET Qd ₁ and the load MISFET Qp ₁ , and a load. For forming a contact hole C _2a in contact with both the drain region of the MISFET Qp ₂ for use
A second sidewall spacer 13 composed of a silicon nitride film 10 is further formed on the sidewall of the first sidewall spacer 7 provided on the sidewalls of the gate electrodes FG ₁ and FG ₂ , and the field insulating film 2 is formed. Since the silicon oxide film forming the field insulating film is not exposed to the etching plasma, the silicon oxide film forming the field insulating film 2 is not etched.

Although the invention made by the present inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the scope of the invention. It goes without saying that it can be changed.

For example, in the above-described embodiment, the case where the method is applied to the SRAM manufacturing method has been described.
It is applicable to any method of manufacturing a semiconductor integrated circuit device having a contact hole in contact with both the source region or drain region of the ISFET and the gate electrode of the second MISFET adjacent to the first MISFET.

[0082]

The effects obtained by the typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, the source region or drain region of the first MISFET and the first MISFE are provided.
When forming a contact hole in contact with both the gate electrode provided on the field insulating film for element isolation of the second MISFET adjacent to T, the field insulating film at the end of the element isolation region is cut away. No MI, so the first MI
It is possible to prevent junction leakage between the source region or drain region of the SFET and the semiconductor substrate, and improve the reliability of the semiconductor integrated circuit device.

[Brief description of drawings]

FIG. 1 is an equivalent circuit of a SRAM memory cell.

FIG. 2 is a main-portion plan view showing the pattern layout of the memory cell of the SRAM according to the embodiment of the present invention;

FIG. 3 is a main part plan view showing the pattern layout of the memory cell of the SRAM according to the embodiment of the present invention.

FIG. 4 is a plan view of a principal portion showing the pattern layout of the memory cell of the SRAM according to the embodiment of the present invention.

FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate showing the method for manufacturing the SRAM memory cell according to the embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a memory cell of SRAM according to an embodiment of the present invention.

FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate showing the method for manufacturing the SRAM memory cell according to the embodiment of the present invention;

FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate showing the method for manufacturing the SRAM memory cell according to the embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate showing the method for manufacturing the SRAM memory cell according to the embodiment of the present invention;

FIG. 10 is a main-portion plan view showing a pattern layout of a memory cell of a conventional SRAM.

FIG. 11 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a conventional SRAM memory cell.

FIG. 12 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a conventional SRAM memory cell.

FIG. 13 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a conventional SRAM memory cell.

[Explanation of symbols]

1 semiconductor substrate 2 field insulating film 3 p-type well 4 n-type well 5 epitaxial layer 6 gate insulating film 7 first sidewall spacer 8 n ⁻ type semiconductor region 9 n ⁺ type semiconductor region 10 silicon nitride film 11 first layer Interlayer insulating film 12 resist pattern 13 second sidewall spacer 14 semiconductor substrate 15 field insulating film 16 gate insulating film 17 n ⁻ type semiconductor substrate 18 sidewall spacer 19 n ⁺ semiconductor region 20 silicon nitride film 21 interlayer insulating film 22 photo Resist mask A Storage node B Storage node C _1a Contact hole C _1b Contact hole C _2a Contact hole C _2b Contact hole C ₃ Contact hole CN _1a Contact hole CN _1b Contact hole CN _1c Contact hole CN _2a Contact hole CN _2b Contact hole CN _2c Contact hole CN ₃ Contact hole DL Data line bar DL Data line FG ₁ Gate electrode FG ₂ Gate electrode FG ₃ Gate electrode INV ₁ CMOS inverter INV ₂ CMOS inverter L Provided at the end of the element isolation region and the sidewall of the MISFET gate electrode Distance from the end of the formed sidewall spacer L ₁ Local wiring L ₂ Local wiring M ₁ First layer metal wiring M ₂ Second layer metal wiring M ₃ Third layer metal wiring Qd ₁ for driving MISFET Qd ₂ driving MISFET Qp ₁ load MISFET Qp ₂ load MISFET Qt ₁ transfer MISFET Qt ₂ transfer MISFET T _1a first through hole T _1b first through hole T _1c first through hole T ₂ second 2 through hole V _cc power supply voltage V _ss reference voltage WL word line

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/8244 H01L 21/3065 H01L 21/8238 H01L 27/092 H01L 27/11

Claims (5)

(57) [Claims] 1. A contact in contact with both a source region or a drain region of a first MISFET and a gate electrode provided on a field insulating film for element isolation of a second MISFET adjacent to the first MISFET. A method of manufacturing a semiconductor integrated circuit device for forming a hole, comprising:
(a). After forming the field insulating film composed of the first insulating film on the main surface of the semiconductor substrate, the first M film is formed.
Forming a gate insulating film for the ISFET and the second MISFET, and then forming gate electrodes for the first MISFET and the second MISFET;
(b). The first MISFET and the second MISF
A step of forming a source region and a drain region of ET,
(c). The first MISFET and the second MISF
A step of forming a first sidewall spacer formed of a second insulating film on the side wall of ET, and (d) a step of sequentially forming a third insulating film and an interlayer insulating film on the semiconductor substrate, (e). The interlayer insulating film is etched to form the source electrode or the drain region of the first MISFET and the gate electrode provided on the field insulating film for element isolation of the second MISFET. Forming a part of the contact hole, and (f). The first
On the sidewalls of the first sidewall spacers provided on the sidewalls of the MISFET and the second MISFET.
Forming a second side wall spacer formed of the insulating film of the first MISFET, and forming the second sidewall spacer on the source or drain region of the first MISFET and the field insulating film for element isolation of the second MISFET. A step of forming another part of the contact hole in contact with the gate electrode, the method for manufacturing a semiconductor integrated circuit device. 2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the first insulating film, the second insulating film and the interlayer insulating film are formed of a silicon oxide film. The method of manufacturing a semiconductor integrated circuit device, wherein the insulating film of is composed of a silicon nitride film. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the field insulating film is formed when the second sidewall spacer is formed.
2. The method for manufacturing a semiconductor integrated circuit device, wherein the insulating film is not exposed to etching plasma. 4. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the first sidewall spacer and the second sidewall spacer are processed by anisotropic etching. Manufacturing method of integrated circuit device. 5. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the drain region or the source region of the first MISFET is a drain region of a driving MISFET which constitutes one CMOS inverter of SRAM or Source region of transfer MISFET or SRA
MIS for load constituting one CMOS inverter of M
The drain region of the FET, and the second MISFET
Has a gate electrode of a driving MISFET and a load MISFET which constitute the other CMOS inverter of the SRAM.
A method for manufacturing a semiconductor integrated circuit device, which is an extraction electrode of a common gate electrode of the above.