JPH06101496B2 - Testing and measuring equipment for semiconductor devices - Google Patents
Testing and measuring equipment for semiconductor devicesInfo
- Publication number
- JPH06101496B2 JPH06101496B2 JP61256189A JP25618986A JPH06101496B2 JP H06101496 B2 JPH06101496 B2 JP H06101496B2 JP 61256189 A JP61256189 A JP 61256189A JP 25618986 A JP25618986 A JP 25618986A JP H06101496 B2 JPH06101496 B2 JP H06101496B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- defective
- semiconductor devices
- measurement
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 83
- 230000002950 deficient Effects 0.000 claims description 44
- 238000005259 measurement Methods 0.000 claims description 36
- 235000012431 wafers Nutrition 0.000 description 24
- 239000000523 sample Substances 0.000 description 8
- 238000003860 storage Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） 本発明は、半導体ウエハ上に複数形成された半導体デバ
イスの試験測定を行なう半導体デバイスの試験測定装置
に関する。Description: [Object of the Invention] (Field of Industrial Application) The present invention relates to a semiconductor device test measurement apparatus for performing test measurement of a plurality of semiconductor devices formed on a semiconductor wafer.
（従来の技術〕 一般に半導体デバイスの試験測定装置は、多数の探針を
配置されたプローブカード等を用い、半導体ウエハ上に
複数形成された半導体デバイス電極パットに探針を接触
させ、半導体デバイスの電気的な試験測定を行なう。(Prior Art) Generally, a semiconductor device test and measurement apparatus uses a probe card or the like in which a large number of probes are arranged, and the probes are brought into contact with a plurality of semiconductor device electrode pads formed on a semiconductor wafer. Perform electrical test measurements.
そして、半導体ウエハ上に形成された半導体デバイスが
良品であるか、不良品であるかを判別し、不良品の半導
体デバイスにインキング等のマーキングを行なう。Then, it is determined whether the semiconductor device formed on the semiconductor wafer is a good product or a defective product, and marking such as inking is performed on the defective semiconductor device.
なお、上述のマーキングは、電気的な試験測定による良
品および不良品の判別結果をメモリ内に記憶しておき、
１枚の半導体ウエハ上に形成された全ての半導体デバイ
スの電気的な試験測定が終了した後、インカー等によっ
てマーキングするよう構成された半導体デバイスの試験
測定装置もある。In addition, the above-mentioned marking is stored in the memory the determination result of good product and defective product by electrical test measurement,
There is also a semiconductor device test and measurement apparatus configured to perform marking with an inker or the like after electrical test and measurement of all semiconductor devices formed on one semiconductor wafer is completed.
（発明が解決しようとする問題点） しかしながら、上記説明の従来の半導体デバイスの試験
測定装置では、例えば、１枚の半導体ウエハ上に形成さ
れた半導体デバイスのほとんどが不良品であるような場
合においても、試験測定が終了した後、これら全ての不
良品の半導体デバイスにマーキングを行なうため、マー
キングに時間を要し、稼働率が悪化するという問題があ
る。また、上述のように、１枚の半導体ウエハ上に形成
された半導体デバイスのほとんどが不良品であるような
場合では、少数の良品の半導体デバイスのために、この
半導体ウエハを試験測定終了後のカッティング工程等に
送ることは、生産効率上好ましくない。(Problems to be Solved by the Invention) However, in the conventional semiconductor device test and measurement apparatus described above, for example, when most of the semiconductor devices formed on one semiconductor wafer are defective products. However, since all of these defective semiconductor devices are marked after the test measurement is completed, there is a problem that the marking takes time and the operation rate deteriorates. Further, as described above, in the case where most of the semiconductor devices formed on one semiconductor wafer are defective products, the semiconductor wafers after the test measurement are completed due to the small number of non-defective semiconductor devices. Sending to a cutting process or the like is not preferable in terms of production efficiency.
本発明は、かかる従来の事情に対処してなされたもの
で、従来に比べて大幅に稼働率の向上を図ることのでき
る半導体デバイスの試験測定装置を提供しようとするも
のである。The present invention has been made in view of such conventional circumstances, and an object of the present invention is to provide a test measuring apparatus for a semiconductor device capable of significantly improving the operation rate as compared with the conventional case.
［発明の構成］ （問題点を解決するための手段） すなわち本発明の半導体デバイスの試験測定装置は、半
導体ウエハ上に複数形成された半導体デバイスの試験測
定を行なう手段と、該手段の測定結果から前記半導体デ
バイスが良品であるか不良品であるかを判別する手段
と、該手段の判別結果から前記半導体デバイスの歩留り
とあらかじめ設定された設定値とを比較する手段と、該
手段の比較結果に応じて不良品の半導体デバイスにマー
キングする手段とを備えたこと特徴とする。[Configuration of Invention] (Means for Solving Problems) That is, the semiconductor device test measurement apparatus of the present invention includes means for performing test measurement of a plurality of semiconductor devices formed on a semiconductor wafer, and measurement results of the means. Means for determining whether the semiconductor device is a good product or a defective product, means for comparing the yield of the semiconductor device with a preset value from the determination result of the means, and a comparison result of the means And a means for marking a defective semiconductor device according to the above.
（作用） 本発明の半導体デバイスの試験測定装置では、半導体ウ
エハ上に複数形成された半導体デバイスの試験測定を行
ない良品および不良品の半導体デバイスを判別し、この
判別結果から半導体デバイスの歩留りとあらかじめ設定
された設定値とを比較し、この比較結果に応じて、例え
ば半導体デバイスの歩留りが、あらかじめ設定された設
定値以上の場合のみ、不良品の半導体デバイスにマーキ
ングする。(Operation) In the semiconductor device test measuring apparatus of the present invention, a plurality of semiconductor devices formed on a semiconductor wafer are tested and measured, and good semiconductor devices and defective semiconductor devices are discriminated. A defective semiconductor device is marked only when the yield of the semiconductor device is equal to or higher than a preset set value, for example, by comparing the set value with the set value.
したがって、例えば、半導体デバイスの歩留りがあらか
じめ設定された設定値以下の場合、すなわち、１枚の半
導体ウエハ上に形成された半導体デバイスの大部分が不
良品で、良品の半導体デバイスが少数しかないような場
合は、マーキングを行なわず、半導体デバイスの試験測
定装置の稼働率の向上を図ることができる。Therefore, for example, when the yield of semiconductor devices is less than or equal to a preset set value, that is, most of the semiconductor devices formed on one semiconductor wafer are defective and only a small number of non-defective semiconductor devices are present. In this case, marking can be omitted and the operating rate of the test and measurement apparatus for semiconductor devices can be improved.
（実施例） 以下本発明の半導体デバイスの試験測定装置を図面を参
照して一実施例について説明する。(Embodiment) An embodiment of the semiconductor device test and measurement apparatus of the present invention will be described below with reference to the drawings.
この実施例の半導体デバイスの試験測定装置は、第１図
に示すように、半導体ウエハ１上の半導体デバイスの電
気的な試験測定およびマーキング等を行なうプローバー
部２と、このプローバー部２に電気的に接続され、試験
測定された半導体デバイスが良品であるか不良品である
かを判別するテスター部３とから構成されている。As shown in FIG. 1, the semiconductor device test and measurement apparatus of this embodiment includes a prober unit 2 for conducting electrical test measurement, marking, and the like of a semiconductor device on a semiconductor wafer 1, and an electrical prober unit 2. And a tester unit 3 that is connected to the semiconductor device and determines whether the semiconductor device tested and measured is a good product or a defective product.
上記プローバー部２は、例えば測定対象の半導体ウエハ
１が配置されるＸ−Ｙテーブル2a、多数の半導体ウエハ
１が収容されたキャリヤ1aから測定対象の半導体ウエハ
１をＸ−Ｙテーブル2a上に配置する搬送部2b、半導体ウ
エハ１上に複数形成された半導体デバイスの電極パット
に接触される多数の探針を配置されたプローブカード2
c、テスター部３の判別結果を記憶する記憶部2d、この
記憶部2dに記憶された判別結果から例えば良品数と予め
設定された設定良品数とを比較して歩留りが設定値以上
であるか判定する比較部2e、比較部2eの比較結果に応じ
て不良品の半導体デバイスにインキング等のマーキング
を行なうマーキング部2fと、比較部2eに設定値を入力す
る入力部2gとから構成されている。The prober unit 2 includes, for example, an XY table 2a on which the semiconductor wafer 1 to be measured is placed, and the semiconductor wafer 1 to be measured is placed on the XY table 2a from the carrier 1a containing a large number of semiconductor wafers 1. A carrier part 2b for carrying out, a probe card 2 in which a large number of probes to be brought into contact with electrode pads of a plurality of semiconductor devices formed on the semiconductor wafer 1 are arranged.
c, a storage unit 2d that stores the determination result of the tester unit 3, and whether the yield is equal to or more than a set value by comparing the number of non-defective products with a preset number of non-defective products from the determination result stored in the storage unit 2d, for example Comparing unit 2e to determine, a marking unit 2f that performs marking such as inking on a defective semiconductor device according to the comparison result of the comparing unit 2e, and an input unit 2g that inputs a set value to the comparing unit 2e. There is.
なお、マーキング部2fは、図示しないインカー等から構
成され、Ｘ−Ｙテーブル2a上あるいは、Ｘ−Ｙテーブル
2a上から他の載置台上に半導体ウエハ１を搬送した後に
マーキングを行なうよう構成されている。The marking portion 2f is composed of an inker (not shown) or the like, and is placed on the XY table 2a or the XY table.
Marking is performed after the semiconductor wafer 1 is transferred from above 2a to another mounting table.
また、上記テスター部３は、プローブカード2cを介して
半導体デバイスに測定信号の供給および読み取りを行な
う測定部3a、測定部3aの測定結果から、試験測定された
半導体デバイスが良品であるか不良品であるかを判別す
る判別部3b等から構成されている。In addition, the tester unit 3 determines whether the semiconductor device tested and measured is a good product or a defective product based on the measurement results of the measurement unit 3a and the measurement unit 3a that supply and read the measurement signal to the semiconductor device via the probe card 2c. It is composed of a discrimination unit 3b for discriminating whether or not
上記構成のこの実施例の半導体デバイスの試験測定装置
は、第２図のフローチャートに示すよう動作する。The semiconductor device test and measurement apparatus of this embodiment having the above-described configuration operates as shown in the flowchart of FIG.
すなわち、搬送部2bによりＸ−Ｙテーブル2a上に半導体
ウエハ１がロードされ、アライメントされる（ａ）。That is, the semiconductor wafer 1 is loaded and aligned on the XY table 2a by the carrying section 2b (a).
次に、Ｘ−Ｙテーブル2a上の所定の位置に配置された半
導体ウエハ１に対して、プローブカード2cの探針が半導
体デバイス上の電極パットと接触状態とされて、テスタ
ー部３の測定部3aおよび判別部3bにより、電気的な試験
測定および良品と不良品の判別が行なわれ、この判別結
果は記憶部2dに記憶される（ｂ）。Next, the probe of the probe card 2c is brought into contact with the electrode pad on the semiconductor device with respect to the semiconductor wafer 1 arranged at a predetermined position on the XY table 2a, and the measuring unit of the tester unit 3 is measured. Electrical test measurement and discrimination between non-defective products and defective products are performed by the 3a and the discrimination unit 3b, and the discrimination result is stored in the storage unit 2d (b).
測定が終了すると（ｃ）、比較部2eにおいて入力部2gか
ら予め入力された設定良品数と、記憶部2dに記憶された
良品数とを比較する（ｄ）。When the measurement is completed (c), the comparison unit 2e compares the preset number of non-defective products input from the input unit 2g with the number of non-defective products stored in the storage unit 2d (d).
そして、測定によって判別された良品数が設定良品数以
上の場合は、マーキング部2fによって、記憶部2d記憶さ
れた不良品の半導体デバイスにマーキングが行なわれる
（ｅ）。When the number of non-defective products determined by measurement is equal to or larger than the set number of non-defective products, the marking unit 2f marks the defective semiconductor device stored in the storage unit 2d (e).
この後、測定結果のプリントが行なわれ（ｆ）、半導体
ウエハ１の通常キャリヤ1aへのアンロードが行なわれる
（ｇ）。Thereafter, the measurement result is printed (f), and the semiconductor wafer 1 is unloaded onto the normal carrier 1a (g).
一方、比較部2eにおいて比較された良品数が設定良品数
以下の場合は、マーキング部2fによるマーキングは行な
われず、不良品と判定した旨のプリントが行なわれ
（ｈ）、この後半導体ウエハ１は図示しない指定キャリ
ヤヘアンロードされる（ｉ）。On the other hand, when the number of non-defective products compared in the comparison unit 2e is less than or equal to the set number of non-defective products, marking is not performed by the marking unit 2f, and printing to the effect that the product is determined to be defective is performed (h). It is unloaded to a designated carrier (not shown) (i).
すなわち、上述のこの実施例の半導体デバイスの試験測
定装置では、比較部2eにおいて入力部2gから予め入力さ
れた設定良品数と、測定によって判別された良品数とを
比較し、この比較の結果良品数が設定良品数以下の場合
は、半導体ウエハ１に対するマーキングを行なわず不良
品と判定して指定キャリヤヘアンロードする。したがっ
て不良品の半導体デバイスが多数存在する半導体ウエハ
１のマーキングに要する時間を省いて、半導体デバイス
の試験測定装置の稼働率の向上を図ることができ、か
つ、測定終了後の工程へ不良品の半導体デバイスが多数
存在する半導体ウエハ１が送られることがなく、生産効
率の向上を図ることができる。That is, in the test measuring apparatus for a semiconductor device of this embodiment described above, the number of non-defective products set in advance in the comparing unit 2e from the input unit 2g is compared with the number of non-defective products determined by measurement, and the result of this comparison If the number is less than the set number of non-defective products, the semiconductor wafer 1 is not marked and it is determined that the product is defective and the semiconductor wafer 1 is unloaded to the designated carrier. Therefore, it is possible to save the time required for marking the semiconductor wafer 1 having a large number of defective semiconductor devices, improve the operation rate of the test measuring apparatus for semiconductor devices, and perform the process after the measurement is completed. The production efficiency can be improved because the semiconductor wafer 1 having a large number of semiconductor devices is not sent.
なお、設定良品数は、原料コスト、測定終了後の工程に
おける加工コスト、生産効率等から算出し、設定する。
また、比較対象は、良品数のように歩留りを示すもので
あれば、例えば不良品数、良品率、不良品率等としても
よいことはもちろんである。The number of non-defective products set is calculated and set from the raw material cost, the processing cost in the process after the measurement, the production efficiency, and the like.
Further, it is needless to say that the comparison target may be, for example, the number of defective products, the ratio of non-defective products, the ratio of defective products, etc. as long as it shows the yield like the number of non-defective products.
また、上述の実施例では、プローバー部２と、テスター
部３とが分離されている例について説明したが、これら
のプローバー部２とテスター部３とは、一体的に構成し
てもよい。Further, in the above-described embodiment, an example in which the prober unit 2 and the tester unit 3 are separated has been described, but the prober unit 2 and the tester unit 3 may be integrally configured.
［発明の効果］ 上述のように、本発明の半導体デバイスの試験測定装置
では、従来に比べて大幅に稼働率の向上を図ることがで
きる。[Effects of the Invention] As described above, in the semiconductor device test and measurement apparatus of the present invention, it is possible to significantly improve the operating rate as compared with the conventional one.
第１図は本発明の一実施例の半導体デバイスの試験測定
装置の構成を示す構成図、第２図は第１図に示す半導体
デバイスの試験測定装置の動作を示すフローチャートで
ある。 １……半導体ウエハ、2d……記憶部、2e……比較部、2f
……マーキング部、3a……測定部、3b……判別部。FIG. 1 is a block diagram showing the configuration of a semiconductor device test and measurement apparatus according to an embodiment of the present invention, and FIG. 2 is a flow chart showing the operation of the semiconductor device test and measurement apparatus shown in FIG. 1 ... Semiconductor wafer, 2d ... Memory section, 2e ... Comparison section, 2f
…… Marking section, 3a …… Measuring section, 3b …… Discrimination section.
Claims (2)
バイスの試験測定を行なう手段と、該手段の測定結果か
ら前記半導体デバイスが良品であるか不良品であるかを
判別する手段と、該手段の判別結果から前記半導体デバ
イスの歩留りとあらかじめ設定された設定値とを比較す
る手段と、該手段の比較結果に応じて不良品の半導体デ
バイスにマーキングする手段とを備えたこと特徴とする
半導体デバイスの試験測定装置。1. A means for performing a test measurement of a plurality of semiconductor devices formed on a semiconductor wafer, a means for determining whether the semiconductor device is a non-defective product or a defective product from the measurement result of the means, and the means. The semiconductor device comprising means for comparing the yield of the semiconductor device with a preset value from the result of the determination, and means for marking defective semiconductor devices according to the comparison result of the means. Test and measurement equipment.
手段は、良品の半導体デバイスの個数が予め設定された
設定値以上の場合のみ不良品の半導体デバイスにマーキ
ングするよう構成された特許請求の範囲第１項記載の半
導体デバイスの試験測定装置。2. The marking means for marking defective semiconductor devices is configured to mark defective semiconductor devices only when the number of non-defective semiconductor devices is equal to or greater than a preset value. Item 1. A semiconductor device test and measurement apparatus according to item 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61256189A JPH06101496B2 (en) | 1986-10-28 | 1986-10-28 | Testing and measuring equipment for semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61256189A JPH06101496B2 (en) | 1986-10-28 | 1986-10-28 | Testing and measuring equipment for semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63110648A JPS63110648A (en) | 1988-05-16 |
| JPH06101496B2 true JPH06101496B2 (en) | 1994-12-12 |
Family
ID=17289143
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61256189A Expired - Lifetime JPH06101496B2 (en) | 1986-10-28 | 1986-10-28 | Testing and measuring equipment for semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06101496B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0602271B1 (en) * | 1992-12-17 | 2004-04-28 | Samsung Electronics Co. Ltd. | Testing and repairing process for memory chips on a wafer, each chip having a redundancy circuit |
-
1986
- 1986-10-28 JP JP61256189A patent/JPH06101496B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63110648A (en) | 1988-05-16 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |