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JPH03185744A - Semiconductor element - Google Patents

Semiconductor element

Info

Publication number
JPH03185744A
JPH03185744A JP1325695A JP32569589A JPH03185744A JP H03185744 A JPH03185744 A JP H03185744A JP 1325695 A JP1325695 A JP 1325695A JP 32569589 A JP32569589 A JP 32569589A JP H03185744 A JPH03185744 A JP H03185744A
Authority
JP
Japan
Prior art keywords
measured
semiconductor elements
defect
contact
fuse terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1325695A
Other languages
Japanese (ja)
Inventor
Takashi Tamura
尚 田村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP1325695A priority Critical patent/JPH03185744A/en
Publication of JPH03185744A publication Critical patent/JPH03185744A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05553Shape in top view being rectangular

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To easily judge a defect when many semiconductor elements are measured simultaneously by a method wherein a fuse terminal is built in each semiconductor element. CONSTITUTION:A fuse terminal 11 is connected to a main functional operation circuit 1 by using a power supply. When many semiconductor elements are measured simultaneously with a semiconductor test apparatus, a needle of a probe card is first brought into contact with individual pads 2 to 10. An electric current in the forward direction is made to flow to a diode 12 attached to each pad and a voltage at this time is measured. Whether the needle of the probe card is normally brought into contact with the individual pads is read out and judged from its measured value. The same operation is executed on many semiconductor elements. When it is normally brought into contact, an electrical test and a functional test are made and it is judged whether they are good products or not. When a defect is found by the tests, a fuse at the fuse terminal is blown to identify the defect. Thereby, many semiconductor elements can simultaneously and easily be measured.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体試験装置により試験を行う半導体素子
に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device tested by a semiconductor testing device.

〔発明の概要〕[Summary of the invention]

この発明は数回に分けて試験することにより、測定時間
短縮のため多数個同時測定を行う半導体素子において、
試験により不良と判定されたにもかかわらず、バンドマ
ークがつけられない場合でも内蔵されたヒユーズ端子の
ヒユーズを切断することにより、不良であることを識別
し多数個同時測定を可能としたものである。
The present invention allows semiconductor devices to be tested simultaneously in large numbers to shorten measurement time by conducting tests in several batches.
Even if a band mark cannot be attached even though the product is determined to be defective through testing, by cutting the fuse of the built-in fuse terminal, it is possible to identify the defect and measure multiple items at the same time. be.

〔従来の技術〕[Conventional technology]

従来、ウェハで半導体素子の測定時間短縮の目的による
多数個同時測定において半導体試験装置からの不良信号
数に合わせて同時測定数を決定する方法で行われていた
Conventionally, when simultaneously measuring a large number of semiconductor devices on a wafer for the purpose of shortening the measurement time, the number of simultaneous measurements has been determined according to the number of defective signals from a semiconductor testing device.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし、従来の技術においては、半導体素子を試験する
にあたり、半導体素子が不良である場合試験装置からの
不良信号をブローバが受は取り、半導体素子にパッドマ
ークをつけることで、前記半導体素子を破壊し不良品と
していた。しかし、試験装置からの不良信号数に制限が
あり、多数個同時測定を行おうとすると、バンドマーク
がつけられないものがでて多数個同時測定数を制限する
という欠点があった。
However, in conventional technology, when testing a semiconductor device, if the semiconductor device is defective, a blower receives a defective signal from the test equipment and marks the semiconductor device with a pad mark, thereby destroying the semiconductor device. It was considered a defective product. However, there is a limit to the number of defective signals from the test equipment, and when trying to measure a large number of signals simultaneously, some signals cannot be marked with a band mark, which limits the number of simultaneous measurements.

〔課題を解決するための手段〕[Means to solve the problem]

上記問題点を解決するために、この発明は半導体素子に
ヒユーズ端子を設けた溝底とし、バッドマークを付けら
れない制約がある場合の多数個同時測定の合否の判定を
可能としたものである。
In order to solve the above-mentioned problems, the present invention provides a groove bottom with a fuse terminal provided in the semiconductor element, thereby making it possible to judge the pass/fail of simultaneous measurement of a large number of semiconductor elements when there is a restriction that it is not possible to attach a bad mark. .

〔作用〕[Effect]

上記のように構成された半導体素子を多数個同時測定し
たとき、試験により不良であった場合、このヒユーズ端
子のヒユーズを切断することで、不良であることを識別
し、多数個同時測定を容易に行えることが出来るのであ
る。
When a large number of semiconductor devices configured as described above are measured simultaneously, if they are found to be defective, cutting the fuse at this fuse terminal will identify the defect and facilitate simultaneous measurement of a large number of devices. It is possible to do this.

〔実施例〕〔Example〕

以下に、この発明の実施例を図面に基づいて説明する。 Embodiments of the present invention will be described below based on the drawings.

第1図において一つの半導体素子の中で、ヒユーズ端子
1.1は本機能動作回路lと電源で接続されている。ま
ず半導体試験装置により多数個同時測定するにあたり、
各バンド2〜10にプローブカードの針を接触させる。
In FIG. 1, a fuse terminal 1.1 in one semiconductor element is connected to the functional operation circuit 1 through a power source. First, when measuring a large number of devices simultaneously using semiconductor test equipment,
Bring the needle of the probe card into contact with each band 2-10.

各バッドに付いているダイオード12に順方向に電流を
流し、その時の電圧を測定する。その測定値から正常に
プローブカードの針が各バッドに接触されているかを読
み取り判定する。これと同しことを半導体素子、多数個
で実施する。正常に接触されていれば電気的機能的試験
を行い、合否判定をする。合否判定により不良である場
合にはヒユーズ端子に電圧もしくは電流を印加し、ヒユ
ーズ13を切断する。切断することにより、プローブカ
ードの針が接触しても電気的につながらないことになる
。その結果、次工程で試験した時にこの半導体素子につ
いては接触不良と判定され、それ以降電気的1機能的試
験は行われない。このようにして半導体素子のヒユーズ
の状態により、バッドマークをつけられない時の多数個
同時測定を可能にしているのである。
A current is passed in the forward direction through the diode 12 attached to each pad, and the voltage at that time is measured. From the measured values, it is determined whether the needles of the probe card are properly touching each pad. The same thing is done with a large number of semiconductor elements. If the contact is normal, an electrical functional test is performed and a pass/fail judgment is made. If the result of the pass/fail determination is that it is defective, a voltage or current is applied to the fuse terminal to disconnect the fuse 13. By cutting it, there will be no electrical connection even if the needle of the probe card comes into contact with it. As a result, when tested in the next step, this semiconductor element is determined to have poor contact, and no electrical and single functional tests are performed thereafter. In this way, it is possible to simultaneously measure a large number of semiconductor devices when bad marks cannot be made depending on the state of the fuses of the semiconductor devices.

〔発明の効果〕〔Effect of the invention〕

この発明は以上説明したように半導体素子にヒユーズ端
子を内蔵したことにより多数個同時測定時の不良判定を
容易にする効果がある。
As explained above, this invention has the effect of making it easier to determine whether a semiconductor device is defective when simultaneously measuring a large number of devices by incorporating a fuse terminal into the semiconductor device.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の実施例である半導体素子である。 本機能動作回路 2〜10・・・バッド 11・・・ヒユーズ端子 12・・・ダイオード 13・・・ヒユーズ FIG. 1 shows a semiconductor device according to an embodiment of the invention. This function operation circuit 2-10...Bad 11...Fuse terminal 12...Diode 13... Fuse

Claims (1)

【特許請求の範囲】[Claims]  半導体試験装置によって多数個同時に半導体素子の電
気的、機能的試験がなされるウェハ上に設けられた半導
体素子において、半導体素子にヒューズ端子を付けたこ
とを特徴とする半導体素子。
1. A semiconductor device provided on a wafer on which a large number of semiconductor devices are electrically and functionally tested simultaneously by a semiconductor testing device, characterized in that the semiconductor device is provided with a fuse terminal.
JP1325695A 1989-12-14 1989-12-14 Semiconductor element Pending JPH03185744A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1325695A JPH03185744A (en) 1989-12-14 1989-12-14 Semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1325695A JPH03185744A (en) 1989-12-14 1989-12-14 Semiconductor element

Publications (1)

Publication Number Publication Date
JPH03185744A true JPH03185744A (en) 1991-08-13

Family

ID=18179682

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1325695A Pending JPH03185744A (en) 1989-12-14 1989-12-14 Semiconductor element

Country Status (1)

Country Link
JP (1) JPH03185744A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997024763A1 (en) * 1995-12-29 1997-07-10 Intel Corporation An integrated circuit package with internally readable permanent identification of device characteristics
US5686759A (en) * 1995-09-29 1997-11-11 Intel Corporation Integrated circuit package with permanent identification of device characteristics and method for adding the same
CN102683326A (en) * 2011-03-16 2012-09-19 三星Led株式会社 Semiconductor light emitting diode chip, method of manufacturing thereof and method for quality control thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5670825A (en) * 1995-09-29 1997-09-23 Intel Corporation Integrated circuit package with internally readable permanent identification of device characteristics
US5686759A (en) * 1995-09-29 1997-11-11 Intel Corporation Integrated circuit package with permanent identification of device characteristics and method for adding the same
WO1997024763A1 (en) * 1995-12-29 1997-07-10 Intel Corporation An integrated circuit package with internally readable permanent identification of device characteristics
CN102683326A (en) * 2011-03-16 2012-09-19 三星Led株式会社 Semiconductor light emitting diode chip, method of manufacturing thereof and method for quality control thereof

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