JPH0575029A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0575029A JPH0575029A JP23423791A JP23423791A JPH0575029A JP H0575029 A JPH0575029 A JP H0575029A JP 23423791 A JP23423791 A JP 23423791A JP 23423791 A JP23423791 A JP 23423791A JP H0575029 A JPH0575029 A JP H0575029A
- Authority
- JP
- Japan
- Prior art keywords
- type region
- region
- type
- zener diode
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特
に、定電圧ダイオードを有する半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a constant voltage diode.
【0002】[0002]
【従来の技術】従来の半導体装置は、図6に示すように
N型シリコン基板1の表面に設けた酸化シリコン膜2を
選択的にエッチングして開孔部を設け、この開孔部の周
囲に選択的にアクセプター不純物を拡散し、P型拡散層
18を形成する。次にP型領域18の内側にP型領域1
8よりアクセプター不純物濃度の高いP+ 型領域19を
形成する。次にP型領域18の外周にN+ 型領域20を
形成後、P+ 型領域19上の酸化シリコン膜を除去し、
開孔部のP+ 型領域19及びP型領域18に接続する電
極7とN型シリコン基板1の裏面に設けた電極8とを形
成し、定電圧ダイオードを構成する。2. Description of the Related Art In a conventional semiconductor device, as shown in FIG. 6, a silicon oxide film 2 provided on the surface of an N-type silicon substrate 1 is selectively etched to form an opening, and the opening is surrounded by the opening. An acceptor impurity is selectively diffused into the P type diffusion layer 18. Next, inside the P-type region 18, the P-type region 1
A P + type region 19 having an acceptor impurity concentration higher than that of No. 8 is formed. Next, after forming the N + type region 20 on the outer periphery of the P type region 18, the silicon oxide film on the P + type region 19 is removed,
An electrode 7 connected to the P + type region 19 and the P type region 18 of the opening and an electrode 8 provided on the back surface of the N type silicon substrate 1 are formed to form a constant voltage diode.
【0003】[0003]
【発明が解決しようとする課題】この従来の半導体装置
は、PN接合のブレークダウン後の低電流域では、接合
内のキャリア密度の局所的ゆらぎによりショット雑音が
発生する。この雑音はブレークダウン電圧が高いほど大
きくなり、ツェナー電圧の高い定電圧ダイオードを回路
に組み込むと、雑音によって誤動作することがあるとい
う問題があった。In this conventional semiconductor device, shot noise is generated in the low current region after breakdown of the PN junction due to local fluctuation of carrier density in the junction. This noise increases as the breakdown voltage increases, and there is a problem that malfunction may occur due to noise when a constant voltage diode having a high Zener voltage is incorporated in the circuit.
【0004】また、ツェナー電圧が高いものほど、半導
体基板の不純物濃度が低いので、動作抵抗が大きくなる
といった特性上の問題点があった。Further, the higher the Zener voltage is, the lower the impurity concentration of the semiconductor substrate is, so that there is a characteristic problem that the operating resistance is increased.
【0005】[0005]
【課題を解決するための手段】本発明の第1の半導体装
置は、一導電型半導体基板の上面に設けた逆導電型のベ
ース領域と、前記ベース領域内に設けた一導電型のコレ
クタ領域及び一導電型のツェナーダイオードと、前記コ
レクタ領域及びツェナーダイオードと接続し且つ誘電体
膜を介して前記ベース領域との間にコンデンサを形成す
る電極とを備えている。A first semiconductor device of the present invention comprises a base region of opposite conductivity type provided on the upper surface of a semiconductor substrate of one conductivity type and a collector region of one conductivity type provided in the base region. And a Zener diode of one conductivity type, and an electrode that is connected to the collector region and the Zener diode and that forms a capacitor between the collector region and the Zener diode and the base region.
【0006】本発明の第2の半導体装置は、一導電型半
導体基板の上面に選択的に設けた逆導電型のベース領域
及びツェナーダイオードと、前記ベース領域内に設けた
一導電型のエミッタ領域と、前記ベース領域及びツェナ
ーダイオードと接続し且つ誘電体膜を介して前記半導体
基板との間にコンデンサを形成する電極とを備えてい
る。According to a second semiconductor device of the present invention, an opposite conductivity type base region and a Zener diode are selectively provided on the upper surface of a one conductivity type semiconductor substrate, and one conductivity type emitter region is provided in the base region. And an electrode that is connected to the base region and the Zener diode and forms a capacitor between the base region and the Zener diode and the semiconductor substrate via a dielectric film.
【0007】[0007]
【実施例】次に、本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.
【0008】図1は本発明の第1の実施例を示す半導体
チップの断面図である。FIG. 1 is a sectional view of a semiconductor chip showing a first embodiment of the present invention.
【0009】図1に示すように、N型シリコン基板1の
表面に設けた酸化シリコン膜2を選択的にエッチングし
て第1の開孔部を設け、開孔部のN型シリコン基板1の
表面にアクセプター不純物を拡散してP型領域3を形成
する。次に、第1の開孔部を含む表面に酸化シリコン膜
を堆積して選択的に第2の開孔部を設けドナー不純物を
拡散してP型領域3内にN型領域4を形成してNPNト
ランジスタ部を設け、同様にP型領域3内にN+ 型領域
5を形成して、P・N+ 接合のツェナーダイオード部を
設けP型領域3内にP+ 型領域6を形成してコンデンサ
部の一方の電極を設ける。次に、開孔部の表面に熱酸化
膜を設けてN型領域4及びN+ 領域5上の酸化膜を除去
し、アルミニウム層を選択的に設けて電極7を形成して
NPNトランジスタ部及びツェナーダイオード部とコン
デンサ部を接続し、N型シリコン基板1の裏面に電極8
を設け、図2に示す等価回路の複合素子を構成する。As shown in FIG. 1, the silicon oxide film 2 provided on the surface of the N-type silicon substrate 1 is selectively etched to form a first opening portion, and the N-type silicon substrate 1 at the opening portion is formed. The acceptor impurities are diffused on the surface to form the P-type region 3. Next, a silicon oxide film is deposited on the surface including the first opening portion, the second opening portion is selectively provided, and the donor impurity is diffused to form the N-type region 4 in the P-type region 3. To form an N + type region 5 in the P type region 3 and to form a P · N + junction Zener diode portion to form a P + type region 6 in the P type region 3. One electrode of the capacitor section is provided. Next, a thermal oxide film is provided on the surface of the opening to remove the oxide film on the N-type region 4 and the N + region 5, and an aluminum layer is selectively provided to form an electrode 7 to form an NPN transistor portion and The Zener diode part and the capacitor part are connected, and the electrode 8 is formed on the back surface of the N-type silicon substrate 1.
To form a composite element having the equivalent circuit shown in FIG.
【0010】ここで、カソード(電極7)端子に正,ア
ノード(電極8)端子に負の電圧を印加していき、ある
電圧を越えるとP・N+ 接合のツェナーダイオードがブ
レークダウンして、NPNトランジスタのベースに電流
が注入され、トランジスタがオンする。トランジスタが
電流増幅するので、動作抵抗が1/hfeになる。Here, a positive voltage is applied to the cathode (electrode 7) terminal and a negative voltage is applied to the anode (electrode 8) terminal, and when a certain voltage is exceeded, the Zener diode of the P.N.sup. + Junction breaks down, Current is injected into the base of the NPN transistor, turning on the transistor. Since the transistor amplifies the current, the operating resistance becomes 1 / h fe .
【0011】図3は本発明の第1の実施例の電圧対電流
特性を示す図である。FIG. 3 is a diagram showing the voltage-current characteristics of the first embodiment of the present invention.
【0012】図3に示すようにトランジスタの出力(コ
レクタ)からコンデンサを通してトランジスタの入力
(ベース)にツェナーダイオードの雑音電圧を負帰還さ
せ、出力特性の雑音を小さくすることができる。As shown in FIG. 3, the noise voltage of the zener diode can be negatively fed back from the output (collector) of the transistor to the input (base) of the transistor through the capacitor to reduce the noise of the output characteristic.
【0013】図4は本発明の第2の実施例を示す半導体
チップの断面図である。FIG. 4 is a sectional view of a semiconductor chip showing a second embodiment of the present invention.
【0014】図4に示すよに、P型シリコン基板9の表
面に設けた酸化シリコン膜10を選択的にエッチングし
て第1の開孔部を設けドナー不純物を拡散し、N型領域
11a,11bを形成する。次に、N型領域11a,1
1b内に夫々P型領域12a,12bを形成して、PN
Pトランジスタ部を作る。また、P型シリコン基板9の
表面に選択的にN+ 型領域13を形成して、P・N+ 接
合のツェナーダイオード部を設け、更にP型シリコン基
板9の表面に選択的にP+ 型領域14を形成してコンデ
ンサ部の一方の電極を設ける。次に、開孔部の表面に熱
酸化膜を設けてP型領域12a,12b及びN+ 型領域
13の酸化膜を開孔し、アルミニウム層を選択的に設け
て電極15a,15b,15cを形成し、P型シリコン
基板9の裏面に電極16を設け、図5に示す等価回路の
複合素子を構成する。As shown in FIG. 4, the silicon oxide film 10 provided on the surface of the P-type silicon substrate 9 is selectively etched to provide a first opening to diffuse the donor impurity, and the N-type region 11a, 11b is formed. Next, the N-type regions 11a, 1
P-type regions 12a and 12b are formed in 1b, respectively, and PN
Make a P-transistor part. Further, the N + type region 13 is selectively formed on the surface of the P type silicon substrate 9 to provide a Zener diode portion of P · N + junction, and the P + type substrate 13 is selectively formed on the surface of the P + type. A region 14 is formed to provide one electrode of the capacitor section. Next, a thermal oxide film is provided on the surface of the opening to open the oxide film of the P type regions 12a and 12b and the N + type region 13, and an aluminum layer is selectively provided to form the electrodes 15a, 15b and 15c. Then, the electrode 16 is provided on the back surface of the P-type silicon substrate 9 to form the composite element of the equivalent circuit shown in FIG.
【0015】ここで、カソード(電極15c)端子に
正,アノード(電極16)端子に負の電圧を印加してい
き、ある電圧を越えるとP・N+ 接合のツェナーダイオ
ードがブレークダウンして、PNPトランジスタのベー
スに電流が流れ、トランジスタがオンする。トランジス
タが電流増幅するので動作抵抗が小さくなる。コンデン
サを通して、トランジスタのベースに雑音電圧を負帰還
させているので、雑音が小さくなる。Here, a positive voltage is applied to the cathode (electrode 15c) terminal and a negative voltage is applied to the anode (electrode 16) terminal. When a certain voltage is exceeded, the Zener diode of the P · N + junction breaks down, A current flows through the base of the PNP transistor, turning on the transistor. Since the transistor amplifies the current, the operating resistance is reduced. Since the noise voltage is negatively fed back to the base of the transistor through the capacitor, noise is reduced.
【0016】[0016]
【発明の効果】以上説明したように本発明は、半導体基
板にツェナーダイオード部とツェナー電流を増幅するト
ランジスタ部と雑音電圧をトランジスタに負帰還させる
コンデンサ部を形成することにより動作抵抗と雑音を小
さくできるという効果を有する。As described above, according to the present invention, the operating resistance and noise are reduced by forming the Zener diode section, the transistor section for amplifying the Zener current and the capacitor section for negatively feeding back the noise voltage to the transistor on the semiconductor substrate. It has the effect of being able to.
【図1】本発明の第1の実施例を示す半導体チップの断
面図。FIG. 1 is a sectional view of a semiconductor chip showing a first embodiment of the present invention.
【図2】本発明の第1の実施例の等価回路図。FIG. 2 is an equivalent circuit diagram of the first embodiment of the present invention.
【図3】本発明の第1の実施例の電圧対電流特性を示す
図。FIG. 3 is a diagram showing voltage-current characteristics of the first embodiment of the present invention.
【図4】本発明の第2の実施例を示す半導体チップの断
面図。FIG. 4 is a sectional view of a semiconductor chip showing a second embodiment of the present invention.
【図5】本発明の第2の実施例の等価回路図。FIG. 5 is an equivalent circuit diagram of the second embodiment of the present invention.
【図6】従来の半導体装置の一例を示す半導体チップの
断面図。FIG. 6 is a sectional view of a semiconductor chip showing an example of a conventional semiconductor device.
1 N型シリコン基板 2,10 酸化シリコン膜 3,12a,12b,18 P型領域 4,11a,11b N型領域 5,13,20 N+ 型領域 6,14,19 P+ 型領域 7,8,15a,15b,15c,16 電極 9 P型シリコン基板1 N-type silicon substrate 2, 10 Silicon oxide film 3, 12a, 12b, 18 P-type region 4, 11a, 11b N-type region 5, 13, 20 N + type region 6, 14, 19 P + type region 7, 8 , 15a, 15b, 15c, 16 electrodes 9 P-type silicon substrate
Claims (2)
電型のベース領域と、前記ベース領域内に設けた一導電
型のコレクタ領域及び一導電型のツェナーダイオード
と、前記コレクタ領域及びツェナーダイオードと接続し
且つ誘電体膜を介して前記ベース領域との間にコンデン
サを形成する電極とを備えたことを特徴とする半導体装
置。1. A base region of opposite conductivity type provided on the upper surface of a semiconductor substrate of one conductivity type, a collector region of one conductivity type and a zener diode of one conductivity type provided in the base region, and the collector region and zener. A semiconductor device, comprising: an electrode connected to a diode and forming a capacitor between the diode and the base region via a dielectric film.
けた逆導電型のベース領域及びツェナーダイオードと、
前記ベース領域内に設けた一導電型のエミッタ領域と、
前記ベース領域及びツェナーダイオードと接続し且つ誘
電体膜を介して前記半導体基板との間にコンデンサを形
成する電極とを備えたことを特徴とする半導体装置。2. A base region of opposite conductivity type and a Zener diode selectively provided on the upper surface of the one conductivity type semiconductor substrate,
An emitter region of one conductivity type provided in the base region,
A semiconductor device comprising: an electrode connected to the base region and the Zener diode and forming a capacitor between the base region and the Zener diode and the semiconductor substrate via a dielectric film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP03234237A JP3128885B2 (en) | 1991-09-13 | 1991-09-13 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP03234237A JP3128885B2 (en) | 1991-09-13 | 1991-09-13 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0575029A true JPH0575029A (en) | 1993-03-26 |
JP3128885B2 JP3128885B2 (en) | 2001-01-29 |
Family
ID=16967836
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP03234237A Expired - Fee Related JP3128885B2 (en) | 1991-09-13 | 1991-09-13 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3128885B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07202224A (en) * | 1993-12-28 | 1995-08-04 | Nec Corp | Semiconductor device |
US7625804B2 (en) * | 2004-06-08 | 2009-12-01 | Samsung Electronics Co., Ltd. | Structure for realizing integrated circuit having Schottky diode and method of fabricating the same |
JP2021525975A (en) * | 2018-05-30 | 2021-09-27 | サーチ フォー ザ ネクスト エルティディSearch For The Next Ltd | Circuits and devices including transistors and diodes |
-
1991
- 1991-09-13 JP JP03234237A patent/JP3128885B2/en not_active Expired - Fee Related
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07202224A (en) * | 1993-12-28 | 1995-08-04 | Nec Corp | Semiconductor device |
US7625804B2 (en) * | 2004-06-08 | 2009-12-01 | Samsung Electronics Co., Ltd. | Structure for realizing integrated circuit having Schottky diode and method of fabricating the same |
JP2021525975A (en) * | 2018-05-30 | 2021-09-27 | サーチ フォー ザ ネクスト エルティディSearch For The Next Ltd | Circuits and devices including transistors and diodes |
Also Published As
Publication number | Publication date |
---|---|
JP3128885B2 (en) | 2001-01-29 |
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Legal Events
Date | Code | Title | Description |
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A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20001017 |
|
LAPS | Cancellation because of no payment of annual fees |