JPH0566067B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image signal processing device that converts an input analog image signal into a digital image signal and processes it.

[Prior Art] Conventionally, as a method of image signal processing, it has been known to enhance the contour of an image signal using a level difference between a pixel of interest and its surrounding pixels.

[Problems to be Solved by the Invention] However, when contour enhancement is performed, slight noises other than the original image or noises added in the processing circuit are emphasized, making the reproduced image very unsightly. Sometimes I put it away.

Furthermore, in a configuration in which an analog image signal representing image density is converted into a digital image signal, and contour enhancement processing is performed on the digital image signal using the level difference between the pixel of interest and its surrounding pixels, the digital image signal is If the contrast, ie, the level difference between the digital image signal representing a white image and the digital image signal representing a black image, is sufficient, good contour enhancement processing can be performed.

Therefore, it is conceivable to perform processing to enhance the contrast of the digital image signal whose outline is to be emphasized. However, this contrast-enhancing processing also corrects the level of image signals that do not correspond to the contours, and as a result, contour enhancement processing is applied to areas other than the contours, which may result in an unsightly image. There is.

[Means for Solving the Problems] The present invention has been made in view of the above points, and includes an input means for inputting an analog image signal representing image density, and an input means for inputting an analog image signal representing an image density, and a digital image representing a multi-tone image. an analog-to-digital conversion means for converting into a signal; outputting digital image signals near the black level and white level among the digital image signals from the analog-to-digital conversion means as digital image signals indicating the black level and white level, respectively; a level conversion means for outputting an intermediate level digital image signal as it is; and a digital contour for performing contour enhancement processing on the digital image signal outputted from the level conversion means using a level difference between a pixel of interest and its surrounding pixels. The present invention provides an image signal processing device having a stiffening processing means.

[Embodiment] FIG. 1 is a basic block diagram of an embodiment of an image signal processing apparatus according to the present invention. In the figure, reference numeral 1 denotes a document, which is conveyed in the direction of the thick arrow by a mechanical conveyance device (not shown). 2 is a lens. 3 is a line CCD image sensor, but original 1
Other imaging means may be used as long as the brightness and darkness above can be read. For example, a 1:1 light receiving element may be used. Also,
Instead of transporting original 1, lens 2 and CCD
3 may be sub-scanned.

4 is a video amplifier, which amplifies the DC output voltage of CCD 3 to the required level. If an AC amplifier is used instead, a powerful clamp circuit is required.

5 is an automatic level control circuit (ALC circuit) that clamps the black level of the video signal to a constant voltage, for example, zero volts. Therefore, the video amplifier 4 may be an AC amplifier.

Reference numeral 6 denotes an automatic gain control circuit (AGC circuit) which automatically generates a video signal with a constant maximum amplitude even if there are changes in the amount of light from the light source (not shown), changes in the aperture value of the lens 2, variations in the sensitivity of the CCD 3, etc.

7 is a shading correction circuit that corrects uneven light intensity of the light source, peripheral light intensity characteristics of lens 2, for example, COS ⁴ θ
This is to correct the characteristics and sensitivity unevenness of CCD3. The details of the shading correction circuit 7 are disclosed in Japanese Patent Application Laid-Open No. 56-64566 filed by the present applicant, so a detailed explanation thereof will be omitted.

Reference numeral 8 denotes an A/D converter, in which the analog video signal is sampled into a digital signal by a clock pulse φ _T (not shown). The sampling level should be greater than or equal to the required gradation depth, for example, 6 bits.
The case of 64 gradations will be explained.

Reference numeral 9 denotes a limiter circuit corresponding to the level converting means of the present invention, which is used to remove small noises in the white background portion and black background portion of the image.

10 is a contour enhancement circuit that performs contour enhancement processing on the digital image signal.

11 is a peak detector, and contour reinforcement circuit 10
This is to automatically set the amount of correction for
The MTF characteristics of the lens 2 and the tensile circuit 10 are
It constitutes an equalization circuit that corrects the frequency characteristics of the CCD 3.

12 is a magnitude comparator, 13 is a read-only memory (ROM) for the dither matrix.
It is. Here, the characteristic-compensated digital video signal and dither matrix data written in advance in the ROM 13 are compared, and a 1-bit digital video signal is output from the output terminal 14.
The digital video signal output terminal 14 is connected to a printer via a modulator/demodulator (not shown) or directly connected to the printer to reproduce images.

The details of each circuit in FIG. 1 will be explained below.

(1) Automatic level control circuit (ALC circuit) Figure 2 shows a block diagram of one embodiment of the ALC circuit.

a is an input terminal, b _o (n=0, 1, 2...) is an output terminal, 50 is an adder, 51 is a multiplier, 52 is A
-D converter samples at clock _φT .
Although the multiplier 51 is not necessary for the ALC circuit, it is shown that it must be inserted in this stage when combined with the AGC circuit described later. The analog video signal that has passed through the adder 50 and multiplier 51 is quantized into, for example, a 6-bit digital signal by the A-D converter 52, and is applied to a magnitude comparator 53, which is applied to a preset preset switch. 54 data. Although a 6-bit magnitude comparator does not exist, it can easily be constructed by cascading 4-bit magnitude comparators.

The preset switch 54 is, for example, (000001)
Set it as In this case, when the video signal is (000000), the A<B output terminal becomes high level (hereinafter referred to as "H"), the A=B output terminal becomes low level (hereinafter referred to as "L"), and the video signal When is (000001), A<B output terminal is “L”
In this case, the A=B output terminal is "H". Furthermore, when the video signal is greater than (000010), both are “L”.
becomes.

55 is a counter which is reset by the horizontal synchronizing signal φ _x , counts the transfer clock φ _T , and calculates Q _h.
= (n=0, 1, 2, ...). The number of bits is set to the number necessary to separate the image section of the CCD 3 from the non-image black level section. For example, if you set 12 bits, you can specify addresses for 4096 pixels. The counter 55 is configured, for example, by cascading three stages of 4-bit synchronous counters.

56 is a gate circuit, which is a logic circuit for addressing the black level section of the non-image area in the video signal.
For example, it is configured using a multi-input AND circuit. G
is its output terminal, which is connected to the AND gate 57 and gates the "A<B" signal in the black level section.

Reference numeral 58 denotes an up/down counter which loads preset data into the preset switch 59 using the vertical synchronizing signal "COPY" and counts up (or down) the horizontal synchronizing signal φ _x . The outputs Q _A to Q _F of the up-down counter 58 are D-
The signal is input to the A converter 60, converted into an analog signal by the transfer clock φ _T , and input to the other input terminal B of the adder 50.

The level control mechanism is as follows. first,
At the start of image reading, the up-down counter 58 is set to the preset switch 5 by the signal "COPY".
Load the data of 9 and use that value as it is D-A
The signal is transmitted to a converter 60 and converted into an analog signal. The analog signal and video input signal are added together and A-
D-converted. As a result, if the black level is larger than (000010), the "A<B" output becomes "L", the up-down counter 58 goes into countdown mode, and the previously loaded data is horizontally Countdown is performed in synchronization with the synchronization signal φ _x .

Then, the DC level of the video signal applied to the input terminal of the A-D converter 52 begins to fall for each line reading scan, and the "A=B" output becomes "H", that is,
When the black level of the output signal of the A-D converter 52 reaches (000001), the "INH" input of the up-down counter 58 becomes "H" and stops counting. That is, the black level of the video signal is (000001). If the black level of the output video signal of the A-D converter 52 becomes (000000), the "A<B" output terminal becomes "H" and the up/down counter 58 counts up. mode, and the DC level of the video signal acts in the opposite direction. Thus, the black level of the video signal is (000001).

The setting value of the preset switch 59 is determined by converting the value from D to A and adding it to the video input signal.
The black level when converted is preset switch 5
Set it to a value that is equal to or closest to the value of 4. Preset switches 54 and 5
For example, it is convenient to use a hexadecimal code switch.

As described above, the automatic level control circuit in the image signal processing device of this embodiment includes an A-D converter as an analog-to-digital conversion circuit that converts an input analog image signal into an image digital value, and an A-D converter that converts the input analog image signal into an image digital value. A comparator as a comparison circuit that compares with set data, an up-down counter as a digital processing circuit whose output digital value changes according to the output of the comparison circuit, and a digital converter that converts the output digital value into an analog signal. A DA converter as an analog conversion circuit,
It has an adder as an addition circuit that adds the analog signal and the analog image signal, and the closed loop circuit includes the analog-to-digital conversion circuit, the comparison circuit, the digital processing circuit, the digital-to-analog conversion circuit, and the addition circuit. Therefore, the image digital value corresponding to the analog image signal at a predetermined level can be converged to the data. Furthermore, the level can be controlled with an accuracy of one least significant bit of the image digital value.

(2) Automatic gain control circuit (AGC circuit) Figure 3 shows a block diagram of an embodiment of the AGC circuit.

c is an analog video input terminal, b _o (n=0, 1,
2,...) are output terminals. 51 is an analog multiplier, which has the following relationship: X・Y=Z (1). That is, by varying the DC level Y, the amplitude X of the video signal can be controlled.

Note that components with the same number are the same in all drawings. The video signal quantized by the A-D converter 52 is applied to a peak hold circuit 61. Details of the peak hold circuit 61 are shown in FIG.

In Figure 4, V _o (n=0, 1, 2,...)
is the input signal and W _o is the peak-held output signal. 207 is a latch circuit, and 208 is a magnitude comparator.

Suppose that a new input is applied to _Vo while the latch outputs Q _A to Q _F are holding a certain value.
Both values are compared in magnitude by the magnitude comparator 208, and as a result, if the new input V _o is larger, "A>B" and the output becomes "H".
Open AND gate 209.

On the other hand, the clock φ _T that passes only the image area by the AND gate 210 is further processed by the AND gate 210.
09 and acts on the load terminal LD of the latch 207 to latch new data as a peak value. Furthermore, since the latch 207 is cleared by the horizontal synchronizing signal φ _x , the latch data immediately before clearing is the peak value of one line before.

In FIG. 3, the peak held video signal is applied to a magnitude comparator 62 and compared in magnitude with data from a preset switch 63. The preset switch 63 is set to, for example, (111110) in advance.

64 is an up-down counter, 65 is a preset switch, and 66 is a DA converter, which operates in the same way as the ALC circuit. That is, the preset switch 65 is a switch that initially determines the amplitude of the video signal, and the preset switch 63
stores the white level peak value of the video signal to be converged as a set value. In the previous reading scan, if the white level peak value of the input video signal is less than the set value (111110) of the preset switch 63, the up-down counter 64 is counted up by 1 bit to increase the gain of the multiplier 51 and vice versa. If the white level peak value of the video signal is larger than the set value of the preset switch 63, the gain of the multiplier 51 is controlled to decrease. Also, the white level peak value of the video signal is set to the preset switch 63.
When the gain of the multiplier 51 is equal to the set value, the gain of the multiplier 51 is held at the same value.

As described above, the automatic gain control circuit in the image signal processing device of this embodiment includes an A-D converter as an analog-to-digital conversion circuit that converts an input analog image signal into an image digital value, and an A-D converter that converts the input analog image signal into an image digital value. A comparator as a comparison circuit that compares with preset data, an up-down counter as a digital processing circuit whose output digital value changes according to the output of the comparison circuit, and a circuit that converts the output digital value into an analog signal. A D-A converter as a digital-to-analog conversion circuit,
It has a multiplier as a multiplication circuit that multiplies the analog signal and the analog image signal, and the closed loop circuit includes the analog-to-digital conversion circuit, the comparison circuit, the digital processing circuit, the digital-to-analog conversion circuit, and the multiplication circuit. It consists of Therefore, the image digital value obtained by converting the input analog image signal of a predetermined level converges to the data, and it becomes possible to always stably amplify the input analog image signal.

(3) Limiter Circuit FIG. 5 shows a block diagram of an embodiment of the limiter circuit 9 (FIG. 1) corresponding to the level conversion means of the present invention.

d _o (n=0, 1, 2, . . . ) is an input terminal, and e _o is an output terminal.

70 is a magnitude comparator, 71 is a preset switch, 72 to 77 are OR circuits, 78
is a magnitude comparator, 79 is a preset switch, and 80 to 85 are AND circuits.

For example, (111011) in the preset switch 71
is set, if the input signal becomes larger than that, the magnitude comparator 70's "A>
B” output terminal becomes “H”, and the OR gate 72~
The output of 77 is (111111). Also, if you set the preset switch 79 to, for example, (000100), if the input signal is not smaller than that,
The “A>B” output terminal of the magnitude comparator 78 becomes “L”, and the AND gates 80 to 85
The output will be (000000).

The input/output characteristics of this limiter circuit are schematically shown in FIG. 6 in analog form. In addition, examples of waveforms before and after processing by the limiter circuit are shown in Figure 7-A.
Shown in b. The waveforms are schematically illustrated in analog form.

By installing this filter, not only the noise in the white background and black background part of the image is removed, but also the line drawing part where the amplitude of the image signal from which the noise has been removed is low is enhanced by the contour enhancement circuit described later. case,
It is characterized by a change in waveform that tends to become more tense. Therefore, the above-described limiter circuit can fully exhibit its effects by installing it before the contour reinforcing circuit.

As described above, this embodiment includes a conversion circuit that converts an analog image signal into a digital value having a plurality of bits; Since the digital value greater than or equal to the value is matched with the maximum digital value, noise in the white and black areas of the image is removed, and the line drawing area with low amplitude of the image signal from which the noise has been removed is processed by the contour enhancement circuit. When tensing, it is possible to change the waveform to one that is more likely to be tensed.

(4) Contour reinforcement circuit Figure 8 shows a block diagram of the contour reinforcement circuit. This circuit is basically a contour enhancement circuit using a transversal filter.

It is well known that contour enhancement can be performed by subtracting the Laplacian ▽ ² (x, y) = ∂ ² /∂x ² +∂ ² /∂x ² (2) from the original image signal (x, y). It is being The discrete values of the Laplacian for a digital image are ▽ ² (i, j) = Δx ² (i, j) + Δy ² (i, j
)
= (i+1,j)+(i-1,j)+(i,j
+1)+(i,j-1)-4(i,j) (3) If i is the main scanning direction and j is the sub-scanning direction, the calculation coefficients of equation (3) can be diagrammed as shown in FIG. 9A. However, the sign is reversed, and this negative Laplacian may be added to the original image. In this case, the second-order partial differential coefficient in the main scanning direction and the second-order partial differential coefficient in the sub-scanning direction are set to be equal.

However, if this operator is used as is to enhance the contour, the resolution in the main scanning direction and the resolution in the sub-scanning direction will differ. Therefore, the manuscript
A phenomenon occurs in which an image read and reproduced with a 90° rotation is different from an image read and reproduced without rotation. When the present inventors investigated the reason for this, the following facts were found.

That is, as shown in Figure 1, when reading an image using a one-dimensional CCD image sensor, the main scanning is
This is done electrically using the CCD's internal register, but sub-scanning is done mechanically.

Therefore, the cause of deterioration of image reading resolution is the lens resolution (MTF) in the sub-scanning direction.
However, in the main scanning direction, the CCD
It has been found that the resolution in the main scanning direction is inferior to that in the sub-scanning direction because of the deterioration in resolution due to the finite transfer efficiency of . For example, as an example, FIG.
21 is shown. However, identifying the frequency of the lens is
The MTF of the lens is normalized by the frequency characteristics of the CCD transfer clock _φT .

In this way, the spatial frequency characteristics in the main scanning direction are
This is more than twice as bad as the spatial frequency characteristic in the sub-scanning direction.
Therefore, the partial differential coefficient in the sub-scanning direction is set to be half of the partial differential coefficient in the main scanning direction, as shown in FIG. 19B.
When the frequency characteristic of the video signal obtained by convolving the operator in Fig. 9A in the main scanning direction is multiplied by the frequency specification 220 including the lens and CCD in Fig. 10, the result is as shown in Fig. 11. Become. Furthermore, when the frequency characteristic of the video signal obtained by convolving the operator in FIG. 9B in the sub-scanning direction is multiplied by the frequency characteristic 221 of the lens alone in FIG.
It will look like Figure 12. FIG. 11 shows a total frequency characteristic diagram in the main scanning direction, and FIG. 12 shows a total frequency characteristic diagram in the sub-scanning direction. Here, when convolving the operator in FIG. 9(b) in the main scanning direction, the operator in the sub-scanning direction is ignored in the calculation.

When the input waveform is a cosine wave COS(ωτ), the frequency transfer function G(ω) in the main scanning direction is G(ω)=3−2COS(ωτ) (4). Similarly, the frequency transfer function H(ω) of the filter in the sub-scanning direction is H(ω)=1.5−COS(ωτ) (5). Note that τ indicates a fixed delay time.

The circuit shown in FIG. 8 specifically performs this calculation. That is, let M be the partial differential coefficient in the main scanning direction,
Also, if the partial differential coefficient in the sub-scanning direction is N, then ▽ ² (i, j) = M△x ² (i, j) + N△y ²
(i,j)=M(i+1,j)+M(i-1,j)=
This is the calculation of the formula given by N(i,j+1)+N(i,j-1)-2(M+N)(i,j) (6). When the coefficients of the calculation for the pixel of interest are diagrammed, it becomes as shown in FIG. 13.

In FIG. 8, 100 is a shift register,
Delays one line of video signal. 10
1 is also a shift register.

A latch 102 delays the video signal for one pixel. 103-106 are also latches.

107 and 109 are adders, 108 and 110
is a multiplier. Since the multipliers 108 and 110 have a multiplier of 2, the actual circuit requires only replacing the data lines as shown in FIG.

111 and 112 are subtracters, for example, the 15th
As shown in the figure, this can be realized by a two's complementer using an adder. Here 150 is an adder, 152-1
57 is an inverter. In Figure 8, 11
3 and 115 are multipliers, for example, parallel multipliers as shown in FIG. 16 are used. Here, 160 to 164
is an adder, and 165 to 200 are AND circuits.

In FIG. 8, 114 and 116 are switches, the switch 114 sets the coefficient N, and the switch 116 sets the coefficient M, respectively. 117 is an adder, and 131 is a multiplier. For the multiplier 131, for example, a circuit as shown in FIG. 16 can be used. The multiplier multiplies the data from the peak detector 11. 118 is an adder, 119
is a latch.

In this way, by calculating the differential coefficient in the main scanning direction and the differential coefficient in the sub-scanning direction using independent multipliers, it is possible to perform optimal blur correction in both the horizontal and vertical directions. Also, multiplier 1
31 is used to vary the differential coefficients M and N simultaneously while maintaining a proportional relationship, and the control signal for automatic equalization in the frequency domain is added here, but it is not limited to this only. For example, instead of providing switches 114 and 116, they may be used as control lines. In that case, if the functions of the differential coefficients M and N are 2 ⁿ times (n is an integer), then
Simply replacing the signal lines is sufficient; in other cases, a multiplier (not shown) is inserted in either one for parallel control.

As described above, this embodiment includes a contour enhancement circuit that enhances the contour of the image signal in the main scanning direction and the sub-scanning direction, centering on the pixel of interest of the image signal, and Since the differential coefficient M as a correction coefficient for contour enhancement in the direction is set larger than the differential coefficient N in the sub-scanning direction, the resolution of the reproduced image is the same in both the main-scanning direction and the sub-scanning direction. There is no difference between an image read and reproduced after being rotated by 90 degrees and an image read and reproduced without rotation, and optimal blur correction can be performed in each direction.

[Effects of the Invention] As explained above, according to the present invention, among the digital image signals from the analog-to-digital conversion means, digital image signals near the black level and white level are converted into digital images indicating the black level and white level, respectively. The intermediate level digital image signal is output as a signal, and the digital image signal at the intermediate level is output as it is. It becomes possible to perform good contour enhancement processing on the image signal of the contour portion without performing unnecessary contour enhancement processing on the image signal.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the image signal processing device according to the present invention, Fig. 2 is a block diagram of an automatic level control circuit, Fig. 3 is a block diagram of an automatic gain control circuit, and Fig. 4 is a peak hold circuit. 5 is a block diagram of the limiter circuit, FIG. 6 is a diagram showing an example of input/output characteristics of the limiter circuit, FIG. 7 is a diagram showing an example of input and output waveforms of the limiter circuit,
Figure 8 is a block diagram of the contour enhancement circuit for blur correction.
Figure 9 shows the Laplacian, Figure 10 shows the frequency characteristics of the lens and CCD, Figure 11 shows the frequency characteristics after equalization in the main scanning direction, and Figure 1 shows the frequency characteristics after equalization in the main scanning direction.
Figure 2 is a diagram showing the frequency characteristics after equalization in the sub-scanning direction, Figure 13 is a diagram showing the calculation coefficients of the Laplacian, Figure 14 is the circuit diagram of the multiplier, Figure 15 is the circuit diagram of the subtracter, Figure 16 is a circuit diagram of a parallel multiplier. In the figure, 1 is the original, 2 is the lens, and 3 is the
CCD, 4 is video amplifier, 5 is ALC circuit, 6 is
7 is an AGC circuit, 7 is a shading correction circuit, 8 is an A-D converter, 9 is a limiter circuit, and 10 is a contour strengthening circuit.

Claims (1)

[Scope of Claims] 1. Input means for inputting an analog image signal representing image density; Analog-to-digital conversion means for converting the input analog image signal into a digital image signal representing a multi-tone image; and the analog-to-digital conversion. Level converting means for outputting digital image signals near the black level and white level among the digital image signals from the means as digital image signals indicating the black level and white level, respectively, and outputting the intermediate level digital image signals as they are; An image signal processing device comprising digital contour enhancement processing means for performing contour enhancement processing on the digital image signal output from the level conversion means using a level difference between a pixel of interest and its surrounding pixels. .