JPH0229270B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image signal processing device that processes multiple systems of different image signals.

When contour enhancement processing is performed after converting an image signal into a digital signal, a contour enhancement circuit that performs such enhancement processing requires a large number of components, as shown in FIG. 7, for example. If this contour strengthening circuit is provided for each of a plurality of image pickup elements, the cost will be high and the size of the device will increase.

Furthermore, if multiple image sensors are driven sequentially and the sequentially output image signals are processed by one contour processing circuit, it is possible to prevent the circuit configuration from increasing in size. The disadvantage is that it takes a long time.

The present invention has been made in view of the above points, and includes a plurality of image sensors that are driven in parallel and output image signals in accordance with a predetermined transfer clock, and a plurality of systems of images output from each of the plurality of image sensors. A plurality of control means each controlling the signal level, and a plurality of image signals outputted in parallel from the plurality of control means are alternately selected for each pixel.
a combining means for outputting a system of image signals; and a processing means for processing one system of image signals output from the combining means in accordance with a processing clock faster than a transfer clock for image signals from the plurality of image pickup devices. The present invention provides an image signal processing device having the following features.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a basic block diagram of an embodiment of an image signal processing apparatus according to the present invention. In the figure,
Reference numeral 1 denotes a document, which is conveyed in the direction of the bold arrow by a mechanical conveyance device (not shown). 2 is a lens. 3 is a line CCD imaging device, but other imaging means may be used as long as the brightness and darkness on the original 1 can be read. For example, a 1:1 light receiving element may be used. Instead of conveying the original 1, the lens 2 and CCD 3 may be used for sub-scanning. A video amplifier 4 amplifies the output voltage of the CCD 3 to a required level. If an AC amplifier is used instead, a powerful clamp circuit is required. 5 is an automatic level control circuit (ALG circuit),
Clamp the black level of the video signal to a constant voltage, for example zero volts. Therefore, the video amplifier 4 may be an AC amplifier. 6 is an automatic gain control circuit (AGC circuit), which controls changes in the amount of light from the light source (not shown);
Even if there are changes in the aperture value of the lens 2, variations in the sensitivity of the CCD 3, etc., a video signal with a constant maximum amplitude is automatically created. 7 is a shading correction circuit, which corrects uneven light intensity of the light source, peripheral light intensity characteristics of lens 2,
For example, it corrects the COS ⁴ θ characteristic and the sensitivity unevenness of the CCD 3. The details of the shedding correction circuit 7 are disclosed in the patent application filed in 1983 by the present applicant.
Since it is disclosed in No. 140787, the explanation will be omitted.

Reference numeral 8 denotes an A-D converter, in which the analog video signal is sampled into a digital signal by a clock pulse φ _T (not shown). The sampling level may be greater than or equal to the required gradation depth; for example, a case of 6 bits and 64 gradations will be explained.

Reference numeral 9 denotes a limiter circuit for removing small noises in the white and black parts of the image.

10 is a contour enhancement circuit that performs contour enhancement processing on the digital image signal.

Reference numeral 11 denotes a beak detector for automatically determining the correction amount of the contour strengthening circuit 10.
It constitutes an equalization circuit that corrects the frequency characteristics of the CCD 3. 12 is a magnitude comparator,
13 is a read-only memory (ROM) for the dither matrix. Here, the characteristic-compensated digital video signal and the dither matrix data written in advance in the ROM 13 are compared, and a 1-bit digital video signal is output to the output terminal 1.
Output from 4. The digital video signal output terminal 14 is connected to a printer via a modulator/demodulator (not shown) or directly connected to the printer to reproduce images.

FIG. 2 is a basic block diagram of an embodiment of the image signal processing device of the present invention when two CCD image pickup devices are used. As the size of the document to be read increases, a larger CCD is also required, but in reality, due to the manufacturing process of silicon elements, it is difficult to manufacture large CCDs, and even if they were to be realized, it would be extremely difficult to manufacture large CCDs. It becomes expensive. Therefore
A reading method using multiple CCDs is generally well known. FIG. 2 shows two complete systems of automatic equalizers for video signals in the frequency domain shown in FIG. . However, configuring two video signal processing circuits in this manner is economically disadvantageous. Therefore, in FIG. 3, the contour strengthening circuit 10 and the contour strengthening circuit 23, which have the most complicated circuit configuration and large scale, are configured with one contour strengthening circuit 30, and time-division control is performed. It shows.

In Figures 2 and 3, 15 is a lens;
6 is a CCD, 17 is a video amplifier, 18 is an automatic level control circuit (ALC), 19 is an automatic gain control circuit (AGC circuit), 20 is a shading correction circuit,
21 is an A-D converter, 22 is a limiter circuit, 2
3 and 30 are contour enhancement circuits consisting of digital filters, 24 is a peak detector, 25 is a magnitude comparator, and 26 is for a dither matrix.
ROM, respectively lens 2, CCD 3, and
Video amplifier 4, ALC 5, AGC 6, shedding correction circuit 7, A-D converter 8, limiter circuit 9, contour enhancement circuit 10, peak detector 11,
It has the same functions as the magnitude comparator 12 and the dither matrix ROM 13. Also, 2
7 and 29 are video signal output terminals, and 28 is a parallel/serial converter.

The details of each circuit shown in FIGS. 1 to 3 will be explained below.

□1 Automatic level control circuit (ALC circuit) Figure 4 shows a block diagram of one embodiment of the ALC circuit.

a is an input terminal, bn (n=0, 1, 2,...) is an output terminal, 50 is an adder, 51 is a multiplier, 52
is sampled by the A/D converter using the clock _φT . Although the multiplier 51 is not necessary for the ALC circuit, it is shown that it must be inserted in this stage when combined with the AGC circuit described later.
The analog video signal that has passed through the adder 50 and the multiplier 51 is quantized into, for example, a 6-bit digital signal by the A-D converter 52, and applied to a magnitude comparator 53, which is then applied to a preset preset switch 54. compared to data. Although a 6-bit magnitude comparator does not exist, it can easily be constructed by connecting 4-bit magnitude comparators in series. Preset switch 5
4 is set to (000001), for example. In this case, when the video signal is (000000), the A<B output terminal becomes high level (hereinafter referred to as "H"), and the A
=B output terminal is low level (hereinafter "L"), and when the video signal is (000001), A
<B output terminal is “L” and A=B output terminal is “H”. Additionally the video signal is (000010)
When it is larger, both become "L".

55 is a counter that is reset by the horizontal synchronizing signal _φX and counts the transfer clock _φT .
Output to Qn (n=0, 1, 2,...). The number of bits is set to the number necessary to separate the image section of the CCD 3 from the non-image black level section.
For example, if you set 12 bits, you can specify addresses for 4096 pixels. The counter 55 is constructed by, for example, three stages of 4-bit synchronous counters connected in cascade. Reference numeral 56 denotes a gate circuit, which is a logic circuit for addressing the black level section of the non-image portion of the video signal, and is constructed using, for example, a multi-input AND circuit. G is its output terminal, AND
It is connected to the gate 57 and gates the "A<B" signal in the black level section.

58 is an up/down counter, and the preset switch 59 is activated by the vertical synchronization signal "COPY".
Load the preset data into
Count up (or down) the horizontal synchronization signal _φX . Output of up-down counter 58
Q _A Q _F is input to the D-A converter 60, converted to an analog signal by the transfer clock _φT, and added to the adder 5.
0 is input to the other input terminal B.

The level control mechanism is as follows. First, at the start of image reading, the up-down counter 58 loads the data of the preset switch 59 by the signal "COPY", and the value is directly transferred to the
- It is transmitted to the A converter 60 and converted into an analog signal. The analog signal and video input signal are added and A-D converted. As a result, if the black level is larger than (000010), "A<B"
The output becomes “L” and the up-down counter 5
8 is in a countdown mode, and the previously loaded data is counted down in synchronization with the horizontal synchronizing signal _φX . Then, the DC level of the video signal applied to the input terminal of the A-D converter 52 begins to fall for each line reading scan, and the "A=B" output becomes "H", that is, the A-D
When the black level of the output signal of the converter 52 reaches (000001), the "INH" input of the up-down counter 58 becomes "H" and stops counting. That is, the black level of the video signal is (000001). If the black level of the output video signal of the A-D converter 52 becomes (000000), the "A<B" output terminal becomes "H".
As a result, the up-down counter 58 enters the count-up mode, and the DC level of the video signal acts in the opposite direction. Thus, the black level of the video signal is (000001). The setting value of the preset switch 59 is
It is converted and added to the video input signal, and set to a value such that the black level when A/D converted is equal to or closest to the value of the preset switch 54. Preset switches 54 and 59
For example, it is convenient to use a hexadecimal code switch.

As described above, the automatic level control circuit in the image signal processing device of this embodiment includes an A-D converter as an analog-to-digital conversion circuit that converts an input analog image signal into an image digital value, and an A-D converter that converts the input analog image signal into an image digital value. A comparator as a comparison circuit that compares with preset data, an up-down counter as a digital processing circuit whose output digital value changes according to the output of the comparison circuit, and a digital converter that converts the output digital value into an analog signal. - It has a D-A converter as an analog conversion circuit, and an adder as an addition circuit that adds the analog signal and the analog image signal, and the analog-to-digital conversion circuit, the comparison circuit, and the digital processing circuit. Since the digital-to-analog conversion circuit and the addition circuit constitute a closed loop circuit, the image digital value corresponding to the analog image signal at a predetermined level can be converged to the data. Furthermore, the level can be controlled with an accuracy of one least significant bit of the image digital value.

□2 Automatic gain control circuit (AGC circuit) Figure 5 shows a block diagram of an embodiment of the AGC circuit.

C is an analog video input terminal, bn (n=0,
1, 2...) are output terminals. 51 is an analog multiplier and has the following relationship: X・Y=Z (1). That is, by varying the DC level Y, the amplitude X of the video signal can be controlled.

Note that components with the same number are the same in all drawings. A-D converter 5
The video signal quantized by 2 is applied to a peak hold circuit 61. Details of the peak hold circuit 61 are shown in FIG.

In Figure 18, V _o (n=0, 1, 2...)
is the input signal, and ω _o is the output signal subjected to the peak hold circuit. 207 is a latch circuit, 208
is a magnitude comparator. When latch output Q _A ~ Q _F is holding a certain value,
Suppose a new input is applied to _ωo . Both values are compared in magnitude by the magnitude comparator 208, and as a result, if the new input V _o is larger, "A>B" and the output becomes "H".
Open AND gate 209.

On the other hand, the clock φ _T , which passes only both image areas through the AND gate 210, further passes through the AND gate 209 and is connected to the load terminal of the latch 207.
Acts on LD to latch new data as a peak value. Furthermore, since the latch 207 is cleared by the horizontal synchronizing signal _φX , the latch data immediately before clearing is the peak value of one line before.

In FIG. 5, the peak-held video signal is applied to a magnitude comparator 62 and compared in magnitude with data from a preset switch 63. The preset switch 63 is set to, for example, (111110) in advance. 64 is an up-down counter, 65 is a preset switch, 66 is a D-A converter,
The operation is the same as the ALC circuit described above. That is,
The preset switch 65 is a switch that first determines the amplitude of the video signal, and the preset switch 63 stores the white level peak value of the video signal to be converged as a set value. In the previous reading scan, if the white level peak value of the input video signal is less than the set value (111110) of the preset switch 63, the up-down counter 64 is counted up by 1 bit to increase the gain of the multiplier 51, and vice versa. If the white level peak value of the video signal is larger than the set value of the preset switch 63, the gain of the multiplier 51 is controlled to decrease. Further, when the white level peak value of the video signal is equal to the set value of the preset switch 63, the gain of the multiplier 51 is held at its same value.

As described above, the automatic gain control circuit in the image signal processing apparatus of this embodiment includes an A-D converter as an analog-to-digital conversion circuit that converts an input analog image signal into an image digital value, and an A-D converter that converts the input analog image signal into an image digital value. A comparator as a comparison circuit that compares with set data, an up-down counter as a digital processing circuit whose output digital value changes according to the output of the comparison circuit, and a digital converter that converts the output digital value into an analog signal. It has a D-A converter as an analog conversion circuit, and a multiplier as a multiplication circuit that multiplies the analog signal and the analog image signal, and the analog-to-digital conversion circuit, the ratio conversion circuit, and the digital processing circuit. ,
The digital-to-analog conversion circuit and the multiplication circuit constitute a closed loop circuit. Therefore, the image digital value obtained by converting the input analog image signal of a predetermined level converges to the data, and it becomes possible to always stably amplify the input analog image signal.

□3 Limiter Circuit FIG. 6 shows a block diagram of an embodiment of the limiter circuit 9 (FIG. 1).

d _o (n=0, 1, 2...) is an input terminal, and e _o is an output terminal.

70 is a magnitude comparator, 71 is a preset switch, 72 to 77 are OR circuits, 78 is a magnitude comparator, 79 is a preset switch, and 80 to 85 are AND circuits.

For example, if the preset switch 71 is set to (111011) and the input signal becomes larger, the "A>B" output terminal of the magnitude comparator 70 becomes "H".
The outputs of the OR gates 72 to 77 are (111111). Furthermore, if the preset switch 79 is set to (000100), for example, if the input signal becomes smaller than that, the "A>B" output terminal of the magnitude comparator 78 becomes "L", and the AND gate The output of 80-85 is (000000)
becomes. The input/output characteristics of this circuit are schematically shown in FIG. 19 in analog form. In addition, waveform examples before and after processing by the limiter circuit are shown in the second section.
Shown in Figure 0 A and B. The waveforms are schematically illustrated in analog form. By installing this filter, not only the noise in the white background and black background part of the image is removed, but also the part of the line drawing where the amplitude of the image signal from which the noise has been removed is low can be enhanced by the contour enhancement circuit described later. , it has the characteristic of changing to a waveform that is more likely to become tense. Therefore, the above-described limiter circuit can be sufficiently effective by installing it before the contour reinforcing circuit.

As described above, this embodiment includes a conversion circuit that converts an analog image signal into a digital value having a plurality of bits, and a second digital value that matches the digital value that is less than or equal to a first predetermined digital value with the minimum digital value.
Since the digital value above a predetermined digital value is matched with the maximum digital value, noise in the white background and black background parts of the image is removed, and the line drawing part where the amplitude of the image signal from which the noise has been removed is low is enhanced. When a circuit is used to emphasize, it is possible to change the waveform to one that is more easily emphasized.

□4 Contour reinforcement circuit (1) Figure 7 shows a block diagram of the contour reinforcement circuit.
This circuit is basically a contour enhancement circuit using a transversal filter. Original image signal f
(x, y) to Labrasian ▽ ² f (x, y) = ∂ ² f/∂x ² + ∂ ² f/∂y ² (2
) It has been well known that contour reinforcement can be performed by pulling . The Labrasian discrete values for digital images are ▽ ² f (i, j) = △ _x ² f (i, j) + △ _y ² f (i, j) = f (i + 1, j) + f (i - 1, j )+f(i,
j+1) +f(i, j-1)-4f(i, j) (3). If i is the main scanning direction and j is the sub-scanning direction, the calculation coefficient of equation (3) can be diagrammed as the 12th
It will look like Figure A. However, the sign is reversed,
This negative Labrasian may be added to the original image. In this case, the second-order partial differential coefficient in the main scanning direction and the second-order partial differential coefficient in the sub-scanning direction are set to be equal.

However, if this operator is used as is to enhance the contour, the resolution in the main scanning direction and the resolution in the sub-scanning direction will differ. Therefore, a phenomenon occurs in which the image read and reproduced after rotating the document by 90 degrees is different from the image read and reproduced without rotation. When the present inventors investigated the reason for this, the following facts were found.

In other words, as shown in Figure 1, when reading an image using a one-dimensional CCD image sensor, the main scan is
This is done electrically using the CCD's internal register, but sub-scanning is done mechanically.

Therefore, in the sub-scanning direction, the only cause of deterioration in image reading resolution is the resolution of the lens (MTF), whereas in the main scanning direction, the deterioration in resolution due to the finite transfer efficiency of the CCD is an additional factor. It has been found that the resolution in the main scanning direction is inferior to that in the sub-scanning direction because of the addition of For example, as an example, FIG. 21 shows a spatial frequency characteristic 220 including a lens and a CCD, and a spatial frequency characteristic 221 of a single lens. However, the frequency characteristic of the lens is the MTF of the lens normalized by the frequency of the CCD transfer clock _φT .

In this way, the spatial frequency characteristics in the main scanning direction are
This is more than twice as bad as the spatial frequency characteristic in the sub-scanning direction. Therefore, the partial differential coefficient in the sub-scanning direction is set to be half of the partial differential coefficient in the main scanning direction, as shown in FIG. 12B. Multiplying the frequency characteristic of the video signal obtained by convolving the operator shown in FIG. 12 (b) in the main scanning direction with the frequency characteristic 220 including the lens and CCD shown in FIG. Become. Also, the frequency characteristics of the video signal obtained by convolving the operator in Figure 12B in the sub-scanning direction, and the frequency characteristic 2 of the lens alone in Figure 21.
When multiplied by 21, it becomes as shown in Fig. 23. FIG. 22 shows a total frequency characteristic diagram in the main scanning direction, and FIG. 23 shows a total frequency characteristic diagram in the sub-scanning direction. Here, when convolving the operator in FIG. 12B in the main scanning direction, the operator in the sub-scanning direction is ignored in the calculation.

When the input waveform is a cosine wave cos(ωt), the frequency transfer function G(ω) in the main scanning direction is G(ω)=3−2cos(ωτ) (4). Similarly, the frequency transfer function H(ω) of the filter in the sub-scanning direction is H(ω)=1.5−cos(ωτ) (5). Note that τ indicates a fixed delay time.

The circuit shown in FIG. 7 specifically performs this calculation. That is, if the partial differential coefficient in the main scanning direction is M and the partial differential coefficient in the sub-scanning direction is N, then ▽ ² f (i, j) = M△ _x ² f (i, j) + N△ _y ² f(i,
j) =Mf(i+1,j)+Mf(i-1,j) +Nf(i,j+1)+Nf(i,j-1) -2(M+N)f(i,j) (6) It is an operation. When the coefficients of the calculation for the pixel of interest are diagrammed, it becomes as shown in FIG. 13.

In FIG. 7, 100 is a shift register that delays one line of video signals. 1
01 is also a shift register.

A latch 102 delays the video signal for one pixel. 103-106 are also latches. 107 and 109 are adders, 108 and 1
10 is a multiplier. Multipliers 108 and 110
Since the multiplier is 2, the actual circuit requires only replacing the data lines as shown in FIG.

111 and 112 are subtracters, for example, the ninth
As shown in the figure, this can be realized by a two's complementer using an adder. Here 150 is an adder, 15
2 to 157 are inverters. In Figure 7,
113 and 115 are multipliers, for example, the 11th
A parallel multiplier as shown in the figure is used.

Here, 160 to 164 are adders, and 165
~200 is an AND circuit. In Figure 7,
114 and 116 are switches, switch 11
4 sets the coefficient N, and the switch 116 sets the coefficient M, respectively. 117 is an adder, and 131 is a multiplier. For example, the multiplier 131 has a first
A circuit as shown in FIG. 1 can be used. The multiplier multiplies the data from the peak detector 11. 118 is an adder, and 119 is a latch.

In this way, by calculating the differential coefficient in the main scanning direction and the differential coefficient in the sub-scanning direction using independent multipliers, it is possible to perform the optimum pocket correction in each of the horizontal and vertical directions. Furthermore, the multiplier 131 is used to vary the differential coefficients M and N simultaneously and while maintaining a proportional relationship.
The automatic equalization control signal in the frequency domain is added here, but it is not limited to this only.
For example, instead of providing switches 114 and 116, they may be used as control lines. In that case, if the relationship between the differential coefficients M and N is 2 ⁿ times (n is an integer), it is sufficient to simply replace the signal lines; otherwise, insert a multiplier (not shown) into either one. control in parallel.

As described above, this embodiment has a contour enhancement circuit that enhances the contour of the image signal in the main scanning direction and the sub-scanning direction, centering on the pixel of interest of the image signal. Since the differential coefficient M as a correction coefficient for contour enhancement in the direction is set larger than the differential coefficient N in the sub-scanning direction, the resolution of the reproduced image is
Since both the sub-scanning directions match, there is no discrepancy between the image read and reproduced by rotating the original by 90 degrees and the image read and reproduced without rotation, making it possible to perform the optimum pocket correction in each direction.

□5 Contour reinforcement circuit (2) To construct a contour reinforcement circuit digitally, a large number of components are required as shown in FIG. 7. As shown in Figure 2, the reading device reads multiple
When reading with a CCD, one contour enhancement circuit can be used in a time-division manner as shown in FIG. 3 by taking advantage of the digital feature. The method will be specifically explained below.

FIG. 8 is a block diagram of an embodiment of a contour reinforcing circuit capable of time-division operation. h and i are the input image signals from each CCD driven in parallel.
With the converted digital signal, multiplexer 12
0 is selected alternately. multiplexer 120
The frequency of the switching clock is _2φT , which is twice the video signal transfer clock _φT . Here, the video signal that has become one signal line is returned to two signal lines by the demultiplexer 128 after filtering.

129 and 130 are latches, j and k
is its latch output. Demultiplexer 1
28 is operated by a 2φ _T clock, and the latch 129
and 130 are operated by the clock of _φT .

All components from multiplexer 120 to demultiplexer 128 are operated by a _2φT clock.

Functional elements that are the same as in FIG. 7 are given the same numbers.

Since the shift registers 100 and 101 receive two video signals alternately, it is not possible to delay the video signal for 1/2 line.
2 has been added. Similarly, 123-127 are added latch circuits. Since the other components are the same as those in FIG. 7, the number of components can be much reduced compared to the case where two independent digital contour reinforcement circuits are provided.

Although FIG. 8 describes the case where there are two video signals, a similar configuration can be made even when there are three or more video signals by adding shift registers and latches according to the number of video signals.

As described above, this embodiment includes a plurality of image sensors that read an original image, an analog-to-digital converter that converts the output image signal of the image sensor into a digital image signal, and a time-divided digital signal for each of the converters. a multiplexer as a selection circuit for selection; a contour enhancement circuit that enhances the contour by delaying the output digital signal of the selection circuit and comparing it with an adjacent digital signal; an output of the contour enhancement circuit for each converter; Since a demultiplexer is provided as a separating circuit, it is sufficient to provide only one contour reinforcing circuit, thereby reducing the number of parts and reducing costs.

□6 Automatic equalization in the frequency domain of video signals The frequency characteristics of the MTF 221 of the lens and the CCD 3 including the lens shown in Fig. 21 are not necessarily constant; for example, there are large variations in semiconductor devices such as CCDs, and the frequency characteristics Not constant. Also, the MTF of lens 2 is significantly affected by even a slight shift in focus adjustment. For example, if the light intensity is controlled by the aperture value of the lens, the MTF becomes worse as the aperture is opened. Therefore, it is difficult to deal with these frequency characteristic fluctuations by manual adjustment.

Therefore, in this embodiment, the video signal is automatically equalized in the frequency domain.

In order to automatically equalize a video signal in the frequency domain, the frequency characteristics of the video signal in the main scanning direction are measured in advance. When the order of the digital filter constituting the contour enhancement circuit in the main scanning direction is second order, the coefficients can be determined if the frequency characteristics at any three points are known. However, when the coefficients are symmetrical about the pixel of interest as shown in FIG. 13, the frequency characteristics may be measured at two points. In order to measure the video signal including the optical system, a test chart as shown in FIG. 14 is prepared. The lower half of this test chart is a pattern with a low spatial frequency, and the upper half is a pattern with a spatial frequency at or near the Nyquist limit. The lower half may be entirely black. This test chart is read and scanned to determine the peak black level value V _LF in the lower half area,
Peak value of black level in the upper half area V _HF
By sampling and holding each of these, the transmission characteristics of the video signal can be determined. Automatic equalization of the video signal can then be performed by determining the difference between V _LF and V _HF and increasing or decreasing the differential coefficient of the digital filter until the difference becomes zero.

FIG. 18 shows a peak hold circuit for peak holding V _LF or V _HF . V _o (n=
0, 1, 2...) are input terminals, and ω _o is an output terminal. 207 is a latch circuit, and 208 is a magnitude comparator. Suppose that a new input is applied to V while the latch outputs Q _A to Q _F are holding a certain value. Both values are compared in magnitude by the magnitude comparator 208, and as a result, if the new input V _o is larger, “A>H”, the output becomes “H”, and the AND gate 209 is opened. on the other hand
The clock φ _T which passes only the image area by the AND gate 210 further passes through the AND gate 209 and acts on the load terminal LD of the latch 207 to latch new data as a peak value. Furthermore, since the latch 207 is cleared by the horizontal synchronizing signal _φX , the latch data immediately before clearing is the peak value of one line before.

FIG. 17 shows an embodiment of a peak detector circuit for comparing peak values V _LF and V _HF . t _o
(n=0, 1, 2...) are video signal input terminals, U _o
is an output terminal for differential coefficient control. 201 and 2
02 is a peak hold circuit, and both use the peak hold circuit shown in FIG. The peak hold circuit 201 peak-holds V _LF . V _LF
EN is an enable signal for this purpose, and the timing is as shown in FIG. The peak hold circuit 202 peak-holds _VHF . V _HF EN
is an enable signal for that purpose. When the output V _LF PEAK of the peak hold circuit 201 and the output V _HF PEAK of the peak hold circuit 202 are schematically represented in an analog manner, it becomes as shown in FIG. V _LF PEAK
and V _HF PEAK is a magnitude comparator 20
The size is compared in 3.

204 is an up/down counter that counts the horizontal synchronizing signal _φX . A preset switch 205 is used to set the initial value of the differential coefficient. The data of the preset switch 205 is loaded into the up-down counter 204 by the vertical synchronization signal "COPY". 206 is a latch. The peak detector circuit in FIG. 17 is placed at position 11 in FIG. In addition, in Figures 7 and 8, 1
1, the multiplier 131
is controlling the multiplier. The input of the peak detector 11 in FIG. 7 may be the output g of the latch 119. The multiplier 131 changes the weighting of the addition output of the differential coefficient in the main scanning direction and the differential coefficient in the sub-scanning direction.
In other words, correction of the frequency characteristics in the sub-scanning direction is performed secondarily by sliding the control value in the main-scanning direction. With this method, a practically sufficient blur correction effect can be obtained for blur factors that commonly appear in the main scanning direction and the sub-scanning direction, such as the MTF of a lens. Of course, in FIG. 7, two systems of peak detectors 11 may be provided, one for the main scanning direction and one for the sub-scanning direction, and the multipliers 113 and 115 may be controlled independently.

In this case, the frequency characteristics in the sub-scanning direction are measured by using a test chart (not shown) which is a version of the test chart shown in FIG. 14 rotated by 90 degrees.

In the automatic equalization time chart in Figure 15, a, b, c, d, e attached to the video signal input
The symbols . . . correspond to the black lines a, b, c, d, e . . . on the test chart in FIG. In the first line of scanning, the video signal output is the input waveform as it is, but in the second line, the amplitude V _HF of the high spatial frequency video signal matches the amplitude V _LF of the low spatial frequency video signal, This shows that equalization has been completed.

The time chart in Figure 16 is based on Figures 2 and 3.
The timing chart for automatic equalization when two CCD image sensors are used as shown in the figure is shown. After the equalization is completed, a sequence controller (not shown) stops the counting operation of the up-down counter 204. In this way, the transmission characteristics of the video signal including the optical system can be automatically equalized in the frequency domain.
Although the description has been made using a second-order equalization filter, it is also possible to perform more precise equalization using a third-order or higher-order filter. In addition, as shown in Figure 14, the test chart used was a pattern in which a pattern with a low spatial frequency and a pattern with a high spatial frequency were placed separately, but if it can be separated using an appropriate bandpass filter, , patterns with a low spatial frequency and patterns with a high spatial frequency may be arranged in a mixed manner. The same applies to the sub-scanning direction. In that case, the bandpass filter may be analog or digital, but a digital filter is suitable for measuring the frequency characteristics in the sub-scanning direction.

As described above, this embodiment includes a CCD as an image sensor that reads an original image through an optical system, a strengthening circuit that strengthens the outline of an output image signal of the image sensor, and an output peak value of the strengthening circuit. a peak detector as a detection circuit that detects the output of the detection circuit when the image sensor reads an image with a high spatial frequency; and the detection when the output of the detection circuit reads an image with a spatial frequency lower than the spatial frequency. It has a multiplier as a control circuit for controlling the stiffening coefficient of the stiffening circuit to match the output of the circuit.

According to the above configuration, it is possible to automatically equalize the transmission characteristics of the image signal including the optical system in the frequency domain.

As explained above, according to the present invention, the output is output from each of the plurality of image sensors without providing a plurality of processing units corresponding to each of the plurality of image sensors and without sequentially driving the plurality of image sensors. It becomes possible to process multiple systems of image signals with a simple configuration and at high speed.

[Brief explanation of drawings]

Figure 1 is a block diagram of an automatic equalizer for video signals in the frequency domain, Figure 2 is a block diagram of an embodiment using two CCDs, and Figure 3 is a time-division use of the contour enhancement circuit. Fig. 4 is an automatic level control circuit diagram, Fig. 5 is an automatic gain control circuit diagram, Fig. 6 is a limiter circuit diagram,
Fig. 7 is a contour enhancement circuit diagram for blur correction, and Fig. 8 is a contour enhancement circuit diagram for blur correction for time-sharing use.
Fig. 9 is a subtracter circuit diagram, Fig. 10 is a multiplier circuit diagram, Fig. 11 is a parallel multiplier circuit diagram, Figs. 12 and 13 are diagrams showing the Labrasian, and Fig. 14 is a plan view of the test chart. , FIG. 15 is a diagram showing one example of an automatic equalization time chart, FIG. 16 is a diagram showing another example of an automatic equalization time chart, FIG. 17 is a peak detector circuit diagram, and FIG. 18 is a peak hold diagram. Circuit diagram, Fig. 19 is an input/output characteristic diagram of the limiter circuit, Fig. 20 is a diagram showing an example of input and output waveforms of the limiter circuit, Fig. 21 is a frequency characteristic diagram of the lens and CCD, and Fig. 22 is the main scanning direction. FIG. 23 is a frequency characteristic diagram after equalization in the sub-scanning direction. In the figure, 1 is the original, 2 is the lens, and 3 is
CCD, 4 is video amplifier, 5 is ALC circuit, 6 is
An AGC circuit, 7 a shading correction circuit, 8 an AD converter, 9 a limiter circuit, 10 a contour enhancement circuit, and 11 a peak detector, respectively.

Claims (1)

[Scope of Claims] 1. A plurality of image pickup devices that are driven in parallel and output image signals in accordance with a predetermined transfer clock; and controlling the levels of image signals of multiple systems output from each of the plurality of image pickup devices. a plurality of control means; a composition means for outputting one system of image signals by alternately selecting, pixel by pixel, multiple systems of image signals output in parallel from the plurality of control means; and an output from the composition means. and processing means for processing one system of image signals according to a processing clock faster than a transfer clock for image signals from the plurality of image pickup devices.