JPH0547974A - Semiconductor chip module - Google Patents
Semiconductor chip moduleInfo
- Publication number
- JPH0547974A JPH0547974A JP19956191A JP19956191A JPH0547974A JP H0547974 A JPH0547974 A JP H0547974A JP 19956191 A JP19956191 A JP 19956191A JP 19956191 A JP19956191 A JP 19956191A JP H0547974 A JPH0547974 A JP H0547974A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- heat sink
- heat
- chip module
- face
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 78
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 239000011810 insulating material Substances 0.000 claims abstract description 8
- 230000017525 heat dissipation Effects 0.000 abstract description 8
- 239000000463 material Substances 0.000 abstract description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 239000004020 conductor Substances 0.000 abstract description 4
- 238000000034 method Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 238000003780 insertion Methods 0.000 description 3
- 230000037431 insertion Effects 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- JOYRKODLDBILNP-UHFFFAOYSA-N Ethyl urethane Chemical compound CCOC(N)=O JOYRKODLDBILNP-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000009429 electrical wiring Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
(57)【要約】
【目的】 良好な放熱を実現することにより、高速性に
支障がない半導体チップモジュールを提供することを目
的とする。
【構成】 本発明に係る半導体チップモジュールは、配
線部が形成されている半導体基板6と、回路面が上向き
になるように実装され、この配線部上に配置された1個
または複数個の半導体チップ4と、これらの半導体チッ
プ4の回路側に一端部が接触したヒートシンク3と、こ
れらのヒートシンク3の他端部を外部に露出させる孔2
aが穿設され、半導体チップ4を全て内包するキャップ
2を備えている。半導体基板6とこの半導体基板6上に
搭載されたフェイスアップ型半導体チップ4を接続する
ボンディングワイヤ8を絶縁性の材料で被覆しているの
で、ヒートシンク3とボンディングワイヤ8が接触して
も電気特性が悪化することはない。したがって、ヒート
シンク3の大型化が可能になり、効率良く、熱放射する
ことができる。また、製造上も歩留まりの向上が実現で
き、ヒートシンク3の材料に導体を使用しやすくなるの
で材料コストの低減が実現できる。
(57) [Abstract] [Purpose] An object of the present invention is to provide a semiconductor chip module that does not hinder high-speed performance by realizing good heat dissipation. A semiconductor chip module according to the present invention is mounted on a semiconductor substrate 6 on which a wiring portion is formed and a circuit surface facing upward, and one or a plurality of semiconductors arranged on the wiring portion. Chip 4, heat sink 3 whose one end is in contact with the circuit side of these semiconductor chips 4, and hole 2 for exposing the other end of these heat sinks 3 to the outside
a is provided, and a cap 2 that encloses all the semiconductor chips 4 is provided. Since the bonding wire 8 that connects the semiconductor substrate 6 and the face-up type semiconductor chip 4 mounted on the semiconductor substrate 6 is covered with an insulating material, the electrical characteristics even if the heat sink 3 and the bonding wire 8 come into contact with each other. Does not get worse. Therefore, the size of the heat sink 3 can be increased, and heat can be efficiently radiated. In addition, the yield can be improved in manufacturing, and the conductor can be easily used as the material of the heat sink 3, so that the material cost can be reduced.
Description
【0001】[0001]
【産業上の利用分野】本発明は、コンピュータや通信な
どの信号処理の高速化が要求される分野に適用できるマ
ルチチップモジュール、シングルチップモジュールなど
の半導体チップを搭載した半導体チップモジュールに関
するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip module having a semiconductor chip such as a multi-chip module or a single chip module, which is applicable to a field requiring high speed signal processing such as computer and communication. ..
【0002】[0002]
【従来の技術】 電子機器の機能の大規模化および高速
化が求められるにつれ、論理LSIゲート1個当りの遅
延時間は数百psと高速化してきた。それに対して、プ
リント基板上に多数のDIPやプラグインパッケージを
搭載する従来の実装形態では高速化したLSIの性能を
十分に発揮させることが困難になってきた。そのため
に、1枚のセラミック基板上に多くのチップを高密度に
搭載し、高速性能なマルチチップモジュールが開発され
実用されている(LSIハンドブック、第1版、pp.
415−416、電子通信学会、1984年)。2. Description of the Related Art With the demand for large-scale and high-speed functions of electronic devices, the delay time per logic LSI gate has been increased to several hundreds ps. On the other hand, in the conventional mounting mode in which a large number of DIPs and plug-in packages are mounted on the printed circuit board, it has become difficult to sufficiently exert the performance of the accelerated LSI. For this purpose, a high-speed multi-chip module in which many chips are mounted at high density on one ceramic substrate has been developed and put into practical use (LSI Handbook, First Edition, pp.
415-416, IEICE, 1984).
【0003】図4に示されるように、このようなマルチ
チップモジュール方式等において、半導体チップをフェ
イスアップで実装した場合には、図4に示すように半導
体チップ4で発生した熱をX方向すなわち基板1側に逃
していた。半導体チップモジュールは、この放熱動作に
より熱抵抗による性能悪化を防いでいた。As shown in FIG. 4, when the semiconductor chips are mounted face up in such a multi-chip module system, the heat generated in the semiconductor chips 4 is transferred in the X direction as shown in FIG. It was missed to the substrate 1 side. The semiconductor chip module has prevented the performance deterioration due to thermal resistance due to this heat radiation operation.
【0004】[0004]
【発明が解決しようとする課題】しかし、発生した熱を
基板側に逃す方法のみでは、必ずしも十分な放熱を行う
ことができず、半導体チップモジュールの性能は序々に
悪化し、故障率も高くなり、長期間の使用が不可能にな
るという欠点があった。そこで本発明は、性能の悪化が
生じない良好な放熱設計ができる半導体チップモジュー
ルを提供することを目的とする。However, it is not always possible to sufficiently dissipate heat only by the method of releasing the generated heat to the substrate side, the performance of the semiconductor chip module gradually deteriorates, and the failure rate increases. However, there was a drawback that it could not be used for a long time. Therefore, an object of the present invention is to provide a semiconductor chip module capable of a good heat dissipation design without deterioration of performance.
【0005】[0005]
【課題を解決するための手段】本発明に係る半導体チッ
プモジュールは、配線部が形成されている半導体基板
と、いわゆるフェイスアップですなわち回路面が上向き
になるように実装されて、この配線部上に配置された1
個または複数個の半導体チップと、この半導体チップの
上面中央部に一端部が接触したヒートシンクと、このヒ
ートシンクの他端部を外部に露出させる孔が穿設され、
半導体チップを全て内包するキャップとを備え、半導体
基板とこの半導体基板上に搭載されている半導体チップ
を接続するボンディングワイヤが絶縁性材料で被覆され
ていることを特徴とするものである。A semiconductor chip module according to the present invention is mounted in a so-called face-up manner on a semiconductor substrate on which a wiring portion is formed, that is, a circuit surface faces upward, and the semiconductor chip module is mounted on the wiring portion. Placed in
One or more semiconductor chips, a heat sink whose one end is in contact with the center of the upper surface of the semiconductor chip, and a hole for exposing the other end of this heat sink to the outside are provided.
The semiconductor device is characterized in that it has a cap that encloses all semiconductor chips, and that the bonding wires connecting the semiconductor substrate and the semiconductor chips mounted on this semiconductor substrate are covered with an insulating material.
【0006】[0006]
【作用】本発明に係る半導体チップモジュールによれ
ば、フェイスアップ型の半導体チップから発生した熱は
半導体チップの上面に接触したヒートシンクの一端部か
ら他端部に伝導する。この熱伝導によって、熱はキャッ
プの外部に導かれ、キャップの外で発散される。According to the semiconductor chip module of the present invention, the heat generated from the face-up type semiconductor chip is conducted from one end of the heat sink contacting the upper surface of the semiconductor chip to the other end. By this heat conduction, heat is guided to the outside of the cap and radiated outside the cap.
【0007】さらに、半導体基板とこの半導体基板上に
搭載されている半導体チップを接続するボンディングワ
イヤを絶縁性材料で被覆しているので、たとえヒートシ
ンクが導電材であっても、ヒートシンクとボンディング
ワイヤの接触で電気的特性が悪化することはなく、ヒー
トシンクの大型化も可能になる。Further, since the bonding wire connecting the semiconductor substrate and the semiconductor chip mounted on the semiconductor substrate is covered with the insulating material, even if the heat sink is a conductive material, the heat sink and the bonding wire are not separated. The electrical characteristics are not deteriorated by the contact, and the heat sink can be increased in size.
【0008】[0008]
【実施例】図1は本発明の実施例に係る半導体チップモ
ジュールの外観を示す斜視図であり、図2は図1に示さ
れた半導体チップモジュールをII II´で切断した
時の断面図である。下部基板1は、例えばアルミナ材で
形成され、その側面からは上部基板6の上に構成された
電気配線と接続した複数のリードピン5が延びている。
上部基板6は低誘電率絶縁材料で形成され、例えば、熱
抵抗3℃/W、サマーバイヤを併用した3インチ角のポ
リイミド多層配線構造を使用することができる(“銅ポ
リイミド多層配線基板”、HYBRIDS、VOL.
7,No.7,pp.10−12参照)。1 is a perspective view showing the appearance of a semiconductor chip module according to an embodiment of the present invention, and FIG. 2 is a sectional view of the semiconductor chip module shown in FIG. 1 taken along line II II '. is there. The lower substrate 1 is made of, for example, an alumina material, and a plurality of lead pins 5 connected to the electrical wiring formed on the upper substrate 6 extend from the side surface of the lower substrate 1.
The upper substrate 6 is formed of a low dielectric constant insulating material, and for example, a 3-inch square polyimide multilayer wiring structure having a thermal resistance of 3 ° C./W and a summer bayer can be used (“copper polyimide multilayer wiring substrate”, HYBRIDS). , VOL.
7, No. 7, pp. 10-12).
【0009】また、下部基板1は、上部基板6よりも大
きい平板で構成され、この下部基板1の上面に上部基板
6が積み重なった状態で固定されている。上部基板6が
重なっていない下部基板1の上面にはキャップ2の縁部
が覆い被せられている。したがって、キャップ2と下部
基板1により上部基板6は内包された状態になってい
る。上部基板6の表面には電極が露出しており、これら
の電極と接続するようにフェイスアップ型半導体チップ
4およびフェイスダウン型半導体チップ4aが図のよう
に搭載されている。フェイスアップ型半導体チップ4
は、文字通り、回路面が上向きになっており、ボンディ
ングワイヤ法により上部基板6の配線と電気的に接続さ
れている。また、フェイスダウン型半導体チップ4a
は、回路面が下側になるようにダイボンディング法等に
より上部基板6の配線と電気的に接続されている。The lower substrate 1 is composed of a flat plate larger than the upper substrate 6, and the upper substrate 6 is fixed on the upper surface of the lower substrate 1 in a stacked state. An edge portion of the cap 2 is covered on the upper surface of the lower substrate 1 where the upper substrate 6 does not overlap. Therefore, the upper substrate 6 is enclosed by the cap 2 and the lower substrate 1. The electrodes are exposed on the surface of the upper substrate 6, and the face-up type semiconductor chip 4 and the face-down type semiconductor chip 4a are mounted as shown in the figure so as to be connected to these electrodes. Face-up type semiconductor chip 4
Literally has a circuit surface facing upward and is electrically connected to the wiring of the upper substrate 6 by a bonding wire method. Also, a face-down type semiconductor chip 4a
Are electrically connected to the wiring of the upper substrate 6 by a die bonding method or the like so that the circuit surface faces downward.
【0010】また、キャップ2は、例えば、厚さ1mm
のコバールで蓋状に形成されていて、フェイスダウン型
半導体チップ4aの搭載位置と対応した位置に、例えば
直径30〜50μmぐらいの孔7aが穿設されている。
また、フェイスアップ型半導体チップ4の搭載位置と対
応した位置に、穿孔7aよりも直径が大きい孔7が穿設
されている。これらの穿孔7,7aにそれぞれヒートシ
ンク3,3aの一端部が挿入される。これらのヒートシ
ンク3,3aは熱導電率の高い材料であるAlやCuW
からなり、挿入部と放熱部で構成されている。挿入部
は、上記の穿孔7,7aに挿入しやすい、例えば棒状と
なっている。また、放熱部は、自動冷却されやすいよう
に表面積が大きくなる構造で、例えば、円盤上になって
いる。この放熱部は多段になるほど、冷却速度が速くな
る。ヒートシンク3,3aは、このような構成になって
いるのでキャップ2の内部への挿入が容易であり、キャ
ップ2の外部へフェイスアップ型半導体チップ4および
フェイスダウン型半導体チップ4aに発生した熱を効率
良く逃がすことができる。フェイスアップ型半導体チッ
プ4およびフェイスダウン型半導体チップ4aからヒー
トシンク3,3aに熱を効率よく伝えるために、ヒート
シンク3と半導体チップ面の接触方法は、面接触とする
のが望ましい。したがって、フェイスアップ型半導体チ
ップ4およびフェイスダウン型半導体チップ4aの上面
が平面になっている場合、ヒートシンク3,3aの挿入
部の先端は平面になっているのが望ましい。なお、回路
面にヒートシンク3が接触しても、回路面はSiNやS
iONからなるパッシベーション膜で保護されているの
で性能上の問題は起こらない。The cap 2 has a thickness of 1 mm, for example.
Is formed in the shape of a lid by Kovar, and a hole 7a having a diameter of, for example, 30 to 50 μm is formed at a position corresponding to the mounting position of the face-down type semiconductor chip 4a.
Further, a hole 7 having a diameter larger than that of the hole 7a is formed at a position corresponding to the mounting position of the face-up type semiconductor chip 4. One ends of the heat sinks 3 and 3a are inserted into these holes 7 and 7a, respectively. These heat sinks 3 and 3a are made of a material having high thermal conductivity such as Al or CuW.
It is composed of an insertion part and a heat dissipation part. The insertion portion has a rod shape, for example, which can be easily inserted into the perforations 7, 7a. Further, the heat radiating portion has a structure having a large surface area so as to be easily automatically cooled, and is, for example, a disk. The cooling speed increases as the number of stages of the heat radiation unit increases. Since the heat sinks 3 and 3a have such a configuration, they can be easily inserted into the inside of the cap 2, and the heat generated in the face-up type semiconductor chip 4 and the face-down type semiconductor chip 4a can be transferred to the outside of the cap 2. Can be released efficiently. In order to efficiently transfer heat from the face-up type semiconductor chip 4 and the face-down type semiconductor chip 4a to the heat sinks 3 and 3a, it is desirable that the heat sink 3 and the semiconductor chip surface are brought into surface contact. Therefore, when the upper surfaces of the face-up type semiconductor chip 4 and the face-down type semiconductor chip 4a are flat, it is desirable that the tips of the insertion portions of the heat sinks 3 and 3a are flat. Even if the heat sink 3 comes into contact with the circuit surface, the circuit surface is not covered with SiN or S.
Since it is protected by the passivation film made of iON, no performance problem occurs.
【0011】一般に、導電性のヒートシンクの方が、絶
縁性のヒートシンクより熱伝導性がよく、放熱効率がよ
いので、この点だけを考えれば、導電性のヒートシンク
を使用する方が望ましい。また、ヒートシンクを大型化
することによりさらに放熱性を良くすることができる。
しかし、大型の導電性ヒートシンクを用いると、ボンデ
ィングワイヤとの接触による電気特性の悪化が心配とな
る。そこで、本実施例では、導電性のヒートシンクでも
大型化ができるように、ボンディングワイヤ8を0.5
〜0.7μm厚のウレタン等の絶縁性材料で絶縁材料で
被覆している。このため、導電性のヒートシンクでもボ
ンディングワイヤ8と接触してもよく、ヒートシンクの
大型化が可能となり、放熱性をよくすることができる。In general, a conductive heat sink has better thermal conductivity and better heat dissipation efficiency than an insulating heat sink. Therefore, considering only this point, it is preferable to use a conductive heat sink. Further, the heat dissipation can be further improved by enlarging the heat sink.
However, when a large conductive heat sink is used, there is concern that the electrical characteristics may deteriorate due to contact with the bonding wire. Therefore, in the present embodiment, the bonding wire 8 is set to 0.5 so that the conductive heat sink can be increased in size.
It is covered with an insulating material such as urethane having a thickness of ˜0.7 μm. For this reason, even a conductive heat sink may come into contact with the bonding wire 8, the size of the heat sink can be increased, and heat dissipation can be improved.
【0012】図3を用いて、さらに詳しい説明をする
と、ボンディングワイヤ8は絶縁性の材料で被覆されて
いるので、ヒートシンク3とボンディングワイヤ8間の
距離tは、最悪、接触するまで小さくでき、ヒートシン
ク3の大型化を図ることができる。また、ヒートシンク
3とボンディングワイヤ8が多少接触しても電気特性に
影響しないので、実装および製造公差を縮めて製造する
ことができ、歩留まりの向上も実現できる。さらに、ヒ
ートシンクの材料にAlN、立方相窒化ほう素(CB
N)、ダイヤモンド等の絶縁物よりも安価なAlやCu
Wなどの導体の使用が可能になるので材料コストを下げ
ることができる。なお、電気的には、ヒートシンク3と
ボンディングワイヤ8が多少接触してもかまわないが、
機械的信頼性が低下しないように十分注意する必要があ
る。Explaining in more detail with reference to FIG. 3, since the bonding wire 8 is covered with an insulating material, the distance t between the heat sink 3 and the bonding wire 8 can be minimized until they come into contact with each other. It is possible to increase the size of the heat sink 3. Further, even if the heat sink 3 and the bonding wire 8 come into contact with each other to some extent, the electrical characteristics are not affected, so that the mounting and manufacturing tolerances can be reduced and the manufacturing can be performed, and the yield can be improved. Furthermore, AlN and cubic phase boron nitride (CB
N), Al and Cu that are cheaper than insulators such as diamond
Since it is possible to use a conductor such as W, the material cost can be reduced. In addition, electrically, it does not matter if the heat sink 3 and the bonding wire 8 are slightly in contact with each other,
Great care must be taken not to reduce the mechanical reliability.
【0013】本実施例に係るマルチチップモジュール
は、例えば、フェイスアップ型半導体チップ4およびフ
ェイスダウン型半導体チップ4aが搭載され、下部基板
1に固定された上部基板6の上面をキャップ2で内包す
る工程、ヒートシンク3,3aの一端をキャップ2の穿
孔7,7aに挿入し、その先端を半導体チップ4の上面
に接触させる工程、ヒートシンク3,3aとフェイスア
ップ型半導体チップ4およびフェイスダウン型半導体チ
ップ4aが接触した状態で、例えば、キャップの穿孔2
aとヒートシンク3,3aの隙間に半田を埋め込めるこ
とにより、ヒートシンク3,3aをキャップ2に固定す
る工程を経てパッケージ化される。In the multi-chip module according to this embodiment, for example, a face-up type semiconductor chip 4 and a face-down type semiconductor chip 4a are mounted, and an upper surface of an upper substrate 6 fixed to a lower substrate 1 is enclosed by a cap 2. Process: Inserting one end of the heat sink 3, 3a into the perforation 7, 7a of the cap 2 and bringing its tip into contact with the upper surface of the semiconductor chip 4, heat sink 3, 3a and face-up type semiconductor chip 4 and face-down type semiconductor chip With the 4a in contact, for example, the perforation 2 of the cap
By embedding solder in the gaps between a and the heat sinks 3 and 3a, the heat sinks 3 and 3a are fixed to the cap 2 to be packaged.
【0014】また、本実施例では、すべてのフェイスア
ップ型半導体チップ4にヒートシンク3を装着している
が、発熱量が大きい半導体チップに選択的に装着するこ
とができる。このように、ヒートシンクは1個の半導体
チップに対して1個装着されるので、基板面からの高さ
が異なる複数の半導体チップに対しても、確実にヒート
シンクを装着することができる。Further, in this embodiment, the heat sinks 3 are mounted on all the face-up type semiconductor chips 4, but they can be selectively mounted on the semiconductor chips which generate a large amount of heat. As described above, one heat sink is attached to one semiconductor chip, so that the heat sink can be surely attached to a plurality of semiconductor chips having different heights from the substrate surface.
【0015】[0015]
【発明の効果】本発明の構成によれば、フェイスアップ
で実装された半導体チップに個別にヒートシンクを装着
しているので、良好な放熱設計が可能で高速設計に支障
がなく、フェイスアップ実装方式の半導体チップの熱抵
抗の低減を図ることができる。According to the structure of the present invention, since the heat sinks are individually mounted on the semiconductor chips mounted face-up, good heat dissipation design is possible and high-speed design is not hindered. The thermal resistance of the semiconductor chip can be reduced.
【0016】さらに、フェイスアップで実装された半導
体チップと半導体基板を接続するボンディングワイヤを
絶縁性材料で被覆しているので、ボンディングワイヤと
ヒートシンクが接触しても電気特性は悪化しない。した
がって、ヒートシンクの大型化が実現でき、熱の放散性
が向上する。また、半導体チップモジュール製造におい
ても、導体が使い易くなるため、材料コストが安価にな
り、歩留まり向上のため生産コストも削減できる。しか
も、ヒートシンクは、選択的に1個の半導体チップに対
してそれぞれ装着することが可能なので、フェイスアッ
プ実装方式の半導体チップおよびフェイスダウン実装方
式の半導体チップが混在するマルチチップモジュールで
もフェイスアップ実装チップの熱抵抗の低減が可能にな
る。Further, since the bonding wire connecting the semiconductor chip mounted face up and the semiconductor substrate is covered with the insulating material, the electrical characteristics are not deteriorated even if the bonding wire and the heat sink come into contact with each other. Therefore, it is possible to increase the size of the heat sink and improve heat dissipation. Also, in the manufacturing of semiconductor chip modules, the conductors are easy to use, the material cost is low, and the production cost can be reduced because the yield is improved. Moreover, since the heat sink can be selectively attached to one semiconductor chip respectively, even in a multi-chip module in which face-up mounting type semiconductor chips and face-down mounting type semiconductor chips are mixed, face-up mounting chips are also included. It is possible to reduce the thermal resistance of the.
【図1】本実施例の半導体チップモジュールの斜視図。FIG. 1 is a perspective view of a semiconductor chip module of this embodiment.
【図2】本実施例の半導体チップモジュールの断面図。FIG. 2 is a cross-sectional view of the semiconductor chip module of this embodiment.
【図3】本発明を説明するための図。FIG. 3 is a diagram for explaining the present invention.
【図4】従来の方式を説明するための図。FIG. 4 is a diagram for explaining a conventional method.
1…下部基板 2…キャップ 3…大型ヒートシンク 3a…小型ヒートシンク 4…フェイスアップ型半導体チップ 4a…フェイスダウン型半導体チップ 5…リードピン 6…上部基板 7、7a…キャップの穿孔 8…絶縁性ボンディングワイヤ 8a…非絶縁性ボンディングワイヤ DESCRIPTION OF SYMBOLS 1 ... Lower substrate 2 ... Cap 3 ... Large heat sink 3a ... Small heat sink 4 ... Face-up type semiconductor chip 4a ... Face-down type semiconductor chip 5 ... Lead pin 6 ... Upper substrate 7, 7a ... Cap hole 8 ... Insulating bonding wire 8a … Non-insulating bonding wire
Claims (1)
1個または複数個の半導体チップと、 前記半導体チップの上面中央部に一端部が接触したヒー
トシンクと、 前記ヒートシンクの他端部を外部に露出させる孔が穿設
され、前記半導体チップを全て内包するキャップとを備
え、 前記半導体基板と前記半導体チップを接続するためのボ
ンディングワイヤが絶縁性材料で被覆されていることを
特徴とする半導体チップモジュール。1. A semiconductor substrate on which a wiring portion is formed, one or a plurality of semiconductor chips arranged on the wiring portion so that a circuit surface faces upward, and one end at a central portion of an upper surface of the semiconductor chip. A bonding wire for connecting the semiconductor substrate and the semiconductor chip, the heat sink being in contact with the semiconductor chip, and a cap having a hole for exposing the other end of the heat sink to the outside and including all the semiconductor chips. A semiconductor chip module, wherein the semiconductor chip module is covered with an insulating material.
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19956191A JPH0547974A (en) | 1991-08-08 | 1991-08-08 | Semiconductor chip module |
AU20775/92A AU657774B2 (en) | 1991-08-08 | 1992-08-04 | Semiconductor chip module and method for manufacturing the same |
EP19920113478 EP0528291A3 (en) | 1991-08-08 | 1992-08-07 | Semiconductor chip module and method for manufacturing the same |
CA002075593A CA2075593A1 (en) | 1991-08-08 | 1992-08-07 | Semiconductor chip module and method for manufacturing the same |
US08/232,346 US5525835A (en) | 1991-08-08 | 1994-04-22 | Semiconductor chip module having an electrically insulative thermally conductive thermal dissipator directly in contact with the semiconductor element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19956191A JPH0547974A (en) | 1991-08-08 | 1991-08-08 | Semiconductor chip module |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0547974A true JPH0547974A (en) | 1993-02-26 |
Family
ID=16409877
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19956191A Pending JPH0547974A (en) | 1991-08-08 | 1991-08-08 | Semiconductor chip module |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0547974A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001210767A (en) * | 1999-11-16 | 2001-08-03 | Matsushita Electric Ind Co Ltd | Heat sink |
JP2011187523A (en) * | 2010-03-05 | 2011-09-22 | Fujitsu Ltd | Liquid cooling unit |
-
1991
- 1991-08-08 JP JP19956191A patent/JPH0547974A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001210767A (en) * | 1999-11-16 | 2001-08-03 | Matsushita Electric Ind Co Ltd | Heat sink |
JP2011187523A (en) * | 2010-03-05 | 2011-09-22 | Fujitsu Ltd | Liquid cooling unit |
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