JPH0536930A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To provide a memory cell structure which can realize reduction in size to the same degree as SGT and sufficient cell storage capacity with the present process technology. CONSTITUTION:A groove is formed on the surface of a silicon substrate and a switching transistor defining two side surfaces facing with each other as the source and drain is formed on the upper part of a column-wise semiconductor layer 1 separated with the groove. A capacitor is formed with a storage node electrode 5 which is in contact with a side surface as a storage node contact 9 of these two side surfaces and is formed via an insulating film around the other side surface to surround the entire part of a column type semiconductor layer 1 and a plate electrode 6 which is formed via the capacitor insulating film 7 to surround this storage node electrode 5, a bit line contact 10 is formed at the side surface facing the side surface of the column type semiconductor layer forming the storage node contact 9, and moreover a word line 2 is formed on top of the column type semiconductor layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a dynamic RAM (DRAM).

[0002]

2. Description of the Related Art In recent years, semiconductor memory devices have been highly integrated and have a large capacity.
In a MOS dynamic RAM (DRAM) composed of individual MOS capacitors, research into miniaturization of the memory cell is progressing.

With the miniaturization of such memory cells, the area of the capacitor for storing information (charge) is reduced, and as a result, the memory contents are erroneously read out or destroyed by α rays or the like. There is a problem with software errors.

As a method for solving such a problem and achieving high integration and large capacity, the area occupied by the capacitor is substantially expanded, the capacity of the capacitor is increased, and the storage is increased without increasing the area occupied. Various methods have been proposed to increase the charge amount.

As one of them, as shown in FIG. 7, a gate electrode is formed on the outer periphery of a columnar semiconductor layer 100 formed by forming a groove in a semiconductor substrate via a gate insulating film, and the columnar semiconductor layer is formed. A MOS transistor (Surrounding Gate Gate Tr) in which source / drain diffusion layers 101s and 101d are formed on the upper surface and the groove bottom, respectively.
A vertical SGT cell is proposed in which a capacitor is formed between the columnar semiconductor layer and the plate electrode 102 embedded in the groove by using an anistor (hereinafter referred to as SGT) as a switching transistor. Here, the bit line is formed by forming a direct contact on the upper surface of the columnar semiconductor layer.

By laying out this SGT cell by the open bit line system, the cell size can be greatly reduced as compared with the conventional planar structure MOS transistor using the folded bit line system.

Ideally, the folded bit line method is used, and the cell size is 8F ² (F is a design rule in the plane) in the conventional planar MOSFET, whereas it is 4F ^{2 in the} SGT cell. It can be reduced to about half.

However, in the SGT cell, only four side surfaces of the silicon pillar can be used as a capacitor. Therefore, the effective area of the capacitor is only 4F.
There is only d (d is the depth of the groove), and in order to realize a sufficiently large cell storage capacity, the groove must be dug considerably deep. However, when digging a groove, the aspect ratio d / F is set to 10
The above process is difficult in terms of process technology, and there is a problem that a sufficient cell capacity cannot be obtained.

Further, since the bit line contact, which is the connecting portion between the bit line and the MOS transistor, is formed on the flat surface portion, the cell size is reduced to 6F ² (bit line running direction 3F × word line running direction) or less. There was a problem that I could not.

[0010]

As described above, while the conventional SGT cell laid out by the open bit line system can ideally reduce the cell size to 4F ² , it has a sufficient cell capacity in the current process technology. There was a problem that I could not get it.

The present invention has been made in view of the above circumstances, and provides a memory cell structure that can be made as small as an SGT and that can realize a sufficient cell storage capacity by using the current process technology. The purpose is to do.

[0012]

In view of the above, according to the first aspect of the present invention, a groove is formed on the surface of a semiconductor substrate, and the two side surfaces facing each other are formed on the upper surface of the columnar semiconductor layer separated by the groove. A switching transistor is formed, and one of these two side surfaces is used as a storage node contact, and the storage transistor is formed around the other side surface via an insulating film so as to surround the entire columnar semiconductor layer. A capacitor is formed by a node electrode and a plate electrode formed so as to surround the storage node electrode via a capacitor insulating film, and a bit is formed on a side surface of the columnar semiconductor layer forming the storage node contact. A line contact is formed, and a word line is formed on the top surface of the columnar semiconductor layer. That.

In the second aspect of the present invention, a groove is formed on the surface of the silicon substrate, and the aspect ratio of the grooves separated by the groove is 1 :.
The columnar semiconductor layer of No. 1 is further separated by forming an insulating film along the running direction of the bit line, and at least the surface of the columnar semiconductor layer formed by this separation has a first high concentration having a first conductivity type from below. Layer, a columnar semiconductor layer having the second conductivity type is divided into three by forming a second high concentration layer having the first conductivity type from above, and between the first and second high concentration layers. A gate electrode is formed on the three side surfaces of the columnar semiconductor layer located on the side of the gate insulating film via a gate insulating film, and a MOSFET having the region as a channel and the first and second high-concentration layers as the source and drain is formed on the lower side. Capacitors are formed on the three side surfaces of the first high-concentration layer located, and bit lines are formed so as to contact the three side surfaces of the second high-concentration layer located on the upper side and the top surface of the columnar semiconductor layer. There is.

[0014]

According to the first structure described above, the upper portion of the trench is used as a MOSFET, but the storage node electrode is formed around this portion through the insulating film, and the capacitor is formed all around the columnar semiconductor layer. Since it is formed, the capacitor can be formed on the outer four side surfaces of the columnar semiconductor layer while maintaining the cell area at 4F ² .

Assuming that the plate electrode can ideally be thinned to near zero, the effective area of the capacitor portion is SGT.
Can be increased to 8 Fd.

Therefore, it is possible to obtain a sufficient capacitance of the capacitor without making the groove deep, and it is possible to realize a sufficient storage capacitance with the current process technology.

According to the second structure, it is possible to form two memory cells, which is twice the size of the SGT cell, in the columnar semiconductor layer having an aspect ratio of 1: 1 and the bit line contact is SG.
Unlike the T cell, since it is mainly formed on the side surface of the columnar semiconductor layer, the rate of the memory cell area is not limited.
Therefore, the cell size can be reduced to about 2F ² which is about half the size of the SGT cell.

Preferably, a so-called SOI structure in which an insulating film is formed on the surface of the substrate and cells are formed on the insulating film is used to completely separate the insulating film from the substrate.

[0019]

Embodiments of the present invention will now be described in detail with reference to the drawings.

Example 1 As a first example of the semiconductor memory device of the present invention, FIG.
(a), FIG. 1 (b) and FIG. 1 (c) show the SGT structure DRAM.
The top view which shows, the AA sectional drawing and its BB sectional drawing are shown.

In this DRAM, grooves running in the vertical and horizontal directions on the surface of a p-type silicon substrate are arranged, and a plurality of columnar semiconductor layers separated by the grooves are arranged in a matrix. MOSFETs as switching transistors having two side surfaces facing each other as source / drain regions 1s and 1d made of n-type diffusion layers, and these 2
A storage node electrode 5 is formed by contacting one of the side faces as a storage node contact 9 and surrounding the other side face via a silicon oxide film 4 so as to surround the entire columnar semiconductor layer 1, and further the storage node electrode 5. A capacitor composed of a plate electrode 6 formed via a capacitor insulating film 7 so as to surround the node electrode is formed, and a bit line contact 10 is formed on a side surface of the columnar semiconductor layer 1 forming the storage node contact 9 opposite to a side surface thereof. And the word line 2 is formed on the top surface of the columnar semiconductor layer.

A bit line 3 is formed in the uppermost layer so that the bit line contact 10 formed on the side surface of the columnar semiconductor layer is connected to the contact pad 8 connecting over two adjacent cells.

Here, the storage node electrode 5 and the plate electrode 6 are made of a polycrystalline silicon film, and the capacitor insulating film 7 is made of a two-layer film of a silicon oxide film and a silicon nitride film.

The contact pads 8 for connecting the word lines and bit lines 3 which are the gate electrodes constituting the MOSFET and the source / drain regions 1d of the MOSFET are also made of polycrystalline silicon.

Further, as shown in FIG. 1 (a), the plate electrodes 6 are continuously arranged along the separation groove to serve as a common electrode.

In addition, a gate electrode 2 made of a polycrystalline silicon film is formed on the top surface of each columnar semiconductor layer 1 above the element isolation trench via a gate insulating film 4g, and each columnar semiconductor layer 1 is formed. N-type layers 1s and 1d serving as a source or a drain are formed on the two side surfaces facing each other, forming a MOS transistor.

A storage node electrode 5 is formed around each columnar semiconductor layer 1 with an insulating film 4 interposed therebetween.
The entire side surface is used as a capacitor.

Further, the word line 2 as a gate electrode runs in a direction perpendicular to the bit line 3.

Then, the upper layer of the word line is flattened by the insulating film 11 made of a silicon oxide film formed by the CVD method, and is connected to the source or drain 1d of the MOS transistor through the contact pad 8.
A bit line 3 made of a polycrystalline silicon film or the like is provided.

According to this structure, the bit line contact is formed above the capacitor, and the bit line is shared by the two cells adjacent in the running direction of the bit line. The connection portion between the bit line and the switching transistor, which has been a problem in the conventional SGT cell structure, does not contribute to the increase of the memory cell area, and the cell length in the bit line direction is the gate length F + the groove width F. The size can be reduced to 2F.

Further, according to this structure, the length of one side surface that can be used as a capacitor can be ideally set to 2F which is twice as large as that of the SGT cell structure. The depth should be about half, which is sufficient for the current process.

Next, the manufacturing process of this DRAM will be described.

First, by vertically and horizontally forming grooves on the surface of the p-type silicon substrate 1 having a specific resistance of about 5 Ωcm by anisotropic etching through a trench mask consisting of a two-layer film of a silicon nitride film and a silicon oxide film. Columnar semiconductor layer 1
Is formed, and a film thickness of 80 nm is formed around it by thermal oxidation.
The silicon oxide film 4 is formed, and the storage node contact 9 is formed on the silicon oxide film 4 by the photolithography method.

After that, the trench mask is removed, and polycrystalline silicon with a film thickness of about 50 nm is deposited by the CVD method.
By ion implantation or phosphorus diffusion of arsenic or phosphorus,
Doping is performed to form the storage node electrode 5. At this time, an n-type diffusion layer is formed in the region of the side wall of the trench which is in contact with the substrate.

Then, the capacitor insulating film 7 consisting of a two-layer film of a silicon nitride film / a silicon oxide film and a polycrystalline silicon film are embedded, and the plate electrode 6 is patterned.

Thus, the MOS capacitor utilizing the groove is formed, and subsequently, the MOS transistor is formed by the usual method.

First, a gate insulating film 4g made of a thermal oxide film having a thickness of about 15 nm is formed, a polycrystalline silicon film to be the gate electrode 2 is further deposited, and then a photoresist is formed in the groove region along the word line direction. -Form a pattern. Then, by using this photoresist pattern as a mask, reactive ion etching is performed to form a pattern to form the gate electrode 2 to be a word line.

Thereafter, the surface of the substrate is exposed by the usual photolithography method and reactive ion etching method, and arsenic is ion-implanted to form n-type layers 1s and 1d to be the source or drain of the MOS transistor. .

Then, the entire surface is covered with an interlayer insulating film 11 made of a silicon oxide film formed by the CVD method.

Then, a bit line contact 10 is formed by photolithography, and a contact pad 8 is formed. Finally, the bit line 3 is formed, and a protective film is formed if necessary, so that the DRAM shown in FIGS. 1A to 1C is completed.

Embodiment 2 In Embodiment 1, since the capacitor is formed over the entire depth of the groove, the contact pad 8 is formed in a mountain shape over the adjacent cells, and the bit line contact is slightly formed. Although it is difficult, if the capacitor is formed by leaving the upper part of the groove as shown in FIG. 2 as the second embodiment, the bit line contact can be easily formed and the concave portion formed on the capacitor can be formed. The contact pad 8 can be formed to be embedded.

Third Embodiment Although the bit line is formed through the contact pad 8 in the first embodiment, as shown in FIG. 3 as the third embodiment, the n-type layer 1d which directly constitutes the source / drain region of the MOSFET is formed. You may make it connect.

Fourth Embodiment Next, as a fourth embodiment of the semiconductor memory device of the present invention, a DRA having an SGT structure is shown in FIGS. 4 (a), 4 (b) and 4 (c).
The top view which shows M, the AA sectional view and its BB sectional view are shown.

In this DRAM, a groove is formed on the surface of a silicon substrate, and a p-type columnar semiconductor layer 1 having an aspect ratio of 1: 1 separated by the groove is formed with a silicon oxide film 14 along a running direction of a bit line. Further separated by forming,
An n-type layer 19 and an n + layer 20 are formed below and above the columnar semiconductor layer formed by this separation, and a gate electrode 2 is formed so as to cover three side surfaces of the columnar semiconductor layer 1 with a gate insulating film 4g interposed therebetween. The p in the middle of the columnar semiconductor layer 1
A MOSFET having the n-type layer 19 and the n + layer 20 as a source / drain is formed with the n-type layer 1p as a channel, and a capacitor having the n-type layer 19 as a storage node is formed on three side surfaces of the n-type layer 19 located on the lower side. The bit line 3 is formed so as to be in contact with the three side surfaces of the n + layer 20 located above and the top surface of the columnar semiconductor layer.

The capacitor uses the n-type layer 19 as a storage node, and has a capacitor insulating film 7 formed on the three side surfaces of the two-layer film of a silicon oxide film and a silicon nitride film,
It is composed of a plate electrode 6 made of a polycrystalline silicon film, and the plate electrode 6 is continuously arranged along the separation groove as shown in FIG. 4 (a) to become a common electrode.

Further, the word line 2 as a gate electrode runs in a direction perpendicular to the bit line 3.

With this structure, the cell size can be reduced to 2F ^2, which is half the size of the SGT cell.

The substrate of this MOSFET has a thickness F /
Since there is only 2 weak layers, when an n-layer serving as a storage node is formed, it is separated from the p-type substrate (or p-type epitaxial layer) S to form a floating substrate type transistor.

Further, the area of the bit line contact can be increased so that not only the top surface of the columnar semiconductor layer but also three side surfaces can be added, and the height of the columnar semiconductor layer can be adjusted. , Regardless of the memory cell size, the area of the bit line contact is
Can be greater than ² . The contact resistance of this bit line contact is proportional to its contact area,
Considering that the resistance value directly affects the reading time of the memory cell, the cell structure of the present invention can further increase the speed.

In this example, since the cell size in the running direction of the bit line is half that of the SGT cell, the word line pitch is twice as severe as that of the SGT cell.

Therefore, row decoders for selecting word lines are arranged every other word line so as to face the cell array, and the transistors forming the row decoder are not ordinary transistors but transistors of SGT structure. It is good to deal with the increase of.

Example 5 In Example 4, the n − -type layer serving as a storage node was formed over the entire thickness of the columnar semiconductor layer. However, as Example 5 shown in FIG. It may be connected to the substrate.

Embodiment 6 In Embodiments 4 and 5, the columnar semiconductor layer is formed directly on the p substrate or the p type epitaxial layer, but a so-called SOI structure is formed via the insulating film 24. It may be formed in.

This makes it possible to completely separate the substrate potential.

[0055]

As described above, the first aspect of the present invention
According to the cell structure (1), a memory having a large storage capacity can be realized without increasing the cell size. Further, since a memory having a large storage capacity can be realized without making the groove deep, a memory having a sufficient storage capacity can be formed even by using the current process. Furthermore, since the storage node is formed only on a part of the side surface, it has a structure that is more resistant to soft errors, pauses, etc. as compared to a normal SGT cell.

According to the second cell structure of the present invention,
SG with a small S factor and a small substrate bias effect
The cell size can be reduced to about 2F ² which is about half the size of the SGT cell without losing the electrical characteristics of the T cell structure. In addition, since the area of the bit line contact can be increased, the reading speed can be increased.

[Brief description of drawings]

FIG. 1 is a diagram showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a semiconductor device according to a third embodiment of the present invention.

FIG. 4 is a diagram showing a semiconductor device according to a fourth embodiment of the present invention.

FIG. 5 is a diagram showing a semiconductor device according to a fifth embodiment of the present invention.

FIG. 6 is a diagram showing a semiconductor device according to a sixth embodiment of the present invention.

FIG. 7 is a diagram showing a conventional semiconductor device having an SGT cell structure.

[Explanation of symbols]

1 Columnar semiconductor layer 2 word lines 3 bit lines 4g gate insulation film 4 Silicon oxide film 5 Storage node electrode 6 plate electrode 7 Capacitor insulation film 8 contact pads 9 Storage node contact 10 bit line contact 11 Insulating film 14 Silicon oxide film 19 n-type layer 20 n + type layer 24 Insulating film

Claims (2)

[Claims] 1. A vertical and horizontal groove is formed on the surface of a substrate of one conductivity type, and a columnar semiconductor layer separated by the groove and two side surfaces of the upper portion of the columnar semiconductor layer facing each other are formed as a source.
A MOSFET serving as a drain region, one of the two side faces serving as a storage node contact for contacting one of the source drain regions, and an insulating film surrounding the other side face so as to surround the entire columnar semiconductor layer. A capacitor composed of a formed storage node electrode and a plate electrode further formed via a capacitor insulating film so as to surround the storage node electrode, and a bit line contact formed on the remaining one side surface of the two side surfaces. And a word line formed on the top surface of the columnar semiconductor layer. 2. A vertical and horizontal groove is formed on the surface of a substrate of one conductivity type, and a columnar semiconductor layer separated by the groove is formed in the middle of the columnar semiconductor layer along the running direction of the bit line. An insulating film separating the semiconductor layer into two, a first high-concentration layer having a first conductivity type formed on at least the lower surface of the semi-columnar semiconductor layer formed by this separation, and a first high concentration layer formed on the upper surface. Second having a conductivity type of 1
Of the semi-columnar semiconductor layer located between them as a source / drain, and a MOSFET composed of a gate electrode formed through a gate insulating film on the three side surfaces, and the first layer located on the lower side. A storage node is formed on three side surfaces of the high-concentration layer, and a capacitor including a capacitor insulating film and a plate electrode sequentially formed on the storage node and three side surfaces of a second high-concentration layer located above the semi-columnar semiconductor layer and A semiconductor memory device comprising: a bit line formed so as to contact a top surface of a columnar semiconductor layer.