JPS6317553A - Semiconductor memory storage and its manufacture - Google Patents

Abstract

PURPOSE:To obtain a memory cell having fine structure by forming not only a capacitor for the memory cell but also a memory transistor on the side surface of a columnar region in a semiconductor substrate. CONSTITUTION:A drain in an N-type diffusion layer 3 connected to a wiring 10 for a bit line is shaped onto an silicon substrate 1a in a columnar region in a P-type silicon substrate 1 through an insulating film 2, and a P-type semiconductor layer 5 connected to the silicon substrate 1a so as to surround the upper side surface of the silicon substrate 1a and connected to the drain in the diffusion layer 3 through a P-N junction is formed. An N-type diffusion layer 6 combining a capacity electrode constituting a capacitor for a memory cell through dielectric films 4 between semiconductor substrates 1a and 1d and a source connected between the diffusion layer 6 and the semiconductor layer 5 through a P-N junction is shaped, and a gate 8 is formed onto the side surface of the semiconductor layer 5 so as to surround the silicon substrate 1a in the upper section of the columnar region through a gate insulating film 7. Accordingly, the fined memory cell can easily be acquired.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly to a semiconductor memory device including an insulated gate field effect transistor and a method of manufacturing the same.

[Conventional technology]

Semiconductor memory cells that store binary information in the form of charges have a small cell area, making them excellent as highly integrated and large-capacity memory cells. In particular, a memory cell consisting of one transistor and one capacitor (hereinafter referred to as a one-transistor type memory cell) is important as a memory for highly integrated storage devices because it has few components and has a small memory cell area. . By the way, recently, the size of memory cells has been reduced due to higher integration of memory cells.

The area of a capacitive part in a one-transistor type memory cell structure is decreasing. Therefore, a decrease in the amount of storage charge due to a decrease in the area of the capacitor section causes problems such as resistance to alpha particles and insufficient sensitivity of the sense amplifier.

Conventionally, in order to solve such problems, the following method has been known as a method of forming a large storage capacity section despite the reduction of the memory cell area.

FIG. 3 is a schematic cross-sectional view of an example of a conventional semiconductor memory device. For example, the International Conference on Solid State Devices (In-teroat
ional Electron Devices Me
eting) 1982, pages 806-808, “
A Corrugated Capacitor Cell for Megabit Dynamic Moss Memories” (^Co
rrugated Ca-pacitor Ce1l
(CCC) For Megabit Dyna,mi
In a paper published under the title MOSMe+5orics), a groove-type one-transistor memory cell in which the capacitive part of the memory cell is buried in a semiconductor substrate is proposed, as shown in FIG.

In FIG. 3, the capacitor electrode 12 forms a capacitor with a dielectric film 4' sandwiched between it and the inversion layer 6'', and charges are accumulated in the inversion layer 6''. The memory transistor whose gate 8' is connected to the word line controls charge movement between the diffusion layer 3' connected to the bit line and the diffusion layer 6' connected to the inversion layer 6''. , the insulating film 9' is an insulating film for isolation from other adjacent memory cells.The trench-type one-transistor memory cell shown in FIG. Semiconductor substrate 1'
By making the grooves deep enough, it is possible to secure a large capacity.

[Problem that the invention seeks to solve]

However, in the conventional trench type memory cell structure, since the memory transistor is formed on the surface of the semiconductor substrate, a planar area of the memory transistor is still necessary. This increase in planar area due to the memory transistor is a major barrier to miniaturization of the memory cell area as memory integration becomes higher. In trench type one-transistor type memory cells, efforts are being made to miniaturize the memory transistors and to miniaturize the memory cell area. However, miniaturization of memory transistors has the disadvantage that hot electrons cause deterioration of transistor characteristics, reducing reliability of memory cells. In addition, in the trench type one-transistor memory cell, since an inversion layer is formed on the side surface of the trench, the effective collision cross section of α rays increases, and soft errors are more likely to occur.

SUMMARY OF THE INVENTION An object of the present invention is to provide a highly reliable semiconductor memory device that is free from soft errors caused by alpha rays, etc., and that is suitable for high integration, and that has miniaturized memory cells, and a method for manufacturing the same.

[Means for solving problems]

The semiconductor memory device of the present invention includes an upper part of a columnar region of the semiconductor substrate surrounded by a first groove of a predetermined depth provided in the surface of a semiconductor substrate of one conductivity type, and along an upper side surface of the columnar region. A lower part of the columnar region of the semiconductor substrate surrounded by a second groove having a predetermined depth narrower than the width of the first groove provided on the bottom surface of the first groove, and an upper surface of the columnar region. a diffusion layer of the opposite conductivity type provided through an insulating film, and an upper part of the columnar region leaving a window opening opening in a strip shape with a predetermined width around the upper side surface of the columnar region directly under the insulating film. and a dielectric film covering a lower side surface and a side surface and a bottom surface of the second groove, and a dielectric film covering the side surface of the window and the insulating film, surrounding the upper side surface of the columnar region with a predetermined width, and transmitting the semiconductor through the window. a semiconductor layer of one conductivity type connected to the substrate and connected to the diffusion layer via a PN junction; and a gate that covers the side surface of the semiconductor layer via a gate insulating film and surrounds the upper side surface of the columnar region with a predetermined width.

The method for manufacturing a semiconductor memory device of the present invention includes the steps of sequentially forming an insulating film and a first impurity layer of an opposite conductivity type on the surface of a semiconductor substrate of one conductivity type, and forming the first impurity layer in a predetermined pattern. , a step of sequentially removing the insulating film and the semiconductor substrate to form a columnar region of the semiconductor substrate in which the insulating film and the first impurity layer are laminated on the upper surface surrounded by a groove of a predetermined depth; and forming a first dielectric band film selectively on the side surface of the columnar region and the bottom surface of the groove by opening a window that goes around the upper side surface of the columnar region directly under the insulating film in a band shape with a predetermined width. forming a semiconductor layer of one conductivity type over the entire surface of the semiconductor substrate; and selectively introducing impurities of the opposite conductivity type into a predetermined portion of the semiconductor layer lower than the window to form a semiconductor layer of the opposite conductivity type. forming a second impurity layer on a side surface of the columnar region, the insulating film, and the first impurity layer;
removing the semiconductor layer on the upper surface of the columnar region, the second impurity layer and the first dielectric film on the bottom surface of the groove, leaving an impurity layer of the first semiconductor layer; and introducing a high concentration impurity of the opposite conductivity type into the upper surface of the first impurity layer to form a region layer of the opposite conductivity type on the insulating film, and selectively introducing a second impurity into the side surface of the second impurity layer. forming a dielectric film of one conductivity type in the groove from the surface of the semiconductor substrate at the bottom of the groove to a predetermined height lower than the junction surface between the second impurity layer and the semiconductor layer; forming a capacitor using the second impurity layer surrounded by the first and second dielectric films as a capacitance electrode; and selectively forming another insulating layer on the upper surface of the semiconductor region. a step of forming a gate insulating film on a side surface of the semiconductor layer; and a step of forming a gate that covers the side surface of the semiconductor layer via a gate insulating film and surrounds the side surface of the columnar region with a predetermined width. It consists of a process.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a), 1(b) and 1(c) are a plan view, a sectional view taken along the line AA, and a sectional view taken along the line BB, respectively, of an embodiment of the semiconductor memory device of the present invention.

In this embodiment, an N
The drain of the diffusion layer 3 of the mold is provided through the insulating film 2, and connected to the silicon substrate 1a so as to surround the upper side surface of the silicon substrate 1a in the columnar region, and connected to the drain of the diffusion layer 3 through a PN junction. A type semiconductor layer 5 is provided between the semiconductor substrates 1a and 1b, and a dielectric film 4 is interposed between the semiconductor layer 5 and a capacitive electrode constituting the capacitor of the memory cell.
An N-type diffusion layer 6 that also serves as a source is provided, which is connected via an N junction, and a gate 8 is provided on the side surface of the semiconductor layer 5 so as to surround the silicon substrate 1a above the columnar region with a gate insulating film 7 interposed therebetween. It has a similar structure. Moreover, this gate 8
As shown in the figure (a>), a word line is also formed by common connection in the row direction (horizontal direction).

That is, in this embodiment, since not only the capacitor of the memory cell but also the memory transistor is provided on the side surface of the silicon substrate in the columnar region, it is possible to easily obtain a more miniaturized memory cell.

FIGS. 2(a) to 2(a) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the method for manufacturing a semiconductor memory device of the present invention.

In this embodiment, as shown in FIG. 2(a), first, a thick oxide film 2 and a polycrystalline silicon film 3a containing N-type impurities are sequentially formed on a P-type silicon substrate 1, and then A photoresist film 11a for forming columnar regions is left in a predetermined pattern.

Next, as shown in FIG. 2(b), the photoresist film 11
Using a as an etching mask, polycrystalline silicon film 3a is
, the oxide film 2 and the silicon substrate 1 are sequentially etched away by an anisotropic etching method to form a silicon substrate 1a in a columnar region, and then the photoresist film 11a is removed and the silicon substrate 1a in a columnar region is removed by a thermal oxidation method. A dielectric film 4a, which is a silicon oxide film, and an insulating film 4a' are formed on the surface and the surface of the polycrystalline silicon film 3a.

Next, as shown in FIG. 2(c), after coating the entire surface of the wafer with photoresist to fill the grooves in the silicon substrate 1, the photoresist film surface is etched onto the surface of the silicon substrate 1a in the columnar region using an anisotropic etching technique. A photoresist film 11b is formed by etching so as to be below the position, and then, using this photoresist film 11b as an etching mask, the dielectric film 4a on the upper side of the silicon substrate 1a in the columnar region is etched away. Then, a window is formed that goes around the upper part of the silicon substrate, and the insulating film 4a' on the surface of the polycrystalline silicon layer 3a is also removed.

Next, as shown in the 21st Z(d>), the photoresist film 1
After removing the semiconductor layer 1b, a thin polycrystalline silicon film semiconductor layer 5 is formed on the entire surface of the wafer, and then heat treatment is performed to remove the thin polycrystalline silicon film of the semiconductor layer near the window on the top of the silicon substrate 1a at least in the columnar region. The film is made into a single crystal, and an insulating film 9a containing N-type impurities is formed on the entire surface of the wafer, and then photoresist is applied to the entire surface of the wafer to fill the grooves in the silicon substrate. A photoresist film 11c is formed by etching so that the photoresist film 11c is located under the columnar region of the silicon substrate 1a.

Next, as shown in FIG. 2(e), the photoresist film 11
After etching the insulating film 9a containing n-type impurities using etching mask c as an etching mask, the photoresist film 11c is removed, and then heat treatment is performed to remove the n-type impurities from the insulating film 9a into the thin polycrystalline silicon film of the semiconductor layer 5. It diffuses into the interior to form a diffusion layer 6.

Next, as shown in FIG. 2 (f>), after removing the insulating film 9a by etching, the thin polycrystalline silicon films of the semiconductor layer 5 and the diffusion layer 6 are selectively etched using an anisotropic etching technique. The thin polycrystalline silicon film of the semiconductor layer 5 and the diffusion layer 6 is left only on the side surface of the silicon substrate 1a in the columnar region.
Subsequently, silicon substrate 1 is etched using anisotropic etching technology.
Only the dielectric film 4a formed at the bottom of the groove is etched away.

Next, as shown in FIG. 2 (g>), after coating the entire surface of the wafer with photoresist to fill the grooves in the silicon substrate, anisotropic etching techniques are used to align the surface of the photoresist film to the surface position of the polycrystalline silicon film 3a. A photoresist film lid is formed by etching so as to be lower than the polycrystalline silicon film 3a and the upper surface of the thin polycrystalline silicon film semiconductor layer 5a by ion implantation using this photoresist film lid as a mask. By implanting N-type impurities of
A mold diffusion layer 3 is formed.

Next, as shown in FIG. 2 (h>), a photoresist film li
After removing d, the entire surface of the wafer is oxidized by a thermal oxidation method to form a dielectric film 4b and an insulating film 7a, as well as a polycrystalline silicon film 3a and a semiconductor layer 5 of a thin polycrystalline silicon film.
Because a high concentration of N-type impurity is implanted into the upper surface of the insulating film 9b and the diffusion layer on the insulating film 2, which is thicker than other regions, enhanced oxidation and diffusion of the n-type impurity occur during thermal oxidation. 3 is formed.

Next, as shown in FIG. 2(i), only the dielectric M4b formed at the bottom of the groove of the silicon substrate 1 is etched away using an anisotropic etching technique, and then the silicon substrate 1 is etched using a selective epitaxial growth technique. P from the bottom of the groove
A silicon substrate 1b containing type impurities is formed. The height of this silicon substrate 1b is such that its surface is below the position of the PN junction surface between the diffusion layer 6 and the semiconductor layer 5.

Next, as shown in FIG. 2 (j), after removing the insulating film 7a formed on the upper side surface of the semiconductor layer 5 by etching, the semiconductor layer 5 and the silicon substrate 1b are removed by thermal oxidation again.
A gate insulating film 7 and an insulating film 9c are respectively formed on the surfaces of the gate insulating film 7 and the insulating film 9c.

Next, as shown in FIG. This polycrystalline silicon film is etched using an etching technique to form a gate 8 around the silicon substrate 1a in the columnar region.

Next, as shown in FIG. 2(e), an insulating layer is placed over the entire surface of the wafer so as to fill the grooves in the silicon substrate 1 and make the surface flat.
9, a contact window is formed on the diffusion layer 3 containing N-type impurities, and then an aluminum wiring 10 is grown and patterned. Thus, Figure 1 (
The semiconductor memory devices of the present invention shown in a), (b) and (c) are obtained.

〔Effect of the invention〕

As described in detail above, in the present invention, not only the capacitor of the memory cell but also the memory transistor is formed on the side surface of the columnar region of the semiconductor substrate, so that a memory cell with a fine structure can be easily obtained. By increasing the height of the memory transistor, a memory transistor with a long channel length can be easily formed, thereby eliminating the problem of hot electrons and improving the reliability of the memory cell. Furthermore, by using a memory transistor with a long channel length, it is possible to easily secure sufficient accumulated charge without lowering the power supply voltage.Furthermore, since the charge accumulation part is surrounded by an insulating film, softness caused by alpha rays can be easily secured. It also has the effect of preventing errors.

[Brief explanation of drawings]

FIGS. 1(a), (b) and (c) are a plan view, a cross-sectional view along the line A-A and a cross-sectional view along the line B-B, respectively, and FIG. ~<e> is a cross-sectional view of a semiconductor chip shown in the order of steps for explaining an embodiment of the method for manufacturing a semiconductor memory device of the present invention, and FIG. 3 is a schematic cross-sectional view of an example of a conventional semiconductor memory device. Yes. 1.1', la, lb...silicon substrate, 2...
Insulating film, 3.3'...Diffusion layer, 3a...Polycrystalline silicon film, 4.4', 4a--Dielectric film, 4a,', 4
b-Insulating film, 5... Semiconductor layer, 6, 6'... Diffusion layer, 6''... Inversion layer, 7... Gate insulating film, 7a...
・Insulating film, 8.8'--Gate, 9.9', 9a,
9b, 9c... Insulating film, 10... Wiring, lla,
llb, 11c, lid... photoresist film, 12.
...Capacitive electrode. (Tono((1”) Muf(1,/b Silicon five moxibustion, 2 extra colors and Hachi,
. 3. Kayagutsu Tsutsui, 4. Ritsudai 1, Se1 month 1.5 - half ■ Nobuan Suga Z Shuko Sanni, 7 Kate hat color season January ψ 3. δge°to 79 flower margin membrane, /θ track arrangement ￥51 surface

Claims (2)

[Claims] (1) The upper part of the columnar region of the semiconductor substrate surrounded by the first groove of a predetermined depth provided on the surface of the semiconductor substrate of one conductivity type, and the first groove along the upper side surface of the columnar region. An insulating film is formed on the lower part of the columnar region of the semiconductor substrate surrounded by a second groove having a predetermined depth narrower than the width of the first groove provided in the bottom surface of the semiconductor substrate, and on the upper surface of the columnar region. a diffusion layer of the opposite conductivity type provided through the insulating film, and the upper and lower side surfaces of the columnar region, leaving a window portion opening in a band shape with a predetermined width around the upper side surface of the columnar region directly under the insulating film. and a dielectric film covering side surfaces and bottom surfaces of the second groove, and a dielectric film covering the side surfaces of the window and the insulating film, surrounding the upper side surface of the columnar region with a predetermined width, and connecting to the semiconductor substrate through the window. and a semiconductor layer of one conductivity type connected to the diffusion layer via a PN junction, covering the dielectric film in such a manner as to bury the second groove and connecting to the lower surface of the semiconductor layer via a PN junction. 1. A semiconductor memory device comprising: a capacitor electrode of an opposite conductivity type; and a gate that covers the side surface of the semiconductor layer via a gate insulating film and surrounds the upper side surface of the columnar region with a predetermined width. (2) A step of sequentially forming an insulating film and a first impurity layer of an opposite conductivity type on the surface of a semiconductor substrate of one conductivity type, and forming the first impurity layer, the insulating film, and the semiconductor substrate in a predetermined pattern. forming a columnar region of the semiconductor substrate in which the insulating film and the first impurity layer are laminated on the upper surface surrounded by a groove of a predetermined depth by sequentially removing the insulating film; forming a first dielectric band film selectively on the side surface of the columnar region and the bottom surface of the groove by opening a window that goes around the upper side surface of the columnar region in a band shape with a predetermined width; and the surface of the semiconductor substrate. forming a semiconductor layer of one conductivity type over the entire semiconductor layer; and forming a second impurity layer of the opposite conductivity type by selectively introducing impurities of the opposite conductivity type into a predetermined portion of the semiconductor layer lower than the window; and forming the semiconductor layer on the upper surface of the columnar region while leaving the semiconductor layer on the side surface of the columnar region, the insulating film, and the first impurity layer, and the second impurity layer on the side surface of the columnar region. the second on the bottom surface of the groove;
a step of removing the impurity layer and the first dielectric film; and introducing high concentration impurities of opposite conductivity type into the upper surfaces of the first semiconductor layer and the first impurity layer so as to remove the impurity layer and the first dielectric film. forming a region layer of opposite conductivity type and selectively forming a second dielectric film on the side surface of the second impurity layer;
A part of the trench is filled with a semiconductor region of one conductivity type from the surface of the semiconductor substrate at the bottom of the trench to a predetermined height lower than the junction surface between the second impurity layer and the semiconductor layer. forming a capacitor using the second impurity layer surrounded by a second dielectric film as a capacitance electrode; selectively forming another insulating film on the upper surface of the semiconductor region; a step of forming a gate insulating film on the side surface of the semiconductor layer; and a step of forming a gate that covers the side surface of the semiconductor layer via a gate insulating film and surrounds the side surface of the columnar region with a predetermined width. A method for manufacturing a storage device.