JPS62193273A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To provide the titled memory with an excavated capacitor structure extremely resistant to any soft errors eliminating any deep grooves and facilitating the formation by a method wherein a capacitor electrode to be a memory node and an MOS transistor are formed on a semiconductor substrate through the intermediary of an insulating film. CONSTITUTION:Capacitor forming grooves 2 are formed on specified positions on a P-type silicon substrate 1 by reactive ion etching process and after forming a thermal oxide film and depositing a polycrystalline silicon film 4 to be etched, patterns are formed on multiple rectangular island regions. Later, the silicon film 4 is single crystallized and the part buried in the grooves 2 are doped with an impurity to form N<+> type layers as capacitor electrodes 5. Next, thermal oxide films as gate insulating films 6 are formed; the second polycrystalline silicon films are deposited; and after these films are pattern-formed to form gate electrodes 7, an N<+> type source region 81 and a drain region 82 are formed by ion implantation. Finally, a CVD insulating film 9 is deposited on overall surface to make a contact hole 11 forming an Al interconnection 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor memory device having one transistor/one capacitor memory cell structure.

(Prior Art) Conventionally, as a semiconductor memory device formed on a semiconductor substrate,
- MO3 type dynamic RAfvl (
(hereinafter abbreviated as dRAM) is known. This dR
In AM, information is stored depending on whether or not charge is accumulated in a MOS capacitor, and information is read out depending on whether or not a charge is accumulated in a MOS capacitor.
This is done by discharging the charge of the S capacitor to the bit line via a MOS transistor and detecting the potential change. Due to recent advances in semiconductor manufacturing technology, particularly advances in microfabrication technology, the capacity of dRAM is rapidly increasing. The biggest problem in increasing the capacity of dRAM is how to reduce the memory cell area while keeping the capacitor capacity large. The magnitude of potential change when reading information from dRAM is determined by the amount of charge accumulated in the MOS capacitor, and the minimum required amount of charge is determined by considering operational margin and soft error margin.

Since the amount of accumulated charge is determined by the capacitance of the MOS capacitor and the applied voltage, and the applied voltage is determined by the power supply voltage, it is necessary to ensure the MOS capacitor capacity as large as possible.

FIGS. 6(a) and 6(b) are a plan view and a sectional view taken along the line AA' of the conventional dRAM.

Capacitor insulation g! on p-type 3i substrate 21 with element isolation.
1st through 24! A capacitor electrode 23 made of an I polycrystalline silicon film is formed in common to all pits. A gate electrode 25 is formed in the window portion of the capacitor electrode 23 via a gate insulating film 24, and using this gate electrode 24 as a mask, n+ type layers 27 and 28 which will become a source and a drain are formed by diffusion. 26 is an n-type layer which becomes the substrate side electrode of the MOS capacitor. The gate electrode 25 is disposed continuously over the capacitor electrodes 23 of vertically adjacent memory cells, and serves as a word line. On the other hand, the sources of the MOS transistors are commonly connected in the horizontal direction by an An wiring 30, which becomes a bit line.

Two are interlayer insulating films.

In order to increase the size of the MOS capacitor in such a dRAM, it is necessary to reduce the thickness, increase the dielectric constant, or increase the area of the capacitor insulating film used. However, making the capacitor insulating film thinner has a limit in terms of reliability. To increase the dielectric constant, for example, it is possible to use a nitride film instead of DI oxide (Si021), but this also has problems mainly with reliability and is not practical. In order to achieve this, it is necessary to secure a large area for the MOS capacitor, and this is a major obstacle in reducing the memory cell area and achieving high integration of dRAM.

As a structure that increases the size of the MOS capacitor without increasing the area occupied by the memory cell, the MOS capacitor on the substrate
Dig a groove in the capacitor area and use the sidewalls of this groove to
A so-called grooved capacitor forming an OS capacitor has been proposed. This method is attracting attention as a promising method because it attempts to form a groove and utilize its sidewalls, whereas conventional methods only use the flat surface of the substrate.

(Problems to be Solved by the Invention) In the memory cells of conventionally proposed am rechargers, the substrate side serves as a storage node, and the capacitor electrode formed on the substrate serves as a so-called cell plate at a reference potential common to all bits (usually ground potential). This point is no different from the case of a planar capacitor. In this structure, charges generated in the substrate due to the incidence of alpha rays flow into the storage node, causing the storage information to disappear!・The error problem is not resolved. Therefore, in order to provide sufficient resistance to soft errors, the depth of the groove must be sufficiently deep to increase the area of the capacitor, which creates a limit in terms of manufacturing technology.

The present invention has been made in view of the above points, and has a grooved capacitor structure that is extremely resistant to soft errors, and therefore does not require very deep grooves and is easy to manufacture.
The purpose is to provide a

[Structure of the Invention] - (Means for Solving the Problems) In the semiconductor memory device according to the present invention, a storage node, a capacitor electrode, and a MOS transistor are formed on a semiconductor substrate with an insulating film interposed therebetween.

That is, a capacitor is constructed by embedding a capacitor electrode serving as a storage node in a groove formed in a semiconductor substrate via a capacitor insulating film, and using the substrate as a common electrode. Further, the MOS transistor is formed in a semiconductor layer formed continuously with the capacitor 1f pole on the substrate with an insulating film interposed therebetween.

(Function) According to the structure of the present invention, since the storage node and the MOS I-transistor, which are information charge storage sections, are all separated from the semiconductor substrate by an insulating film, the charges generated in the substrate due to the incidence of α rays are stored. It does not flow into the node, making it difficult to be influenced by external sources. Therefore, the amount of accumulated charge required is small, and the groove for the capacitor formed in the substrate can be made shallow. Therefore, it is easier to manufacture than the conventional groove grip capacitor structure. In addition, since the capacitor ftff1, which serves as a storage node, is obtained by patterning a semiconductor film deposited on a substrate, reliable element isolation by an insulating film is performed, and therefore, miniaturization of memory cells and
Larger capacity is possible.

(Example) The present invention will be explained in detail below.

FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along line AA' of the dRAM of the embodiment. 2 is formed in the capacitor formation region of the p-type silicon substrate 1, and this substrate 1
A small number of silicon films 4 are arranged in a rectangular island shape on top, with a thermal oxide film 3 serving as an M insulating film separating the capacitor insulating film and the N·10S transistor from the M plate. The portion of each silicon film 4 buried in the trench 2 serves as an n+ type capacitor voltage ti5. Also, n4 is placed adjacent to the capacitor electrode 5 of each island-like silicon film 4.
' type source region 81, similarly n+ type drain region 1a82. M consisting of a gate insulating film 6 and a gate electrode 7
OS) - transistors are formed. As shown in FIG. 1(a), the electrodes 1 to 7 are continuously disposed so as to cross each island-like silicon film 4 in one direction, and these serve as word lines. CV on the substrate with elements formed in this way
A2 wiring 10 is formed via D insulation [19].

The A2 wiring 10 is connected to the drain region 82 of the MOS transistor through the contact hole 11, and is continuously arranged in a direction intersecting the word line, and serves as a bit line.

FIGS. 2(a) to 2(e) are process cross-sectional views showing the manufacturing process of such a dRAM. To explain the manufacturing process using this, first, as shown in (a), a plurality of grooves 2 for forming capacitors are formed in a predetermined arrangement in a p-type silicon substrate 1 by using a reactive ion etching method. Next, as shown in (b), a thermal oxide film 3 of about 100 layers is formed to be used as a capacitor insulating film and as an isolation insulating film to separate the MOS transistor from the substrate. Deposit film 4. Next, as shown in (C), the silicon film 4 is etched through a known PEP process to form patterns into real rectangular island regions separated from each other. Each island-like silicon film is patterned so as to span two grooves 2, as shown in FIG. 1(a). Thereafter, each silicon film 4 is made into a single crystal by laser annealing. The portion of each silicon F14 buried in the groove 2 is doped with impurities to form an n+ type layer, and this is used as the capacitor electrode 5 as a storage node.

After that, as shown in (d), a gate insulating pIA6 made of a thermal oxide film is formed on each silicon film 4, a second polycrystalline silicon film is deposited, and this is patterned to form a gate electrode 7. do. Subsequently, an n+ type source region 81.degree. drain region 1a82 is formed by ion implantation. goo 1
- The electric wires 7 are continuously arranged across each island-like silicon film to form a word line. Finally, as shown in (e), a CVD insulating film 9 is deposited on the entire surface, and a contact 1-hole 11 is opened in this to form an A2 wiring 10 that will become a bit line.

In the structure of this embodiment, the group (1) is used as a reference electrode common to all memory cells, and the information charge is transferred to the MOS
It is accumulated in the capacitor electrode 5 embedded in each groove 2 via the transistor. Therefore, even if charges are generated within the substrate 1 due to the incidence of τα rays, etc., this will not flow into the capacitor electrode 5, which is the storage node of the memory cell, resulting in a dRAM that is highly resistant to soft errors. .

Furthermore, if the same level of resistance as the conventional one is sufficient, the depth of the capacitor can be made shallower, which is advantageous in terms of manufacturing technology. In addition, since adjacent memory cells are completely isolated by the insulating film, the II accumulated charge does not leak to adjacent memory cells, and cell isolation is ensured. As a result, the area occupied by the memory cell can be made sufficiently small, and a large capacity dRAM can be obtained.

In the above example, the silicon film on the substrate is completely separated from the substrate, but when a polycrystalline silicon film is made into a single crystal by laser annealing, a portion of the polycrystalline silicon film is partially attached to the single crystal silicon substrate. Better to stay in touch. This is because this contact portion becomes a nucleus for crystal growth. Real 11i has been designed with such considerations in mind as long as it does not affect the device characteristics! ! An example is explained below.

Figure 3 shows Figure 1 (b) of such an example of dRAM.
FIG. Portions corresponding to those in FIG. 1 are designated by the same reference numerals as in FIG. 1, and detailed description thereof will be omitted.

As is clear from the figure, in this embodiment, a hole 12 is opened in the oxide film 3 before depositing the silicon film 4 under the gate electrode 7 of the MOS transistor, and the silicon I
The IW4 is connected to the substrate 1.

According to this embodiment, the silicon 114 can be easily made into a high-quality single crystal by laser annealing, and therefore a switching MOS transistor with excellent characteristics can be obtained. The fact that the silicon film 4 is in contact with the substrate 1 under the gate electrode 7 means that
There is no adverse effect on the device characteristics; rather, since the substrate region of the MOS transistor is not floating but can be at a fixed potential together with the substrate 1, the advantage is that the characteristics can be stabilized.

FIG. 4 shows a dRAM of yet another embodiment. This embodiment differs from FIG. 3 in that a hole 13 is formed below the drain region 82 of the MOS transistor. In this case, n-type 1ii1 is formed on the surface of the substrate 1 under the drain region [8z
4 will be formed.

This embodiment also provides the same effects as the embodiment shown in FIG.

In the structure of the present invention, the capacitor bridge portion embedded in the trench and the silicon bridge portion for forming the MOS transistor may be formed in two stages. .

FIGS. 5(a) and 5(b) are cross-sectional views for explaining the manufacturing process of the dRAM of such an embodiment.

That is, as shown in FIG. 5(a), 1! After forming J3,
N-type silicon film 41 containing impurities at a high concentration only in groove 2
Embedded and formed. Next, as shown in Figure 5(b),
A silicon film 42 is deposited over the entire surface. After this, the dRAM can be manufactured using the same steps as in the previous embodiment. According to this embodiment, the resistance of the capacitor electrode embedded in the groove can be made sufficiently low.

In addition, the present invention can be implemented with various modifications without departing from the spirit thereof.

[Effects of the Invention] As described above, the present invention provides a dRAM that is highly resistant to soft errors, easy to manufacture, and has a large capacity.
can be realized.

[Brief explanation of drawings]

FIGS. 1(a) and 1(b) are a plan view and a cross-sectional view taken along line A-A' of the dRAM according to an embodiment of the present invention, and FIGS. 2(a) to (e)
) is a sectional view showing the manufacturing process, FIGS. 3 and 4 are sectional views showing dRAM of other embodiments, and FIGS.
) is a cross-sectional view showing the manufacturing process of dRA-1 of another embodiment, and FIGS. 6(a) and 6(b) are a plan view and an AA' cross-sectional view showing an example of a conventional dRAM. 1... P-type silicon substrate, 2... Groove, 3... Thermal oxidation 3Q (capacitor insulating film), 4... Silicon film,
5... N1 type capacitor electrode, 6... Gate insulating film, 7... Gate bridge, 81... N'' type source region,
82...n+ type drain region 9...CvD insulating film, 10...A°C wiring, 11...contact hole, 12.13...hole, 14...n type layer. Figure 2 Figure 3 Figure 4

Claims (4)

[Claims] (1) In a semiconductor memory device in which a memory cell consisting of one capacitor and one MOS transistor is integrated on a semiconductor substrate, the capacitor is connected to a capacitor electrode through a capacitor insulating film in a groove formed in the substrate. is embedded, and the MOS transistor is formed in a semiconductor film that is formed continuously with the capacitor electrode and whose entire or main part is separated from the substrate by an insulating film. A semiconductor memory device characterized by: (2) The capacitor electrode and the semiconductor film in the MOS transistor region continuous thereto are a silicon film formed integrally, and the capacitor insulating film and the insulating film under the semiconductor film in the MOS transistor region are thermally oxidized and formed at the same time. The semiconductor memory device according to claim 1, which is a film. (3) The capacitor electrode and the semiconductor film in the MOS transistor region continuous thereto are a silicon film formed integrally, and the capacitor insulating film and the insulating film under the semiconductor film in the MOS transistor region are thermally oxidized and formed at the same time. 2. The semiconductor memory device according to claim 1, wherein a hole is formed in the thermal oxide film under the semiconductor film in the MOS transistor region, and the semiconductor film is connected to the substrate at this portion. (4) At least a portion of the capacitor electrode is formed by filling the groove with a first silicon film, and the semiconductor film in the MOS transistor region is formed of a second silicon film overlapping with the first silicon film. A semiconductor memory device according to claim 1.