JPH05347554A - Cmos variable frequency divider circuit - Google Patents

Abstract

PURPOSE:To ensure a stable and high speed operation of a CMOS variable frequency divider circuit even with the power voltage of a low level by performing the odd division necessary for a variable frequency dividing operation and the division mode switching logical arithmetic by means of a static FF of a clocked inverter constitution. CONSTITUTION:When a division mode switching signal M is kept at a high level, the NAND logic of a D-FF (D type flip-flop) 2 is fixed at a high level with the NOR logic fixed at a low level respectively. Therefore the output level of the master FF element of the D-FF 2 does not change and is sent to a slave FF element. Then the output level is inverted and fed back to the NOR logic and the NAND logic of the master FF element a D-FF 1 respectively. As a result, an NMOS 5 and an NMOS 8 are turned on and off respectively and the D-FF 1 has a 2-division operation. Meanwhile the complementary output signal of the D-FF 1 is delayed by an extent equal to a single cycle of a clock signal and fed back via the D-FF 2 when the signal M is kept at a low level. Thus a 3-division operation waveform is secured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ultra-high speed CMOS variable frequency divider circuit (2-modulus prescaler) which operates in the GHz band, and particularly to a low power which is a constituent element of a frequency synthesizer used in an ultra-small mobile phone or the like. The present invention relates to a circuit configuration method suitable for an ultra-high speed prescaler (variable frequency division) IC.

[0002]

[Prior Art] With the development of information society,
Demand for mobile communication devices such as mobile phones is rapidly increasing. In order to reduce the size and weight of these mobile communication devices, it is most effective to reduce the battery volume and weight by reducing the circuit power consumption. In particular, high-speed operation is required, and there is a strong demand for lower power consumption of the prescaler IC in the frequency synthesizer, which accounts for most of the power consumption during standby.

On the other hand, due to the expansion of use of mobile communication,
The frequency band assigned to this application has become higher in frequency. That is, the conventional 800 MHz band, the 1.5 GHz band, and the 2.5 GHz band are planned. In response to these trends, there is an increasing demand for higher speeds of the above-mentioned prescaler circuit and the like.

Under these circumstances, the prescaler circuit is conventionally a GaAs-IC or a Si bipolar IC.
Was composed of. (Publication 1; Toshihiko Ichioka, et al .: "Low current consumption GaAs SCFL variable frequency divider" The Institute of Electronics, Information and Communication Engineers, ED88-65, 1988. The former case is reported, and publication 2; Shinji Saito, other:
"High-speed, low-voltage PLL frequency synthesizer LSI with built-in prescaler by Bi-CMOS technology" IEICE Technical Committee Report ICD88-69, 1988. The latter example is reported in. For this reason, in the frequency synthesizer, the prescaler section and the other low-frequency section composed of the CMOS are composed of separate chips. From the viewpoint of cost reduction and power consumption reduction of the system of the mobile communication device, it is desirable that the entire system be made into CMOS, but it is difficult for the conventional CMOS circuit to perform stable high-speed operation in the GHz band.

Therefore, the configuration and operation of the conventional prescaler circuit will be described first, and then the configuration technology of the conventional CMOS prescaler circuit will be reviewed.

FIG. 5 shows a block diagram of a 2-modulus prescaler circuit (÷ 2 / ÷ 3 variable frequency dividing circuit). D
Type flip-flop (hereinafter abbreviated as D-FF) 51,
52 and NOR logic gates 53 and 54. The NOR logic gate 53 performs a logical operation for performing odd frequency division, and the NOR logic gate 54 has a frequency division mode switching function. Conventionally, the NOR logic gate has a vertically stacked structure, and has a structure as shown by PMOS 56, 57 and NMOS 58, 59 in the figure, for example.
The operation will be briefly described. When the division mode switching signal M of the NOR logic gate 54 is H (high level), the output is L
Fixed (low level), the fixed signal is D-FF
Since the NOR logic gate 53 is input to the NOR logic gate 53 through 52, the NOR logic gate 53 operates as an inverter. As a result, the D-FF 51 becomes T-type coupling and performs ÷ 2 frequency dividing operation. On the other hand, when M is L (low level), D-FF
The output signal of 51 is further delayed by one clock by the D-FF 52 and fed back to the input of the NOR logic gate 53. In the NOR logic gate 53, the two input signals are both L
Only at the time of, H is output to obtain a ÷ 3 frequency division operation waveform. FIG. 6 shows time charts for the ÷ 2 frequency division and ÷ 3 frequency division operations described above. A, B, E and F in the figure correspond to the respective parts shown in FIG.

In addition to the block diagram shown in FIG.
A variable frequency divider circuit of ÷ 4 / ÷ 5 can be configured by adding one 5. The block diagram is shown in FIG. D-FF 51, 52, 55 and NOR logic gate 5
It is composed of 3, 54. The NOR logic gate 54 has a frequency division mode switching function. The operating principle is Figure 5
This is the same as the variable frequency dividing circuit described in. ÷ 4 and ÷
FIG. 8 shows a time chart at the time of the division by 5 operation. A, B, E and F in the figure correspond to the respective parts shown in FIG.

In the prior art, in constructing the prescaler circuit shown in FIGS. 5 and 7, a dynamic flip-flop (hereinafter abbreviated as FF) was adopted to realize high speed operation (known document 3; Kanizawa and others, "÷ 4 /
5 CMOS 2 modulus prescaler "1989
Annual Conference of IEICE Autumn Meeting C-124 5-
110). FIG. 9 is a circuit diagram when the variable frequency divider circuit of ÷ 2 / ÷ 3 shown in FIG. 5 is configured by a dynamic FF including a transfer gate (hereinafter referred to as TG). In the figure, the TGs 91 and 92 and the inverters 93 and 94 having the CMOS structure constitute the first stage D-FF1. The inverter 97 is a buffer for obtaining an inverted output,
The MOS 95 and the PMOS 96 are reset transistors for FF initialization. Similarly, TG98, 99,
Inverters 100 and 101 and NMOS 1 for reset
03 and the PMOS 102 constitute the FF2 in the subsequent stage. The inverter 104 generates a clock complementary signal. The operation is the same as the description using the block diagram of FIG. The timing chart during operation is the same as the changes shown in FIG. 5, and A, B, E, and F in the figure correspond to the symbols of the respective parts shown in FIG.

The maximum operating frequency of the variable frequency divider circuit of FIG.
It is determined by the delay time (Tpd) in the signal path of B → E → F → A during the frequency division operation by 3. Tpd is the delay (Tin) of the inverter 97 that generates the inverted output of the first stage D-FFI.
v), the delay (Tnor) in the NOR logic gate 4,
It is the sum of the data write delay (Tw) and the read delay (Tr) in the D-FF 2, and the delay (Tnor) in the NOR logic gate 3. Therefore, it becomes Tpd = Tinv + 2Tnor + Tw + Tr (Formula 1). Therefore, in order to speed up the variable frequency dividing circuit, it is essential to speed up the operation of the D-FF and the logic gate. In the conventional circuit of FIG. 9, a dynamic type FF is adopted to shorten Tw and Tr, thereby increasing the speed.

[0010]

However, in the conventional dynamic FF shown in FIG. 9, the stability of the operation is deteriorated due to the decrease of the frequency of the clock signal and the variation of the threshold value of the transistor due to the variation of the manufacturing process. There is a problem. That is, the D-FF in FIG.
In 1 and 2, the signal is held by the flip-flop element by combining the source-drain junction capacitance Cj of the TG 91 (or 92, 98, 99) and the gate capacitance Cg of the CMOS inverter 93 (or 94, 100, 101) in the next stage. This is done by the charges stored in the capacitor C (= Cj + Cg). However, the accumulated charge decreases with time due to leakage current in the source / drain junction and the gate oxide film and subthreshold leakage current, so the signal level held decreases as the signal cycle becomes longer, and finally the next stage Below the logical threshold of the inverter. As a result, the inverter at the next stage is inverted and malfunctions.

Further, the problem is that as the power supply voltage decreases, the load charging capability of the inverter decreases, so that the combined capacitance C
The amount of charge charged to (= Cj + Cg) decreases, and the operation margin decreases. Such a problem is caused not only by a dynamic FF composed of a TG but also by a dynamic FF composed of a clocked inverter (known document 4; Mon et al.,
"0.2 μm CMOS ultra-high-speed frequency divider" 1990 IEICE Spring National Convention Proceedings C-648 5-212)
Occurs for the same reason.

Further, when the power supply voltage is lowered, the operating speed and operating margin of the NOR logic gate are greatly deteriorated. Therefore, high-speed and stable operation can be expected with an electromotive force (0.9 to 1.6 V) of one dry cell. There wasn't.

Under such circumstances, G
There has been a demand for a CMOS variable frequency dividing circuit technology that operates in the Hz band and operates stably without depending on the operating frequency.

The problems of the conventional dynamic type CMOS variable frequency divider can be summarized into the following three points.

(1) The operational stability is greatly affected by variations in the threshold value of transistors due to process variations.

(2) The lower limit of the operating frequency range exists, and the stability at low frequencies is poor.

(3) As the power supply voltage decreases, the above (1)
Since the problems of (2) and (2) become serious, they are not suitable for low power supply voltage operation.

[0018]

The present invention has been made in order to meet such a demand, and is based on a clocked inverter excellent in high speed as a D-FF that determines the performance of a CMOS variable frequency divider circuit. A logic gate that adopts the configured static FF, and further incorporates the logical operation for performing the odd frequency division necessary for the variable frequency division operation and the logical operation for switching the frequency division mode into the FF element on the master side of the FF. The CMOS variable frequency divider circuit having a large operation margin even at a low power supply voltage and excellent in high speed is configured.

[0019]

Since the present invention is configured as described above, the stability of the operation is excellent even at a power supply voltage of about one electromotive force (0.9 to 1.6 V) of a dry cell, and the high speed operation in the GHz band is possible. It is possible to realize a possible CMOS variable frequency dividing circuit.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

[Embodiment 1] FIG. 1 shows a first embodiment of the present invention. In this embodiment, the circuit configuration of the present invention is shown in FIG.
An example when applied to a 2 / ÷ 3 variable frequency dividing circuit is shown. The flip-flop of the present invention is the D shown in FIG.
-Has both the function of FF and the function of NOR logic gate (53 or 54).

In FIG. 1, the first stage D-FF1 and the latter stage D-FF2 have the same circuit configuration. At first,
The circuit configuration of the master side flip-flop element of the first stage D-FF1 will be described.

The input / output terminal of the inverter 1 is connected to the input / output terminal of the inverter 2 to form a flip-flop element. The input terminal of the first inverter 1 is connected to the high-potential side power supply through the PMOS 3 driven by the clock signal, and the low voltage is inserted through the NMOS 4 and 5 connected in series and the NMOS 6 driven by the clock signal. Connect to the power supply on the potential side. This series-connected NMOS 4 and 5
Serves as a NAND logic gate for the input of the inverter 1.

The input terminal of the inverter 2 is connected to the high-potential side power source through the PMOS 9 and is connected in parallel.
The OS 7 and 8 and the NMOS 6 are inserted to connect to the low potential side power source. The NMOSs 7 and 8 connected in parallel serve as a NOR logic gate for the input of the inverter 2.

Next, the circuit configuration of the slave side flip-flop element of the first stage D-FF1 will be described. The input / output terminal of the inverter 10 is connected to the output / input terminal of the inverter 11 to form a flip-flop element.
12 whose input is driven by a clock signal
Connected to the power supply on the high potential side via the
And an NMOS 16 driven by a clock signal, and connected to the low potential side power source, and the input terminal of the inverter 11 is connected to P
Connected to the high-potential side power source through the MOS14, and N
It is connected to the low-potential-side power supply via the MOS 15 and the NMOS 16.

The output terminal of the inverter 2 and the output terminal of the inverter 1 which are the output terminals of the complementary signal from the master side flip-flop element are connected to the gates of the NMOS 13 and the NMOS 15 which are the input terminals of the slave side flip-flop element, respectively, and the timing pulse And the PMOS 3 and 9 and the NMO
The timing pulse having a phase opposite to that of the timing pulse was inputted to the NMOS 6 and the PMOSs 12 and 14, and the signal input terminals of the flip-flops were connected in series. The NMOSs 7 and 8 in which the gates of the NMOSs 4 and 5 and the signal input terminals of the opposite phase of the signal are connected in parallel
, The output signal terminal is the output terminal of the inverter 11, and the output signal terminal of the opposite phase is the output terminal of the inverter 10.

The subsequent D-FF2 has the same circuit configuration. Next, the overall configuration will be described. First stage DF
The input end of F1 is A1, B1, the input end of the negative phase signal is AN
1, BN1 and output terminals Q1 and QN1. Further, the input end of the D-FF2 in the subsequent stage is A2, B2, the input end of the negative phase signal is AN2, BN2, and the output end is Q2, QN2. D-
The output terminals of FF1, Q1 and QN1, are connected to A2 and BN2, respectively.
Connect to. The output terminals of D-FF2, Q2 and QN2, are connected to AN1 and B1, respectively. Further, the frequency division mode switching signal (M) is input to AN2, and the reverse phase signal thereof is input to B2.

The operation will be described with reference to FIG. M =
When H (high level), the NAND logic of D-FF2 is fixed to H and the NOR logic is fixed to L, so D-
The output level of the master side flip-flop element of FF2 does not change, is transmitted to the slave side flip-flop element of D-FF2, the level is inverted, and the NOR logic of D-FF1 of the master side flip-flop element of D-FF1. And NAND logic, respectively. This allows NMO
S5 turns on and NMOS8 turns off. As a result, the D-FF1 is T-coupled, and the frequency division operation is divided by two.

When M = L (low level), D-FF1
Each of the complementary output signals of D-FF1 is delayed by one cycle of the clock signal and delayed by one cycle of the clock signal and NOR logic of D-FF1 of the master side flip-flop element of D-FF1 and NAND.
Each is returned to logic. In NOR logic, H is output only when both input signals are L, and in NAND logic, L is output only when both input signals are H, so a ÷ 3 frequency division operation waveform is obtained. The timing chart of each part during operation can be read as A → D-FF1 inverter 2 input terminal, B → Q1 and E → D-FF2 inverter 2 input terminal, F → Q2 in FIG. It becomes the same as the chart shown in.

Static type ÷ 2 / ÷ 3 described above
FIG. 2 shows the power supply voltage dependence of the maximum operating frequency (dividing by 3) when the variable frequency dividing circuit is composed of 0.2 μm class gate length CMOS. For reference, the performance of the conventional dynamic variable frequency divider circuit shown in FIG. 9 is also shown in comparison. When the power supply voltage decreases, the variable frequency dividing circuit of the present invention exhibits higher speed.

[Second Embodiment] FIG. 3 shows a second embodiment of the present invention. Unlike the first embodiment, this embodiment has a reset function to enable intermittent operation in order to reduce power consumption. PMOS 20 and 21 are newly added in order to initialize the memory contents of D-FF1 and D-FF2 when the power source of the variable frequency divider circuit is cut off and then re-energized.
When initialization is required, an L level signal is input to the PMOS gate. As a result, the output terminal Q1 of the D-FF1
The potentials of QN1 and QN1 are fixed at L and H levels, respectively, and D
The potentials of the output terminals Q2 and QN2 of FF2 are also fixed to the L and H levels, respectively.

[Embodiment 3] FIG. 4 shows a third embodiment of the present invention. Unlike the first embodiment, this embodiment shows an example in which the circuit configuration of the present invention is applied to the ÷ 4 / ÷ 5 variable frequency dividing circuit shown in FIG. In this implementation, D-FF3 is newly added.
By inserting, it is possible to divide by 4 and divide by 5. D
Since -FF1 and D-FF2 have the same circuit configuration as the first embodiment, the D-FF3 will be described.

The input / output terminal of the inverter 22 is connected to the inverter 2
3 are connected to the input / output terminals to form a flip-flop element. The input terminal of the inverter 22 is connected to the high potential side power source through the PMOS 24 driven by the clock signal, and is connected to the low potential side power source through the series connected NMOS 25 and the NMOS 26 driven by the clock signal. To do. The input end of the inverter 23 is connected to the high potential side power source via the PMOS 27, and is connected to the low potential side power source via the NMOS 28 and the NMOS 26 driven by the clock signal.

Next, the circuit configuration of the slave side flip-flop element of the first stage D-FF3 will be described. The input / output terminal of the inverter 29 is connected to the output / input terminal of the inverter 30 to form a flip-flop element,
PMOS31 whose input end is driven by clock signal
Connected to the high-potential side power source through the
And an NMOS 33 driven by a clock signal, and connected to the low potential side power source, and the input terminal of the inverter 30 is connected to P
Connected to the high-potential side power source through the MOS 34, and N
MOS35 and NMOS3 driven by clock signal
3 and is connected to the low potential side power source.

The output end of the twenty-third inverter 23 and the output end of the inverter 22 which are the output ends of the complementary signal from the master side flip-flop element are respectively the NMOS 33 and the NMOS 35 which are the input ends of the slave side flip-flop element.
Connected to the gate of the
4 and 27 and a gate of the 33rd NMOS, and inputs a timing pulse having a phase opposite to the timing pulse to the NM.
The signal input terminal of the flip-flop is the gate of the NMOS 25, the signal input terminal of the opposite phase of the signal is the gate of the 28th NMOS 28, and the output signal terminal is the output terminal of the inverter 30. The output signal terminal of the reverse phase is used as the output terminal of the inverter 29.

Next, the overall configuration will be described. The input ends of the first-stage D-FF1 are A1, B1, the input ends of the negative phase signal are AN1, BN1, and the output ends are Q1, QN1. Also,
The input ends of the D-FF2 in the latter stage are A2 and B2, the input ends of the negative phase signal are AN2 and BN2, and the output ends are Q2 and QN2.
The input end of the newly inserted D-FF3 is A3, the input end of the negative phase signal is AN3, and the output ends are Q3 and QN3.

Output terminals Q1 and QN1 of D-FF1 are connected to A3 and AN3, respectively. The output terminals Q3 and QN3 of the D-FF3 are connected to A2 and BN2, respectively. Also,
The frequency division mode switching signal M is input to AN2, and its reverse phase signal is input to B2. The output terminals Q2 and QN2 of DFF2 are fed back to AN1 and B1 of D-FF1, respectively.
In addition, Q3 and QN3, which are the output terminals of D-FF3, are connected to DF
It returns to BN1 and A1 of F1 respectively. In the present embodiment, the output terminal of the variable frequency dividing circuit is taken out from the output terminals Q1 and QN1 of the D-FF1.
There is no problem even if it is taken out from the output terminal of 3.

The operation will be described with reference to FIG. M = H
At the time of (high level), the NAND logic of D-FF2 is fixed at H and the NOR logic is fixed at L, so D-FF
The output level of the master-side flip-flop element 2 is transmitted to the slave-side flip-flop element of D-FF2 without being changed and inverted, and the NOR logic and NAND of D-FF1 of the master-side flip-flop element of D-FF1 Each is returned to logic. As a result, the NMO of D-FF1
S5 turns on and NMOS8 turns off. As a result, the cascade-connected D-FF1 and D-FF2 are T-coupled, so that the frequency division operation is divided by 4.

When M = L (low level), D-FF2
Has the same function as D-FF3. Of the complementary output signals of D-FF1, the positive-phase signal output Q1 is delayed by one cycle of the clock signal via D-FF3 and fed back to BN1. AN1 is returned after a delay of a period. Since AN1 and BN1 are NOR logic inputs, H is output only when both of the two input signals are L, so that the dividing operation is divided by 5. On the other hand, the negative-phase signal output QN1 is also delayed by one cycle of the clock signal via the D-FF3 and then fed back to A1.
The signal is delayed by 2 cycles of the clock signal via 2 and fed back to B1. Since A1 and B1 are NAND logic inputs, L is output only when both of the two input signals are H, so that the dividing operation is divided by 5.

The timing chart of each part during operation is shown in FIG.
, The input terminal of the inverter 2 of A → D-FF1,
Input terminal of the inverter 2 of B → Q3, E → D-FF2,
If read as F → Q2, the chart becomes similar to the chart shown in FIG.

Static type ÷ 4 / ÷ 5 described above
If the variable frequency divider is composed of a 0.2 μm class gate length CMOS, if the power supply voltage drops as well as the power supply voltage dependency of the maximum operating frequency of the ÷ 2 / ÷ 3 variable frequency divider shown in FIG. The variable frequency divider of the present invention exhibits higher speed than the conventional dynamic type.

[0042]

As described above, by using the static type CMOS variable frequency divider circuit of the present invention for inputting / outputting complementary signals, stable operation is ensured regardless of the operating frequency, and a low power source such as a battery drive. Under voltage, it operates faster than conventional dynamic variable frequency dividers. As a result, the prescaler circuit etc. used for the frequency synthesizer etc. of the next-generation ultra-small mobile communication device can be made into CMOS, and the complete CM of the IC used in these devices can be realized.
The OS is realized, and there is an effect that the power consumption of the system and the cost can be reduced.

[Brief description of drawings]

FIG. 1A is a block diagram of a first embodiment of the present invention,
(B) It is a circuit diagram of D-FF1 and D-FF2 in the block diagram.

FIG. 2 is a comparison diagram of power supply voltage dependence characteristics of operating highest frequency in the circuit of the present invention and the conventional circuit.

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

4A is a block diagram of a third embodiment of the present invention, FIG.
(B) It is a circuit diagram of D-FF3 in the block diagram.

5A is a block diagram of a conventional ÷ 2 / ÷ 3 variable frequency dividing circuit, and FIG. 5B is a circuit diagram of NOR logic gates 51 and 54 in the block diagram.

6 is a timing chart of each part of the circuit of FIG.

FIG. 7 is a block diagram of a conventional ÷ 4 / ÷ 5 variable frequency dividing circuit.

FIG. 8 is a timing chart of each part of the circuit of FIG.

FIG. 9 is a diagram of a conventional dynamic type ÷ 2 / ÷ 3 variable frequency dividing circuit.

[Explanation of symbols]

 1,2,10,11 Inverter 3,9,12,14 PMOS 4,5,6,7,8,13,15,16 NMOS CK clock signal M division mode switching signal

Claims (1)

[Claims] 1. A CMOS variable frequency divider circuit comprising a plurality of master-slave flip-flops and controlled by two-phase timing pulses, wherein one of the flip-flops is an input / output terminal of an inverter (1). Are connected to the output and input terminals of the inverter (2) to form a flip-flop element, and the input terminal of the inverter (1) is connected to the high-potential side power source through the PMOS (3) and connected in series. Two N
MOS (4) and (5) and NMOS (6) are inserted to connect to the low potential side power source, the input terminal of the inverter (2) is connected to the high potential side power source through the PMOS (9), and , NMOS connected in parallel
(7) and (8) and NMOS (6) are inserted and it is equipped with the master side flip-flop element connected to the low potential side power source, and the input / output terminal of the inverter (10) is input / output of the inverter (11). A flip-flop element is configured by interconnecting the terminals, the input terminal of the inverter (10) is connected to the high-potential side power source through the PMOS (12), and the NMOS (1
3) and the NMOS (16) are connected to connect to the low potential side power supply, the input end of the inverter (11) is connected to the high potential side power supply via the PMOS (14), and the NMOS (1
5) and the slave side flip-flop element connected to the low potential side power source through the NMOS (16), and the output terminal of the inverter (2) which is the output terminal of the complementary signal from the master side flip-flop element. And inverter (1)
The output terminals of the two are connected to the gates of the NMOS (13) and the NMOS (15), which are the input terminals of the slave side flip-flop element, and the timing pulse of the two PMOS (3) and (9) and the NMOS (16) is connected. A timing pulse having a phase opposite to that of the timing pulse is input to the gate of the NMOS.
Input to (6) and the two PMOSs (12) and (14), and the signal input terminals of the flip-flops are connected in series to the NM.
Gates of the OSs (4) and (5), signal input terminals of the opposite phase of the signal are gates of NMOSs (7) and (8) connected in parallel, and an output signal terminal of the inverter (1)
1) as an output terminal, and an output signal terminal of the opposite phase as an output terminal of the inverter (10) to form a frequency divider circuit, which is a logical operation and frequency division mode for performing an odd number frequency division operation necessary for variable frequency division operation. C is characterized in that both the logical operations for switching
MOS variable frequency divider circuit.