JP3349170B2 - CMOS variable frequency divider - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ultra-high-speed CMOS variable frequency divider (two-modulus prescaler) operating in the GHz band, and in particular, to a low-power component which is a component of a frequency synthesizer used in a miniature portable telephone and the like. The present invention relates to a circuit configuration method suitable for an ultra-high-speed prescaler (variable frequency dividing) IC.

[0002]

2. Description of the Related Art With the development of the information society, automobile phones and
Demand for mobile communication devices such as mobile phones is growing rapidly. The most effective way to reduce the size and weight of these mobile communication devices is to reduce the battery volume and weight by reducing the power consumption of the circuit. In particular, there is a strong demand for low power of the prescaler IC in the frequency synthesizer, which requires high-speed operation and occupies most of the power consumption during standby.

On the other hand, with the expansion of the use of mobile communication,
The frequency band assigned for this purpose is becoming higher in frequency. That is, the conventional 800 MHz band to the 1.5 GHz band and further the 2.5 GHz band are planned. In response to such a trend, demands for speeding up the above-described prescaler circuit and the like are increasing.

In such a situation, conventionally, a prescaler circuit has conventionally been a GaAs-IC or a Si bipolar IC.
It was composed of (Publication 1; Toshihiko Ichioka et al .: "Low current consumption GaAs SCFL variable frequency divider" The former example is reported in IEICE Technical Report ED88-65, 1988. other:
"High-speed, low-voltage PLL frequency synthesizer LSI with built-in prescaler using Bi-CMOS technology" IEICE Technical Report, ICD88-69, 1988. An example of the latter has been reported. For this reason, the frequency synthesizer has a prescaler and a CMOS, and the other low-frequency parts have been constituted by separate chips. From the viewpoint of reducing the cost and power consumption of the mobile communication device system, it is desirable to use a complete CMOS system, but it has been difficult for a conventional CMOS circuit to perform stable high-speed operation in the GHz band.

Therefore, first, the configuration and operation of the conventional prescaler circuit will be described, and then the configuration technology of the conventional CMOS prescaler circuit will be outlined.

FIG. 5 shows a block diagram of a two-modulus prescaler circuit (# 2 / ÷ 3 variable frequency dividing circuit). D
Type flip-flop (hereinafter abbreviated as D-FF) 51,
52 and NOR logic gates 53 and 54. The NOR logic gate 53 performs a logic operation for performing odd-number division, and the NOR logic gate 54 has a division mode switching function. Conventionally, the NOR logic gate has a vertically stacked structure, for example, such a configuration as shown by PMOSs 56 and 57 and NMOSs 58 and 59 in the figure.
The operation will be briefly described. When the frequency division mode switching signal M of the NOR logic gate 54 is H (high level), the output is low.
(Low level) fixed, and the fixed signal is D-FF
Since the signal is input to the NOR logic gate 53 through 52, the NOR logic gate 53 operates as an inverter. As a result, the D-FF 51 becomes a T-type coupling and performs a ÷ 2 frequency division operation. On the other hand, when M is L (low level), D-FF
The output signal of 51 is further fed back to the input of NOR logic gate 53 with a delay of one clock further by D-FF 52. In the NOR logic gate 53, both input signals are L
Is output only in the case of, and a ÷ 3 frequency dividing operation waveform is obtained. FIG. 6 shows a time chart at the time of the # 2 frequency division and the # 3 frequency division operation described above. A, B, E, and F in the figure correspond to each unit shown in FIG.

[0007] In addition to the block diagram shown in FIG.
By adding one, a variable divider circuit of # 4 / # 5 can be configured. The block diagram is shown in FIG. D-FFs 51, 52, 55 and NOR logic gate 5
3, 54. The NOR logic gate 54 has a frequency division mode switching function. Fig. 5
This is the same as the variable frequency dividing circuit described above.分 dividing by 4 and ÷
FIG. 8 shows a time chart at the time of the divide-by-5 operation. A, B, E, and F in the figure correspond to each unit shown in FIG.

Conventionally, in configuring the prescaler circuits shown in FIGS. 5 and 7, a dynamic flip-flop (hereinafter abbreviated as FF) has been employed to realize a high-speed operation (Publication 3; Kanisawa et al., “¥ 4 /
5 CMOS 2 Modulus Prescaler "1989
IEICE Autumn National Convention C-124 5-
110). FIG. 9 is a circuit diagram in the case where the $ 2 / # 3 variable frequency dividing circuit shown in FIG. 5 is constituted by a dynamic FF including a transfer gate (hereinafter referred to as TG). In the figure, TGs 91 and 92 and inverters 93 and 94 having a CMOS structure constitute a first stage D-FF1. The inverter 97 is a buffer for obtaining an inverted output.
The MOS 95 and the PMOS 96 are reset transistors for performing FF initialization. Similarly, TG98, 99,
Inverters 100 and 101 and NMOS 1 for reset
03, the PMOS 102 constitutes the FF2 at the subsequent stage. Inverter 104 generates a complementary signal of the clock. The operation is the same as that described with reference to the block diagram of FIG. The timing chart during the operation is the same as the change shown in FIG. 5, and A, B, E, and F in the figure correspond to the symbols of each part shown in FIG.

The maximum operating frequency of the variable frequency dividing circuit of FIG.
It is determined by the delay time (Tpd) in the signal path of B → E → F → A at the time of dividing by three. Tpd is a delay (Tin) of the inverter 97 that generates an inverted output of the first stage D-FFI.
v), the delay (Tnor) in the NOR logic gate 4,
It is the sum of the data write delay (Tw) and the read delay (Tr) in the D-FF 2 and the delay (Tnor) in the NOR logic gate 3. Therefore, Tpd = Tinv + 2Tnor + Tw + Tr (Equation 1). Therefore, in order to increase the speed of the variable frequency dividing circuit, it is indispensable to increase the operation speed of the D-FF and the logic gate. The conventional circuit shown in FIG. 9 employs a dynamic FF to shorten Tw and Tr, thereby increasing the speed.

[0010]

However, in the conventional dynamic FF shown in FIG. 9, the operation stability is degraded due to a decrease in the frequency of the clock signal and a variation in the threshold value of the transistor due to a variation in the manufacturing process. There is a problem. That is, the D-FF in FIG.
In 1 and 2, the signal is held by the flip-flop element by combining the source-drain junction capacitance Cj of the TG 91 (or 92, 98, 99) and the gate capacitance Cg of the next-stage CMOS inverter 93 (or 94, 100, 101). This is performed by the electric charge stored in the capacitance C (= Cj + Cg). However, the accumulated charge decreases with time due to the leak current and the subthreshold leak current at the source / drain junction and the gate oxide film, so that as the signal period increases, the signal level held decreases, and finally the next stage It falls below the logical threshold value of the inverter. As a result, the next-stage inverter is inverted and malfunctions.

Further, the problem is that the lower the power supply voltage, the lower the load charging capability of the inverter.
The amount of charge charged to (= Cj + Cg) decreases, and the operation margin decreases. Such a problem is caused not only by a dynamic FF composed of a TG but also by a dynamic FF composed of a clocked inverter (Known Document 4;
"0.2 μm CMOS ultra-high-speed frequency divider," Proceedings of the IEICE Spring National Convention, C-648 5-212, 1990)
Also occurs for the same reason.

When the power supply voltage is reduced, the operating speed and operating margin of the NOR logic gate are greatly deteriorated. Therefore, a high-speed and stable operation with an electromotive force (0.9 to 1.6 V) of one dry battery can be expected. Did not.

In such a situation, G at low power supply voltage
There has been a demand for a CMOS variable frequency dividing circuit technology that operates in the Hz band and operates stably independent of the operating frequency.

The problems of the conventional dynamic CMOS variable frequency dividing circuit are summarized in the following three points.

(1) The stability of the operation is greatly affected by variations in the threshold value of the transistor due to process variations.

(2) There is a lower limit of the operating frequency range, and the stability at low frequencies is poor.

(3) As the power supply voltage decreases, the above (1)
Since the problems (2) and (2) become serious, they are not suitable for low power supply voltage operation.

[0018]

SUMMARY OF THE INVENTION The present invention has been made in order to meet such a demand, and is based on a clocked inverter which is excellent in a high-speed D-FF which determines the performance of a CMOS variable frequency divider. A logic gate adopting a static FF configured, and further incorporating a logic operation for performing odd-number division necessary for variable frequency division operation and a logic operation for switching a division mode into a master-side FF element of the FF. To form a CMOS variable frequency divider having a large operation margin even at a low power supply voltage and excellent in high-speed operation.

[0019]

Since the present invention is constructed as described above, the operation stability is excellent even at a power supply voltage of about one electromotive force (0.9 to 1.6 V) per one dry cell, and the high-speed operation in the GHz band can be performed. A possible CMOS variable frequency dividing circuit can be realized.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1 FIG. 1 shows a first embodiment of the present invention. In this embodiment, the circuit configuration of the present invention is shown in FIG.
An example in which the present invention is applied to a 2 / ÷ 3 variable frequency dividing circuit is shown. The flip-flop according to the present invention employs the D shown in FIG.
It has both the function of -FF and the function of the NOR logic gate (53 or 54).

In FIG. 1, the first-stage D-FF1 and the second-stage D-FF2 have the same circuit configuration. At first,
The circuit configuration of the master-side flip-flop element of the first stage D-FF1 will be described.

The input / output terminal of the inverter 1 is interconnected with the input / output terminal of the inverter 2 to form a flip-flop element. The input terminal of the first inverter 1 is connected to the high potential side power supply through a PMOS 3 driven by a clock signal, and is connected to a low potential through NMOSs 4 and 5 connected in series and an NMOS 6 driven by a clock signal. Connect to the potential side power supply. The NMOSs 4 and 5 connected in series
Performs the function of a NAND logic gate on the input of inverter 1.

The input terminal of the inverter 2 is connected to the high-potential-side power supply via a PMOS 9 and the NM connected in parallel
OS 7 and 8 are connected to the low potential side power supply via NMOS 6. The NMOSs 7 and 8 connected in parallel function as a NOR logic gate for the input of the inverter 2.

Next, a circuit configuration of the slave flip-flop element of the first stage D-FF1 will be described. The input / output terminal of the inverter 10 is interconnected with the input / output terminal of the inverter 11 to form a flip-flop element.
12 whose input terminal is driven by a clock signal
, And connected to the high-potential-side power supply.
And an NMOS 16 driven by a clock signal, and connected to a low-potential-side power supply.
Connected to a high-potential-side power supply via a MOS 14
It is connected to a low-potential-side power supply via a MOS 15 and an NMOS 16.

The output terminal of the inverter 2 and the output terminal of the inverter 1 which are the output terminals of the complementary signal from the master flip-flop element are connected to the gates of the NMOS 13 and NMOS 15 which are the input terminals of the slave flip-flop element, respectively. With the PMOSs 3 and 9 and the NMO
A timing pulse having a phase opposite to that of the timing pulse was input to the NMOS 6 and the PMOSs 12 and 14, and the signal input terminals of the flip-flops were connected in series. NMOSs 7 and 8 in which the gates of NMOSs 4 and 5 and the signal input terminal of the opposite phase of the signal are connected in parallel
, The output signal terminal is the output terminal of the inverter 11, and the output signal terminal of the opposite phase is the output terminal of the inverter 10.

The subsequent D-FF 2 has the same circuit configuration. Next, the overall configuration will be described. First stage DF
A1 and B1 are input terminals of F1 and AN is an input terminal of antiphase signal.
1, BN1, and the output terminals are Q1, QN1. The input terminals of the subsequent D-FF2 are A2 and B2, the input terminals of the negative-phase signal are AN2 and BN2, and the output terminals are Q2 and QN2. D-
Q1 and QN1, which are the output terminals of FF1, are A2 and BN2, respectively.
Connect to The output terminals Q2 and QN2 of D-FF2 are connected to AN1 and B1, respectively. Also, the frequency division mode switching signal (M) is input to AN2, and the opposite phase signal is input to B2.

The operation will be described with reference to FIG. M =
At the time of H (high level), the NAND logic of the D-FF2 is fixed at H and the NOR logic is fixed at L.
The output level of the master flip-flop element of FF2 does not change and is transmitted to the slave flip-flop element of D-FF2, the level is inverted, and the NOR logic of D-FF1 of the master flip-flop element of D-FF1 is inverted. And NAND logic. With this, NMO
S5 is turned on and NMOS 8 is turned off. As a result, since the D-FF1 is T-coupled, the operation becomes a ÷ 2 frequency division operation.

When M = L (low level), D-FF1
Are delayed by one cycle of the clock signal via the D-FF2, and the NOR logic of the D-FF1 of the master flip-flop element of the D-FF1 and the NAND
Each is fed back to the logic. In NOR logic, H is output only when both input signals are L, and in NAND logic, L is output only when both input signals are H, so that a ÷ 3 frequency-divided operation waveform is obtained. The timing chart of each part at the time of operation can be read as shown in FIG. 5 as A → D-FF1 input terminal of inverter 2, B → Q1, E → D-FF2 inverter 2 input terminal, and F → Q2. It is the same as the chart shown in FIG.

The above-described static type $ 2 / $ 3
FIG. 2 shows the power supply voltage dependence of the maximum operating frequency (at the time of # 3 frequency division operation) when the variable frequency dividing circuit is constituted by a 0.2 μm class gate length CMOS. For reference, the performance of the conventional dynamic variable frequency dividing circuit shown in FIG. 9 is also shown for comparison. When the power supply voltage decreases, the variable frequency dividing circuit of the present invention exhibits higher speed.

Embodiment 2 FIG. 3 shows a second embodiment of the present invention. This embodiment is different from the first embodiment in that an intermittent operation is enabled by adding a reset function to reduce power consumption. PMOSs 20 and 21 are newly added in order to initialize the storage contents of the D-FF1 and the D-FF2 when the power supply to the variable frequency dividing circuit is cut off and then re-energized.
When initialization is required, an L-level signal is input to the gate of the PMOS. Thereby, the output terminal Q1 of the D-FF1
, And QN1 are fixed at L and H levels, respectively.
The potentials of the output terminals Q2 and QN2 of -FF2 are also fixed at L and H levels, respectively.

[Embodiment 3] FIG. 4 shows a third embodiment of the present invention. This embodiment is different from the first embodiment and shows an example in which the circuit configuration of the present invention is applied to the # 4 / # 5 variable frequency divider shown in FIG. In this embodiment, a new D-FF3
Is inserted to enable # 4 frequency division and # 5 frequency division. D
Since -FF1 and D-FF2 have the same circuit configuration as the first embodiment, D-FF3 will be described.

The input / output terminal of the inverter 22 is connected to the inverter 2
3 to form a flip-flop element. The input terminal of the inverter 22 is connected to a high-potential power supply through a PMOS 24 driven by a clock signal, and is connected to a low-potential power supply through an NMOS 25 connected in series and an NMOS 26 driven by a clock signal. I do. The input terminal of the inverter 23 is connected to a high-potential power supply through a PMOS 27, and is connected to a low-potential power supply through an NMOS 28 and an NMOS 26 driven by a clock signal.

Next, the circuit configuration of the slave flip-flop element of the first stage D-FF 3 will be described. The input / output terminal of the inverter 29 is interconnected with the input / output terminal of the inverter 30 to form a flip-flop element.
31 whose input terminal is driven by a clock signal
To the high potential side power supply, and
And an NMOS 33 driven by a clock signal, and connected to a low-potential-side power supply.
Connected to a high-potential-side power supply via a MOS 34, and
MOS 35 and NMOS 3 driven by a clock signal
3 and connected to the low-potential-side power supply.

The output terminal of the inverter 23 and the output terminal of the inverter 22 which are the output terminals of the complementary signal from the master flip-flop element are connected to the NMOS 33 and NMOS 35 which are the input terminals of the slave flip-flop element, respectively.
And the timing pulse is connected to the PMOS2
4 and 27 and the gate of the 33rd NMOS, and a timing pulse having a phase opposite to that of the timing pulse is supplied to the NM.
Input to the OS 26 and the PMOSs 31 and 34, the signal input terminal of the flip-flop is the gate of the NMOS 25, the signal input terminal of the opposite phase of the signal is the gate of the 28th NMOS 28, the output signal terminal is the output terminal of the inverter 30, The output signal terminal of the opposite phase is the output terminal of the inverter 29.

Next, the overall configuration will be described. The input terminals of the first stage D-FF1 are A1 and B1, the input terminals of the opposite phase signals are AN1 and BN1, and the output terminals are Q1 and QN1. Also,
The input terminals of the subsequent D-FF2 are A2 and B2, the input terminals of the negative phase signal are AN2 and BN2, and the output terminals are Q2 and QN2.
The input terminal of the newly inserted D-FF3 is A3, the input terminal of the inverted phase signal is AN3, and the output terminals are Q3 and QN3.

The output terminals Q1 and QN1 of the D-FF1 are connected to A3 and AN3, respectively. The output terminals Q3 and QN3 of the D-FF3 are connected to A2 and BN2, respectively. Also,
The frequency division mode switching signal M is input to AN2, and the opposite phase signal is input to B2. The output terminals Q2 and QN2 of DFF2 are fed back to AN1 and B1 of D-FF1, respectively.
Further, the output terminals Q3 and QN3 of D-FF3 are connected to DF
The signal is fed back to BN1 and A1 of F1. In this embodiment, the output terminal of the variable frequency dividing circuit is extracted from the output terminals Q1 and QN1 of the D-FF1, but the output terminal is the D-FF2 or the D-FF.
There is no problem even if it is taken out from the output terminal of No. 3.

The operation will be described with reference to FIG. M = H
At the time of (high level), the NAND logic of the D-FF2 is fixed at H and the NOR logic is fixed at L, so that the D-FF2 is
The output level of the master-side flip-flop element of D-FF2 is transmitted to the slave-side flip-flop element of D-FF2 without change, inverted, and the NOR logic and NAND of D-FF1 of the master-side flip-flop element of D-FF1 are inverted. Each is fed back to the logic. Thereby, the NMO of the D-FF1 is
S5 is turned on and NMOS 8 is turned off. As a result, the cascade-connected D-FF1 and D-FF2 are T-coupled, so that a ÷ 4 frequency division operation is performed.

When M = L (low level), D-FF2
Has the same function as the D-FF3. Among the complementary output signals of the D-FF1, the positive-phase signal output Q1 is delayed by one cycle of the clock signal via the D-FF3, is fed back to the BN1, and at the same time, receives the clock signal 2 via the D-FF2. AN1 is fed back with a delay of the period. Since AN1 and BN1 are inputs of NOR logic, H is output only when both of the input signals are L, so that the ÷ 5 frequency division operation is performed. On the other hand, the anti-phase signal output QN1 is also delayed by one cycle of the clock signal via the D-FF3 and is fed back to A1 at the same time as the D-FF3.
The signal B2 is delayed by two cycles of the clock signal via B2 and fed back to B1. Since A1 and B1 are inputs of NAND logic, L is output only when the two input signals are both H, so that the ÷ 5 frequency division operation is performed.

FIG. 7 is a timing chart of each part during operation.
At the input terminal of the inverter 2 of A → D-FF1,
B → Q3, E → D-FF2 inverter 2 input terminal,
If the reading is changed to F → Q2, it becomes the same as the chart shown in FIG.

The above described static type $ 4 / $ 5
When the variable frequency dividing circuit is formed of a 0.2 μm class gate length CMOS, when the power supply voltage decreases similarly to the power supply voltage dependence of the maximum operating frequency of the # 2 / # 3 variable frequency dividing circuit shown in FIG. The variable frequency dividing circuit of the present invention shows higher speed than the conventional dynamic type.

[0042]

As described above, by using the static CMOS variable frequency divider for inputting / outputting complementary signals of the present invention, stable operation is ensured regardless of the operating frequency, and a low power supply such as a battery drive is used. Under voltage, it operates faster than the conventional dynamic variable frequency divider. This makes it possible to use CMOS for prescaler circuits and the like used in frequency synthesizers and the like of next-generation microminiature mobile communication devices.
The realization of the OS has the effect that the power consumption and the cost of the system can be reduced.

[Brief description of the drawings]

FIG. 1 (a) is a block diagram of a first embodiment of the present invention;
(B) It is a circuit diagram of D-FF1 and D-FF2 in the block diagram.

FIG. 2 is a comparison diagram of the power supply voltage dependence of the highest operating frequency between the circuit of the present invention and a conventional circuit.

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

FIG. 4 (a) is a block diagram of a third embodiment of the present invention;
(B) It is a circuit diagram of D-FF3 in the block diagram.

5A is a block diagram of a conventional $ 2 / $ 3 variable frequency divider, and FIG. 5B is a circuit diagram of NOR logic gates 51 and 54 in the block diagram.

FIG. 6 is a timing chart of each part of the circuit of FIG. 5;

FIG. 7 is a block diagram of a conventional # 4 / # 5 variable frequency dividing circuit.

FIG. 8 is a timing chart of each part of the circuit of FIG. 7;

FIG. 9 is a diagram of a conventional dynamic type ÷ 2 / ÷ 3 variable frequency dividing circuit.

[Explanation of symbols]

 1, 2, 10, 11 inverter 3, 9, 12, 14 PMOS 4, 5, 6, 7, 8, 13, 15, 16 NMOS CK clock signal M frequency division mode switching signal

Claims (1)

(57) [Claims] 1. A CMOS variable frequency divider comprising a plurality of master-slave flip-flops and controlled by a two-phase timing pulse, wherein one of the flip-flops is an input / output terminal of an inverter (1). Are connected to the input / output terminal of the inverter (2) to form a flip-flop element. The input terminal of the inverter (1) is connected to the high potential side power supply through the PMOS (3) and is connected in series. Only two N
The MOS (4) and (5) and the NMOS (6) are interposed to connect to the low-potential power supply, the input terminal of the inverter (2) is connected to the high-potential power supply through the PMOS (9), and , NMOS connected in parallel
(7) and (8) and a master flip-flop element which is connected to a low-potential-side power supply via an NMOS (6) and has an input / output terminal of an inverter (10) connected to an input / output of the inverter (11). The input terminal of the inverter (10) is connected to a high potential side power supply through a PMOS (12), and the NMOS (1)
3) and the NMOS (16) are connected to the lower potential power supply, the input terminal of the inverter (11) is connected to the higher potential power supply via the PMOS (14), and the NMOS (1
5) and a slave-side flip-flop element connected to a low-potential-side power supply via an NMOS (16), and an output terminal of an inverter (2) which is an output terminal of a complementary signal from the master-side flip-flop element. And inverter (1)
Are connected to the gates of NMOS (13) and NMOS (15), which are the input terminals of the flip-flop element on the slave side, respectively, and the timing pulse is supplied to the two PMOSs (3) and (9) and NMOS (16). Input to the gate and apply a timing pulse having a phase opposite to the timing pulse to the NMOS
(6) and input to the two PMOSs (12) and (14), and the NM in which the signal input terminals of the flip-flops are connected in series.
The gates of OS (4) and (5) are used, the signal input terminal of the opposite phase of the signal is the gate of NMOS (7) and (8) connected in parallel, and the output signal terminal is the inverter (1).
A frequency dividing circuit is configured by using the output terminal of 1) and the output signal terminal of the opposite phase as the output terminal of the inverter (10), and performs a logical operation and a dividing mode for performing an odd number dividing operation necessary for the variable dividing operation. Wherein the logical operation for switching between the two is performed by the flip-flop.
MOS variable frequency divider.