WO2000027031A1

WO2000027031A1 - Flip-flop circuit and semiconductor integrated circuit

Info

Publication number: WO2000027031A1
Application number: PCT/JP1998/004923
Authority: WO
Inventors: Tadaaki Tanimoto
Original assignee: Hitachi, Ltd.
Priority date: 1998-10-30
Filing date: 1998-10-30
Publication date: 2000-05-11
Also published as: AU9650998A

Abstract

A flip-flop circuit having a logic circuit between a master latch circuit and a slave latch circuit. A transmission MOS transistor is used instead of a logic gate circuit as a means constituting the logic circuit and the transmission MOS transistor as a MOS transistor which constitutes the slave latch circuit and is operated by clock signals.

Description

_ Description Flipfrog circuit and semiconductor integrated circuit

The present invention relates to a semiconductor integrated circuit technology and, more particularly, to a flip-flop circuit having a logic function, and is useful for, for example, increasing the speed and reducing the power consumption of a flip-flop circuit having a logic function. Technology. Background art

As a flip-flop circuit having a logic function, an invention in which a logic circuit is provided between a master latch circuit and a slave-latch circuit has been proposed (Japanese Patent Application Laid-Open No. Sho 644-1415). No. 6 and Japanese Patent Publication No. 3-1 154 5 14).

Among them, the invention described in Japanese Patent Application Publication No. 64-141516 prevents malfunctions when latch circuits are connected before and after the logic circuit and the operation of the logic circuit is fast. In order to avoid an increase in circuit size due to the use of a master-slave latch circuit (especially in the case of a plurality of latch circuits), the latch circuit preceding the logic circuit is designated as a master latch circuit. The configuration is such that the subsequent latch circuit is configured as a slave-latch circuit to reduce the circuit area.

In addition, the invention described in Japanese Patent Application Laid-Open No. 3-154514 is intended to reduce the power consumption of a master-slave type flip-flop circuit operated by two clock signals which do not overlap with each other. A logic circuit is provided between the master latch circuit and the slave latch circuit, and when the first clock for operating the master latch circuit is shut off, the second clock for operating the slave latch circuit is also shut off. That's how it works.

In any of the above-mentioned prior inventions, the master-latch circuit and the slave 'latch circuit Although a logic circuit is provided, the logic circuit itself follows the conventional circuit form, and no consideration was given to speeding up the logic operation and reducing the power consumption of the logic circuit part. .

SUMMARY OF THE INVENTION It is an object of the present invention to increase the speed and reduce the power consumption of a flip-flop circuit with a logic function having a logic circuit between a master latch circuit and a slave latch circuit.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Invention

The outline of typical inventions disclosed in the present application is briefly described as follows.

That is, according to the present invention, in a flip-flop circuit with a logic function provided with a logic circuit between a master latch circuit and a slave latch circuit, means for configuring logic between the master latch circuit and the slave latch circuit A transmission MOS transistor (transmission gate) is used in place of a logic gate circuit such as an AND gate circuit or an OR gate circuit, and the transmission MOS transistor constituting this logic and a slave latch corresponding to the clock signal. It is designed to share a MOS transistor for latching the circuit.

As a result, a logic output can be obtained simultaneously with the transmission of a signal from the master latch circuit to the slave * latch circuit by the transmission MOS transistor, and the circuit can be operated at a high speed. A logic circuit consisting of transmission MOS transistors provided between the circuit and the slave's latch circuit has a DC current (grounded from the input signal in a CMOS gate circuit) from the power supply voltage terminal to the ground potential as in a logic gate circuit. (Including a through current that flows instantaneously at the time of change), so that low power consumption is achieved.

Note that the above discussion provided between the master and latch circuits and the slave and latch circuits The logical circuit may be any logic such as AND, OR, exclusive OR, addition (including half addition and full addition), subtraction, selection, or a combination thereof.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a circuit diagram showing a flip-flop circuit according to a first embodiment of the flip-flop circuit with a logical function (exclusive OR) according to the present invention.

FIG. 2 is a circuit diagram showing an equivalent circuit of the flip-flop circuit with a logic function of the embodiment of FIG.

FIG. 3 is a circuit diagram showing a flip-flop circuit according to a second embodiment of the flip-flop circuit with a logical function (exclusive OR) according to the present invention.

FIG. 4 is a circuit diagram showing a flip-flop circuit according to a third embodiment of the flip-flop circuit with a logical function (logical sum) according to the present invention.

FIG. 5 is a circuit diagram showing an equivalent circuit of the flip-flop circuit with a logic function of the embodiment of FIG.

FIG. 6 is a circuit diagram showing a flip-flop circuit according to a fourth embodiment of the flip-flop circuit with a logical function (logical product) according to the present invention.

FIG. 7 is a circuit diagram showing an equivalent circuit of the flip-flop circuit with a logic function of the embodiment of FIG.

FIG. 8 is a circuit diagram showing a flip-flop circuit according to a fifth embodiment of the flip-flop circuit with a logic function (full addition) according to the present invention.

FIG. 9 is a circuit diagram showing an equivalent circuit of the flip-flop circuit with a logic function of the embodiment of FIG.

FIG. 10 is a circuit diagram showing a flip-flop circuit according to a sixth embodiment of the flip-flop circuit with the logic function (half addition) according to the present invention.

FIG. 11 is a circuit diagram showing an equivalent circuit of the flip-flop circuit with a logic function of the embodiment of FIG. FIG. 12 is a circuit diagram showing a flip-flop circuit according to a seventh embodiment of the flip-flop circuit with a logic function (multiplex) according to the present invention.

FIG. 13 is a circuit diagram showing an equivalent circuit of the flip-flop circuit with a logic function of the embodiment of FIG.

FIG. 14 is a timing chart showing operation timings of the circuit of the embodiment in FIG.

FIG. 15 is a timing chart showing the operation timing of the multiplexer circuit of FIG.

FIG. 16 is a circuit diagram showing a multiplexer circuit having functions equivalent to those of the embodiment circuit of FIG. 12 and using a logic gate circuit.

FIG. 17 is a circuit diagram showing an equivalent circuit of the circuit of FIG.

FIG. 18 is a circuit diagram showing a flip-flop circuit according to an eighth embodiment of the flip-flop circuit with a logic function (demultiplex) according to the present invention.

FIG. 19 is a circuit diagram showing an equivalent circuit of the flip-flop circuit with a logic function of the embodiment of FIG.

FIG. 20 is a circuit diagram showing a flip-flop circuit according to a ninth embodiment of the flip-flop circuit with a logic function according to the present invention.

FIG. 21 is a circuit diagram showing an equivalent circuit of the flip-flop circuit with a logic function of the embodiment of FIG.

FIG. 22 is a timing chart showing the operation timing of the embodiment circuit of FIG.

FIG. 23 is a block diagram showing the configuration of a known 16 × 16 pixel binary image filter circuit.

FIG. 24 is a block diagram showing an embodiment of a binary image filter circuit as an application example of the flip-flop circuit with a logic function according to the present invention.

FIG. 25 is a flowchart showing a design procedure when designing a logic integrated circuit by registering a flip-flop circuit with a logic function according to the present invention in a cell library. It is a chart. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a logic circuit having an exclusive OR function (EOR and EN〇R) between a master latch circuit and a slave latch circuit as an embodiment of a flip-flop circuit having a logic function according to the present invention. FIG. 4 is a circuit diagram showing an example of a flip-flop circuit provided with.

The flip-flop circuit shown in Fig. 1 is composed of a master 'latch section 10 consisting of two differential input type CMOS latch circuits LT1 and LT2, and a slave' latch section 30 consisting of one CM〇S latch circuit. And a logical operation unit 20 composed of a transmission MOSFET provided between the master / latch unit 10 and the slave / latch unit 30.

The CMOS latch circuit LT 1 (LT 2) of the master latch unit 10 has a source terminal connected to the power supply voltage Vdd (for example, 5 ports) and a gate terminal to which the clock signal / CLK is input. p 1 (Qp l,) and a pair of differential inputs M〇SFETQ p 2, Q p with the source terminal connected to the drain terminal of the MOSFET TQ pl and the gate terminal connected to the input terminal 3 (Q p 2 Qp 3 ') and the M〇 SFET Q p 4, Qn 1 connected in series between the drain terminals of these MOS FET Q p 2, Q p 3 and the ground potential V ss, respectively. (QP 4 ', Qn 1') and Qp 5, Qn 2 (Q p 5 ', Qn 2') and the drain terminal of the differential input MOS FET Q p 2, Q p 3 p channel M〇S FET Qp 6 (Q p 6 ′).

The gate terminals of the above MOSFETs Qp4 and Qnl (Qp4 'and Qnl,) and the gate terminals of Qp5 and Qn2 (Qp5' and Qn2,) are connected in common. And the common gate terminals of these amplifiers are cross-coupled with each other and connected to the other common drain terminal to form a local latch circuit. Is composed. These common drain terminals are connected to output nodes n1, n2 (n1, n2 ').

The latch circuit LT 1 (LT 2) is used for turning off the MOS FET TQ 1 (Q p 1) when the clock signal / CLK is set to a high level and inactive, and for latching. The p-channel M〇S FETQ p6 (Qp6,) of the p-channel is turned on, and the output nodes nl, n2 (nl, n2 ') become the ground potential Vss. Then, the latch circuit LT 1 (LT 2) is activated when the clock signal / CLK is set to the low level, and when the low-level input signal IN 1 (IN 2) is input at this time, the differential input is performed. M〇 SFET Q p 2 (Q p 2 ′) is turned on, and Qp 3 (Q p 3 ′) is turned off. As a result, a high potential close to the power supply voltage Vcc is applied to the source of the MOSFET TQ p5 (Qn2 '), and the source is turned on, and the output node n1 (n1,) is set to the high level (Vn cc), and n 2 (n 2 ′) becomes low level (V ss), and this state becomes a single-state latch circuit (Qp 4, Qn l and Qp 5, Qn 2, Qp 4, Qn l 'and Q p 5 ,, Q n 2 '). When the input signal INI (IN 2) of the low level or the high level is input, the output node nl (η ΐ ′) goes low (V ss) and n2 (η 2 ′) goes high (V cc). The state is held by the oral latch circuit (Qp4, Qnl and Qp5, Qn2 (Qp4 '_; Qnl, and Qp5, Qn2'). , Q p 6 ′ are always turned on by applying the ground potential V ss (for example, 0 port) to the gate terminals of the MOSFETs when the MOSFET Q p 1, Qp 1 ′ is turned off by the clock / CLK. Acts as an equalizing element.

Note that the latch circuits LT1 and LT2 constituting the master latch section 10 of this embodiment are merely examples, and the present invention is not limited to this. For example, by omitting the differential inputs MO SF ET Q p 2, Q p 3 (Q p 2 ', Q p 3'), the input signal IN 1 (IN 2) is used as the MO SFET Q p 4, A configuration is also possible in which input is made directly to the common gate terminal of Qn1 or Qp5, Qn2 (Qp4, Qnl 'or Qp5', Qn2 '). On the other hand, the slave latch section 30 is composed of M〇SFETs Q p7 and Qn5 and Qp 8 and Qn 6 connected in series between the power supply voltage Vdd and the ground potential V ss. The gate terminals of the MOS FETQ p7 and Qn5 and the gate terminals of QP8 and Qn6 are commonly connected to each other to form an amplifier. The input / output nodes n3 and n4 are cross-coupled with each other to form a latch circuit.

The logic operation unit 20 is connected in parallel between the pair of output nodes n 1 and n 2 of the latch circuit LT 1 of the master latch unit 10 and one input / output node n 3 of the slave latch unit 30. The transmission MO SFETs Qn7 and Qn8 connected to the master, the latch circuit of the latch unit 10 and the pair of output nodes n1, and n2 of the LT2 and the other of the slave latch unit 30 It is composed of transmission MOSFETs Qn9 and QnIO connected in parallel between the input and output node n4. The potential of one output node n 1 of the latch circuit LT 2 is applied to the gate terminal of the transmission MO SFET Qn 7, and the other output node of the latch circuit LT 2 is applied to the gate terminal of the transmission MO SFET Qn 8. The gate of the transmission MOS FET Q n 9 receives the potential of one output node n 1 of the latch circuit LT 1, and the transmission MO SFET Q n 10 has the gate terminal of the latch circuit LT. The potential of the other output node n 2 of 2 is input to each.

As a result, a signal (EOR) obtained by taking the exclusive OR of the input signals A and B is applied to the input / output node n 3 of the slave latch unit 30 and the input / output node of the slave latch unit 30. A signal obtained by taking the exclusive OR (ENOR) of the input signals A and B is supplied to n4, and the width is determined by the inverters (Qp7, Qn5) and (Qp8, Qn6). And output.

Further, in this embodiment, during the period when the clock signal / CLK is at the low level, the n-channel MOS FETs Q n3, Q n4, Q n 3 ′ and Q n 4 ′ for the display are turned on, Transmission The gate terminals of the MS FETs Qn7 to QnlO are set to low level, and Qn7 to QnlO are turned off. As a result, The latch unit 30 enters the signal holding state.

That is, in this embodiment, the M チャージ S FET Qn3 to Qn4 for discharge connected to the output node of the master / latch unit 10 (the input node of the logical operation unit 20) is a clock signal / CLK. During the high level period, the master latch unit 10 is activated, and during the low level period, the transmission MOSFETs Qn7 to Qn10 are turned off to operate the slave latch unit 30 in the signal holding state. Thus, the slave latch unit 30 can be shifted to the latch state at the same time when the operation of the master latch unit 10 by the clock signal ends.

In addition, the free-running circuit of this embodiment is provided with a logic operation section 20 composed of a transmission MOS FET between the master latch section 10 and the slave latch section 30. Performs logic operation simultaneously with transmission of signals to the master latch unit 10 and slave latch unit 30. As a result, the delay due to the logical operation in the logical operation unit 20 is eliminated, and the circuit can be speeded up.

At the same time, the logical operation unit 20 composed of the transmission MOS FET provided between the master latch unit 10 and the slave latch unit 3 ° includes a logic gate circuit such as an AND gate circuit or an OR gate circuit. There is no path through which DC current flows from the power supply voltage terminal to the ground potential. As a result, low power consumption is achieved.

2 (A) and 2 (B) show equivalent circuits that represent the functions of the circuit of Fig. 1 using a conventional logic gate circuit. In other words, in the circuit of this embodiment, a latch circuit is arranged before the logic operation circuit as shown in FIG. 2A, or a latch circuit is arranged after the logic operation circuit as shown in FIG. 2B. Is equivalent to FIG. 2 (C) shows a case where a master / latch circuit MLT and a slave / latching circuit SLT are provided at the front and rear stages of the logical operation circuit, respectively, as in a conventional logic circuit.

As is clear from comparison of Figs. 2 (A), 2 (B) and 2 (C), in the conventional circuit, the gate delay in the logical operation circuit cannot be ignored (therefore, the preceding and following latch circuits are not clocked). The same page cannot be operated) and the delay in the preceding and following latch circuits is added. On the other hand, in the free-flop circuit of this embodiment, the delay (output delay or input delay) in the logic operation circuit section is theoretically “0”, so the delay of the entire circuit is reduced to one stage of the latch. It can be seen that the speed is greatly increased.

FIG. 3 shows another embodiment of a flip-flop circuit in which a logic circuit having an exclusive OR function is provided between a master latch circuit and a slave latch circuit. In FIG. 3, portions denoted by the same reference numerals as those in FIG. 1 are circuits having the same functions. In the embodiment of FIG. 1, the master's latch section 10 is composed of the differential input type CM 0 S latch circuits LT 1 and LT 2, whereas the embodiment of FIG. This is an embodiment of the invention. Also in this embodiment, the logical operation unit 20 provided between the master latch unit 10 and the slave latch unit 30 is constituted by the CMOS transmission gates TG 1 and TG 2. However, the delay time due to the logic operation is reduced, and the speed is increased. As shown in the embodiment of FIG. 1, the use of a differential latch circuit in the master's latch section 10 is more resistant to noise and has the advantage that the signal can be transmitted without error even if the signal amplitude is reduced. There is.

Figure 4 shows the implementation of a flip-flop circuit in which a logical operation unit 20 having an OR function (OR and NOR) is provided between the master latch unit 10 and the slave latch unit 30. Here is an example. The circuit of this embodiment is similar to the embodiment of FIG. 1 in which the logical operation unit 20 is configured to have an exclusive OR function, and in FIG. 4, the same reference numerals as in FIG. 1 are used. Are circuits having the same function. The circuit of FIG. 4 is different from the circuit of the embodiment of FIG. 1 in that the conductivity types of the MOSFETs constituting the latch circuits LT 1 and LT 2 of the latch unit 10 are reversed, and that the clock The drain terminal is connected to the output nodes nl, n2, nl, and η2 'of the latch circuits LT1 and LT2 of the master latch unit 10 controlled by / CLK. {0SF} Are connected to the power supply voltage V dd instead of the ground potential V ss, and are different in the conductivity type and connection of the M〇SFET constituting the logic operation unit 20. That is, the logical operation unit 20 of this embodiment includes a pair of output nodes n 1 and n 2 of the latch circuit LT 1 of the master latch unit 10 and one input of the slave latch unit 30. The transmission MO SFETs Q p11 and Q p12 connected between the output nodes n 3 and n 4 and the output node of this transmission MO SFET Q 11 1 (input and output of the slave 'latch section 30) The MOSFET Qp l 3 connected between the node n 3) and the ground, the output node of the transmission MOSFET Qp 12 (input / output node n4 of the slave 'latch 30) and the power supply voltage Vd d And MO S FET Qp l 4 connected between the two. The potential of one output node n 2 of the latch circuit LT 2 is set at the gate terminal of the transmission M〇 SFET Qp ll, Qp l 2, and the latch circuit is set at the gate terminal of the MOS FET Q 13, Q p 14. The potential of the other output node n 1 ′ of LT 2 is input.

As a result, from the input / output node n 3 of the slave latch unit 30, a signal (N〇R) having the opposite phase of the logical sum of the input signals A and B is output from the input / output node n 3 of the slave latch unit 30. From n4, a signal (OR) that is the logical sum of the input signals A and B is output.

Also in this embodiment, since the logical operation unit 20 provided between the master's latch unit 10 and the slave's latch unit 30 is constituted by a transmission MOSFET, the delay due to the logical operation in the logical operation unit 20 is reduced. And the circuit speeds up.

In addition, a logic operation unit 20 composed of a transmission MOSFET provided between the master latch unit 10 and the slave latch unit 30 is connected to a ground potential from a power supply voltage terminal as in a logic gate circuit. Since there is no path through which direct current flows, low power consumption is achieved.

FIGS. 5A and 5B show equivalent circuits in which the functions of the circuit of FIG. 4 are represented using a conventional logic gate circuit. In other words, in the circuit of this embodiment, a latch circuit is arranged before the logical operation circuit as shown in FIG. 5A, or a latch circuit is arranged after the logical operation circuit as shown in FIG. 5B. Is equivalent to When a similar logic function is realized in a conventional logic circuit, a master latch circuit and a slave latch circuit are provided before and after the logic operation circuit, respectively, as in the case of FIG. 2 (C). Provided.

As apparent from FIGS. 5 (A), 5 (B) and FIG. 2 (C), in the conventional circuit, the gate delay in the logic operation circuit cannot be ignored, and the gate delay in the preceding and following latch circuits cannot be ignored. While the delay is added, in the flip-flop circuit according to the present embodiment, the delay (output delay or input delay) in the logic operation circuit section is theoretically “0”, so the delay of the entire circuit is latched. Since it is reduced to one stage, it can be seen that the speed is greatly increased.

FIG. 6 shows an embodiment of a flip-flop circuit in which a logical operation unit 20 having a logical product (AND and NAND) function is provided between the master latch unit 10 and the slave latch unit 30. The circuit of this embodiment is similar to the embodiment of FIG. 4 in which the logical operation unit 20 is configured to have a logical sum function. In FIG. 6, the same reference numerals as in FIG. These circuits have the same function.

In this embodiment, the latch circuit LT1 of the master-latch unit 10 includes a P-channel MOS FET TQ p23 having a source terminal connected to the power supply voltage V dd and a gate terminal receiving the clock signal CLK, and A pair of differential inputs MO SFETs Qp 24 and Qp 25 connected so that the source terminal is connected to the drain terminal of the MO SFET Qp 23 and the input signals B and / B are input to the gate terminal, and the power supply voltage Vd d And MOSFETs Qp21, Qn24 and Qp22, Qn25 connected in series between the ground potential V ss and the ground potential V ss, respectively. The gate terminals of the MOSFETs Qp21 and Qn24 and the gate terminals of Qp22 and Qn25 are connected in common, and this common gate terminal is cross-coupled with the other common drain terminal. These common drain terminals are connected to the drain terminals of the differential inputs M〇SFETs Q p24 and Qp25, and the output nodes n 1 1 and It is also connected to n12.

When the clock signal / CLK is set to the high level, the latch circuit LT1 turns off the M〇SFET Qp23 and enters the non-operating state. Then, the latch circuit LT 1 is activated when the clock signal / CLK is set to low level, and When a low-level input signal B is input, the differential input MOSFET Qp25 is turned on, and Qp24 is turned off. As a result, a high potential close to the power supply voltage Vcc is applied to the common drain of the MOS FETs Qp22 and Qn25, and the output node nl1 is at a high level (Vcc) and nl2 is at a low level. (Vs s), and this state is held by the local latch circuits (Qp21, Qn24 and Qp22, Qn25). When the high-level input signal B is input, the output node n 11 becomes low level (V ss), and n 22 becomes high level (V cc), and this state becomes the oral latch circuit (Qp 21 1, Qn24 and Qp22, Qn25).

The other latch circuit LT2 of the master latch section 10 has the same configuration as the configuration of the latch circuit LT2 of the master latch section 10 in the flip-flop circuit having an OR function in FIG. In the flip-flop circuit having the exclusive OR function in FIG. 1, the conductivity type of the MOS FET is opposite to that of the latch circuit LT 2 of the master latch unit 10.

The logical operation unit 20 of this embodiment has the same configuration as the logical operation unit 20 in the flip-flop circuit having the OR function of FIG.

In other words, it is connected between a pair of output nodes n 11 and n 12 of the latch circuit LT 1 of the master latch unit 10 and one of the input / output nodes n 3 and n 4 of the slave latch unit 30. Connected between the transmission MOS FET Qp ll and Q pl 2 and the output node (input / output node n 3 of the slave 'latch unit 30) of the transmission MO S FET Qp 11 and the ground point. MO SFETQ p13 and MO SFETQp14 connected between the output node of transmission MO SFETQ p12 (input / output node n4 of slave / latch unit 30) and power supply voltage Vdd. I have. The gate terminal of the transmission M〇S FE TQ p 11, Q 12 has the potential of one output node n 2 ′ of the latch circuit LT 2, and the gate of the MOS FE TQ 13, Q 14 The potential of the other output node n1, of the latch circuit LT2 is input to the terminal. As a result, a signal (NAND) having the opposite phase of the logical product of the input signals A and B is output from the input / output node n3 of the slave latch unit 30, and from the input / output node n4 of the slave latch unit 30. Then, a signal (AND) that is the logical product of the input signals A and B is output.

Also in this embodiment, since the logical operation unit 20 provided between the master / latch unit 10 and the slave / latch unit 30 is constituted by the transmission MOS FET, the logical operation in the logical operation unit 20 is performed. There is no delay, and the circuit speeds up.

In addition, a logic operation unit 20 including a transmission MOS FET provided between the mass latch unit 10 and the slave latch unit 30 has a power supply voltage terminal as in a logic gate circuit and a ground potential. Since there is no path through which DC current flows, low power consumption is achieved.

FIGS. 7A and 7B show equivalent circuits in which the functions of the circuit of FIG. 6 are represented using a conventional logic gate circuit. That is, in the circuit of this embodiment, a latch circuit is arranged in front of the logical operation circuit as shown in FIG. 7 (A), or a latch circuit is arranged after the logical operation circuit as shown in FIG. 7 (B). Is equivalent to When a similar logic function is to be implemented in a conventional logic circuit, the master / latch circuit and the slave latch circuit are placed before and after the logic operation circuit, respectively, as in Fig. 2 (C). Is set up.

As is clear from FIGS. 7 (A), 7 (B) and 2 (C), in the conventional circuit, the gate delay in the logical operation circuit cannot be ignored and the delay in the preceding and following latch circuits is not significant. On the other hand, the flip-flop circuit of the present embodiment theoretically has a delay (output delay or input delay) of “0” in the logic operation circuit section, so the delay of the entire circuit is one stage of latch. It can be seen that the speed is greatly increased because it is reduced in minutes.

FIG. 8 shows an embodiment of a flip-flop circuit in which a logical operation unit 20 having a full addition function is provided between the master latch unit 10 and the slave latch unit 30. The latches to which the operated signals A and B in the master latch section 10 are inputted respectively. The circuits LT 1 and LΤ2 have the same configuration as the embodiment of FIG. The latch circuit LT3 to which the carry signal Cin is input includes an n-channel MOS FET Qn21 having a source terminal connected to the power supply voltage Vdd and a clock signal / CLK input to the gate terminal, and The source terminal is connected to the drain terminal of the MOS SFET Qn 21 and the gate terminal is connected to the input terminal to which the carry signal Cin, / Cin is input. Qn 23 and M〇SFETs Qp 21, Qn 24 and Qp 22, Qn 22 and Qn 25 connected in series between the power supply voltage V dd and the ground potential V ss, respectively.

The gate terminals of the MOSFETs Qp 21 and Qn 24 and the gate terminals of Qp 22 and Qn 25 are commonly connected, and the common gate terminal is cross-coupled with the other common drain terminal. These common drain terminals are connected to the drain terminals of the above differential inputs MOSFE TQn22 and Qn23, as well as to the output nodes n11 and n12. I have.

As described above, the configuration of the latch circuit LT3 to which the carry signal Cin is input is different from the configuration of the latch circuits LT1 and LT2 to which the operand signals A and B are input is as follows. Unlike the logic operation section 20, there is no need to form a signal for controlling the transmission MOS FET, so that the discharge M〇 SF ET (Q n 3, Q n 4) operated by the clock CLK is not required, and V dd — This is to reduce the number of vertical stacked MOSFETs in series between V ss and operate with sufficient source-drain voltage of one MOSFET. The configuration of the latch circuit LT3 is not limited to that of the embodiment, and it is possible to adopt the same configuration as the circuits LT1 and LT2 (however, Qn3 and Qn4 are unnecessary).

The slave 'latch section 30 of this embodiment comprises two latch circuits SLT1 and SLT2. Each of the latch circuits SLT1 and SLT2 is connected between the power supply voltage Vdd and the ground potential Vss. The MOS SFETs Qp27 and Qn27 and Qp28 and Qn28 are connected in series. The gate terminals of the M0 SFETs Qp27 and Qn27 and the gate terminals of Qp28 and Qη28 The common gate terminals are cross-coupled to each other with the other common drain terminal, and these common drain terminals are connected to input / output nodes n3 and n4.

The logical operation unit 20 receives as input the first operation unit 2OA configured similarly to the logical operation unit 20 in FIG. 1 and the output signals of the latch circuits LT1, LT2, and LT3 of the master latch unit 10; The second arithmetic unit 20B is controlled by the output signal of the first arithmetic unit 20A.

The second operation unit 20B is connected between the output nodes nil and nl2 of the third latch circuit LT3 of the master 'latch unit 10 and the input / output node n3 of one of the latch circuits SLT1 of the slave' latch unit 30. The transmission MOS FETs Qp11 and Qp12 connected in parallel between the output nodes nil and nl2 of the LT3 and one of the latch circuits 30 of the slave 'latch unit 30 are connected in parallel between the input and output nodes n4 of the SLT1. , The output node nil of the LT 3 and the output node n1 of one of the latch circuits LT1 of the master latch section 30 and the slave latch described above. The transmission MOS FETs Q 15, Qp l 6 connected in parallel between the other latch circuit SLT 2 of input / output node n 3 ′, the output node nl 2 of LT 3 and the master latch 30 Input / output of one output node n 2 ′ of the latch circuit LT 2 and the other latch circuit SLT 2 of the slave latch unit 30 Over de n 4 'that is constituted by the transmission MO S F E T Q p 17, Q p 1 8 connected in parallel between.

The gate terminals of the transmission MOS FET Q p 11, Q 14, Q 16, and Qpl 8 are connected to the potential of one output node n 5 of the first arithmetic unit 2 OA by the transmission MO SFET Qp The potential of the other output node of the first arithmetic unit 20A is commonly applied to the gate terminals of l 2, Qp 13, Qp 15, and Qp 17. The gate terminal of one output node n1 of the latch circuit LT1 is connected to the gate terminal of the transmission MOSF ET Q n5, and the other output node n2 of the latch circuit LT2 is connected to the gate terminal of the transmission MOSFET Qn6. Is input each time. As a result, one of the latch circuits SLT 1 of the slave latch unit 30 outputs the lower signal (SUM) of the signal obtained by adding the input signals A, B, and Cin and the signal having the opposite phase (/ SUM). From the other latch circuit SLT 2 of the latch unit 30, a signal (Cout) on the upper side of the signal obtained by adding the input signals A, B, and Cin and a signal (/ Cout) having a phase opposite thereto are different from each other. Will be output.

In this embodiment, the output nodes n5 and n6 of the first operation unit 2OA of the logical operation unit 20 are precharged MO SFE TQ p 19 turned on and off by the clock signal CLK, respectively. , Q p20 are connected, and the precharge M 0 SFET Q 19, Q p 20 is a clock signal C LK that causes the latch circuits LT 1 to LT 3 of the master latch unit 10 to be in an inactive state. , And the gate terminals of all the transmission MOS FETs Q pll to Q pl 8 constituting the second operation unit 20 B are fixed to the high level and all are turned off. As a result, the slave latch unit 30 is set in the signal holding state.

Also in the flip-flop circuit of this embodiment, a logic operation unit 20 composed of a transmission MOS FET is provided between the master latch unit 10 and the slave latch unit 30, and the transmission M The SFET performs logic operation at the same time as transmitting signals to the master latch unit 10 and the slave latch unit 30. As a result, the delay due to the logical operation in the logical operation unit 20 is eliminated, and the circuit can be speeded up. In addition, the gate terminals of the transmission MOSFETs Qpll to Qp18 are precharged during the low level period of the clock signal, the clock is changed to the high level, and the latch circuits LT1 and LT2 are activated. The signal line which gives the level of the gate terminal of MOSPET Qp11 to Qp18 is discharged immediately when the input signals A and B are input. High-speed operation is guaranteed because the ON and OFF states are determined.

At the same time, the logic operation section 20 composed of the transmission MOS FET provided between the master latch section 10 and the slave latch section 30 has a power supply as in the logic gate circuit. There is no path for DC current to flow from the voltage terminal to the ground potential. Les ,. As a result, low power consumption is achieved.

FIGS. 9A and 9B show equivalent circuits in which the functions of the circuit of FIG. 8 are represented using a conventional logic gate circuit. That is, the circuit of this embodiment has a configuration in which the latch circuits LT1 to LT3 are arranged in front of the logical operation circuit 20 as shown in FIG. 9 (A) or the latter stage as shown in FIG. 9 (B). This is equivalent to the configuration in which latch circuits SLT 1 and SLT 2 are arranged. When a similar logic function is implemented in a conventional logic circuit, a master latch circuit and a slave latch circuit are provided at the front and rear stages of the logic operation circuit, respectively, as in the case of Fig. 2 (C). Can be

As is clear from FIGS. 9 (A), 9 (B) and 2 (C), in the conventional circuit, the gate delay in the logical operation circuit cannot be ignored and the delay of the preceding and following latch circuits is added. On the other hand, the flip-flop circuit according to the present embodiment theoretically has a delay (output delay or input delay) of “0” in the logical operation circuit section, so that the delay of the entire circuit is one stage of the latch. It can be seen that the speed is greatly increased because it is reduced in minutes.

FIG. 10 shows an embodiment of a flip-flop circuit in which a logical operation unit 20 having a half addition function is provided between a master latch unit 10 and a slave latch unit 30. The main unit 10 of this embodiment comprises two latch circuits LT1 and LT2 to which the input signals A and B are inputted respectively. Each of the latch circuits LT 1 and LT 2 has the same configuration as the embodiment of FIG. The slave 'latch unit 30 also includes two latch circuits SLT1 and SLT2. Each of the latch circuits SLT1 and SLT2 is similar to the slave latch circuits SLT1 and SLT2 of the embodiment of FIG. Each of the MOSFETs is composed of MO SFETs Q p27, Qn27 and Qp28, Qn28 connected in series between the power supply voltage V dd and the ground potential V ss, respectively. The gate terminals of the MOSFETs Qp27 and Qn27 and the gate terminals of Qp28 and Qn28 are connected to each other, and this common gate terminal is cross-coupled to the other common drain terminal. Are connected to the input / output nodes n3 and n4.

The logical operation unit 20 is connected to the output of the latch circuit LT 1 of one of the master latch units 10. —Transmission MO SFETs Qn ll, Qn l 2 connected in parallel between the nodes nl, n 2 and one of the latch circuits 30 of the slave 'latching unit 30', the input / output node n 3 of the SLT 1 and the master 'latch unit The transmission MO SFETQ n 1 connected in parallel between the output node nl ', n 2' of the other latch circuit LT 2 of LT 30 and the input / output node n 4 of the latch circuit SLT 1 of the slave latch section 30 3, Q n 14 connected in parallel between the output node n 1 of LT 1 and the power supply voltage terminal V dd and the input / output node n 3 of the other latch circuit SLT 2 of the slave latch unit 30 The transmission M〇 SFETs Qn 15 and Qn l 6 are connected in parallel between the output node nl of LT 2 and the ground point and the other input / output node η 4 ′ of the latch circuit SLT 2 of the slave 'latch unit 30. It consists of connected transmission MOSFETs Qn17 and Qn18.

The potential of the output node nl 'of the other latch circuit LT2 of the master latch unit 30 is applied to the gate terminals of the transmission M〇SFE TQn11 and Qn15. 2, the potential of the output node n 2 of the latch circuit LT 2 is applied to the gate terminal of Q n 16. In addition, the potential of the output node n1 of one latch circuit LT1 of the master latch unit 30 is applied to the gate terminals of the transmission MO SFETs Qn13 and Qn17, The potential of the output node n2 of the latch circuit LT1 is applied to the gate terminal of Qnl8.

As a result, the signal (A + B) obtained by calculating the logical sum of the input signals A and B and the signal having the opposite phase (/ A + B) are output from one latch circuit SLT1 of the slave latch section 30. ), And the other latch circuit SLT 2 of the slave latch section 30 outputs a signal (A · B) obtained by ANDing the input signals A and B and a signal (/ A · B) having the opposite phase (/ A · B). It will be output.

Further, in this embodiment, during the period when the clock signal / CLK is at the low level, the n-channel MQSFETs Qn3, Qn4, and Qn3Qn4 'for discharge are turned on, and the transmission MO SFETQ The gate terminals of n11 to Qn18 are set to low level, and Qn11 to Qn18 are turned off. As a result, the slave latch unit 30 enters the signal holding state. That is, in this embodiment, the MOS FETs Qn3 to Qn4 for discharge connected to the output node of the master / latch unit 10 (the input node of the logical operation unit 20) have the clock signal / CLK high. The master latch unit 10 is activated during the level period, and the transmission M〇SFET Qnll to Qnl 8 is turned off during the mouth level period, thereby acting to put the slave latch unit 30 into a signal holding state. . Thus, a logic output can be obtained at the same time as the operation of the master / latch unit 10 by the clock signal, and the slave latch unit 30 can be shifted to the latched state at the same time as the operation ends. As a result, the delay due to the logical operation in the logical operation unit 20 is eliminated, and the speed of the circuit can be increased.

At the same time, the logic operation unit 20 composed of the transmission MOSFET provided between the mass latch unit 1Q and the slave latch unit 30 has a power supply voltage terminal, such as in a logic gate circuit, connected to the ground potential. There is no path for direct current to flow. As a result, low power consumption is achieved.

FIGS. 11A and 11B show equivalent circuits in which the function of the circuit of FIG. 10 is represented using a conventional logic gate circuit. In other words, the circuit of this embodiment has a configuration in which the latch circuits LT 1 and LT 2 are arranged in front of the logical operation circuit 20 as shown in FIG. 11A, or the logical operation circuit 20 as shown in FIG. 11B. This is equivalent to the arrangement of latch circuits S LT 1 and S LT 2 at the subsequent stage. When a similar logic function is implemented in a conventional logic circuit, a master latch circuit and a slave latch circuit are provided at the front and rear stages of the logic operation circuit, respectively, as in the case of FIG. 2 (C). Provided.

As is clear from Figs. 11 (A), (B) and Fig. 2 (C), in the conventional circuit, the gate delay in the logical operation circuit cannot be ignored and the delay in the preceding and following latch circuits is not sufficient. In the flip-flop circuit of the present embodiment, the delay (output delay or input delay) in the logic operation circuit section is theoretically “0”, so that the delay of the entire circuit is one stage of the latch. It can be seen that the speed is greatly increased because it is reduced in minutes.

FIG. 12 shows an implementation of a flip-up circuit in which a logical operation unit 20 having a multi-blinker function is provided between the master latch unit 10 and the slave latch unit 30. Here is an example.

In the circuit of this embodiment, the master latch section 10 includes three latch circuits LT 1, LT 2, and LT 3, of which the selection signal SE is supplied to LT 3 and the selected input is supplied to LT 1 and LT 2. The signals IN 1 and IN 2 are configured to be input. Then, the logical operation unit 20 outputs one of the signals IN 1 and IN 2 input to the latch circuits LT 1 and LT 2 to H / L (high) of the selection signal SEL input to the latch circuit LT 3. Or row), and transmits to the slave / latch unit 30 for output.

The latches LT 1 and LT 2 of the three latch circuits constituting the latch section 10 have the same configuration as the latch circuit LT 1 constituting the master latch section 10 of the embodiment of FIG. , LT3 has the same configuration as the latch circuit LT2 forming the mask / latch unit 10 of the embodiment of FIG.

The logical operation unit 20 of this embodiment is connected between the output nodes n 1 and η 2 of the latch circuit LT 1 of the master latch unit 10 and one of the input / output nodes η 3 and η 4 of the slave latch unit 30. The connected transmission M〇 SFET Q ρ 11, Q ρ 12, the pair of output nodes η 1, η 2 ′ of the latch circuit LT 2 and the input / output nodes η 3, η 4 of the slave ′ It is composed of transmission MO SFETs Q p 13 and Q 14 connected between them.

The potential of the output node n 12 of the latch circuit LT 3 is applied to the gate terminals of the transmission MOS MOSFETs Q p 11 and Q 12, and the latch circuit LT is applied to the gate terminals of the MOSFETs Qp 13 and Qp 14. The potential of the other output node n 11 of 3 is being input.

As a result, the input signal IN selected according to the H / L (high or low) of the selection signal SEL input to the latch circuit LT3 from the input / output node n3 of the slave latch unit 30. The signal corresponding to either 1 or IN 2 is selected from the input / output node n 4 of the slave latch 30 according to the selection signal SEL H / L input to the latch circuit LT 3 Input signal IN 1 or IN 2 A signal corresponding to each of them will be output.

FIG. 12 illustrates, as an example, a circuit configured to select and output one of two input signals IN 1 and IN 2 using a one-bit selection signal SEL. In accordance with the concept, the latch section 10 is provided with 2 m (m is a positive integer) number of latch circuits in the latch section 10, and selects one of the m input signals according to the m bit selection signal. It is also possible to configure so as to output the data. Also in this embodiment, since the logical operation unit 20 provided between the master latch unit 10 and the slave latch unit 30 is constituted by a transmission MOSFET, the delay due to the logical operation in the logical operation unit 20 is reduced. And the circuit speeds up.

Further, a logic operation unit 20 including a transmission MOS FET provided between the master latch unit 10 and the slave latch unit 30 has a power supply voltage terminal as in a logic gate circuit and a ground potential. Since there is no path through which DC current flows, low power consumption is achieved.

Figures 13 (A) and (B) show equivalent circuits that represent the functions of the circuit in Figure 12 using a conventional logic gate circuit. That is, the circuit of this embodiment has a configuration in which latch circuits LT1, LT2, and LT3 are arranged in front of the logical operation circuit 20 as shown in FIG. 13A, or a logical operation circuit as shown in FIG. This is equivalent to the arrangement in which the slave's latch 30 is arranged after 20. When a similar logic function is implemented in a conventional logic circuit, a master-latch circuit and a slave-latch circuit are placed before and after the logical operation circuit, as in the case of Fig. 2 (C). Is provided.

As is clear from FIGS. 13 (A), (B) and FIG. 2 (C), in the conventional circuit, the gate delay in the logic operation circuit cannot be ignored and the delays of the preceding and following latch circuits are not significant. On the other hand, in the flip-flop circuit of this embodiment, the delay (output delay or input delay) in the logic operation circuit section is theoretically “0”, so that the delay of the entire circuit is latched. Since it is reduced to one stage, it can be seen that the speed is greatly increased.

Furthermore, the circuit of the embodiment of FIG. The circuit's resistance to delay is also improved compared to conventional circuits. FIG. 14 shows a timing chart of the circuit of the embodiment shown in FIG. 12, and FIG. 15 shows a timing chart of the circuit shown in FIG. Here, FIG. 16 shows a conventional type multiplexer circuit using a logic gate circuit having the same function as the circuit of the embodiment of FIG. 12, and its equivalent circuit is shown in FIG. become. FIGS. 14 and 15 show a case where the input delay time D LY i of the selection signal SEL is longer than 周期 of the cycle of the clock CLK.

In FIG. 14, the input signal IN1 or IN2 appears at the output OUT in accordance with the high / low of the selection signal SEL, which indicates that the output signal OUT is normally output. On the other hand, in FIG. 15, the output OUT is not determined according to the high / low of the selection signal SEL, and it can be seen that the circuit malfunctions. The reason for this is that noise due to hazards (hatched in Fig. 15) appears in the signals SELL atch, / SELL ateh, which are the outputs of NOR gates G 1 and G 2 in the circuit of Fig. 16. is there.

As can be seen from a comparison between FIG. 14 and FIG. 15, in the circuit of FIG. 12, the input delay time DLY i of the selection signal SEL is represented by the hold time of the selection signal SEL thd and the setup time by thd. Assuming that tst and the cycle of the clock CLK are Tc, the input delay time DLYi of the selection signal SEL should be in the range of thd <DLYi <(Tc-tst). If the input delay time DLY i of the selection signal SEL does not satisfy t hd, DLY i, and T c / 2, a malfunction occurs. From this, it can be seen that the circuit of the embodiment of FIG. 12 has improved resistance of the circuit to the input delay of the selection signal SEL compared to the circuit of the conventional circuit of FIG.

FIG. 18 shows an embodiment of a flip-flop circuit in which a logical operation unit 20 having a demultiplexer function is provided between the master latch unit 10 and the slave latch unit 30.

In the circuit of this embodiment, the master latch unit 10 includes two latch circuits LT1 and LT3, of which the selection signal SEL is supplied to LT3 and the input signal IN1 is supplied to LT1. The slave latch section 30 includes two latch circuits SLT1 and SLT2. Then, the logical operation unit 20 selects the signal IN1 input to the latch circuit LT1 according to the H / L (high or low) of the selection signal SEL input to the latch circuit LT3. The slave is configured to transmit the signal to one of the latch circuits SLT1 and SLT2 of the latch unit 30 and output the signal.

LT 1 of the two latch circuits constituting the master / latch section 10 has the same configuration as the latch circuit LT 1 constituting the master / latch section 10 of the embodiment of FIG. It has the same configuration as the latch circuit LT3 forming the mask / latch unit 10 of the embodiment of FIG.

The logical operation unit 20 of this embodiment includes an output node n 1 of the latch circuit LT 1 of the master latch unit 10 and one of the input / output nodes n of the latch circuits SLT 1 and SLT 2 of the slave latch unit 30. 3, n 4 ′ connected between the transmission M 0 SFETs Qp 31 and Qp 38, the other output node n 2 of the latch circuit LT 1 and the latch circuits S LT 1 and S LT 2 of the slave-latch unit 30 The transmission MO SFETs Q p32 and Qp 37 connected between the other input / output nodes n 4 and n 3, one output node nl of the latch circuit LT 1 and the latch circuit SLT of the slave latch unit 30 The transmission MOSFET Qp35 connected in series with the transmission MO SFETQ p31 between the input / output node n3 of the first node and the other output node n2 of the latch circuit LT1 and the slave latch section 30 Latch circuit A transmission MO SFET Qp36 connected in series with the transmission MOSFET Qp32 between the input / output node n4 of the SLT 1 and a latch circuit The transmission MOSFE T Qp 33 connected in series with the transmission MO SFET Qp 37 between the output node n2 of LT 1 and the latch circuit 30 of the slave latch unit 30 and the input / output node n 3 ′ of SLT 2, and the latch circuit The transmission MO SFEQ p 3 4 connected in series with the above-mentioned transmission MO S FE TQ p 38 between the output node n 1 of LT 1 and the input / output node n 4 of the slave ′ latch section 30 SLT 2 It is composed of The gate terminals of the transmission M〇S FET Qp 31 to Qp 34 store the potential of the output node nl 2 of the latch circuit LT 3 in the master latch 10, and the MOS FET TQ p 3 The potential of the other output node nl1 of the latch circuit LT3 is input to the gate terminals of 5 to Qp38.

As a result, according to the selection signal SEL H / L (high or low) input to the latch circuit LT3, the input signal is applied to one of the latch circuits SLT1 and SLT2 of the slave 'latch unit 30. IN 1 is transmitted, and the corresponding signal is output.

FIG. 18 shows an example in which one of the two latch circuits SLT 1 and SLT 2 of the slave latch unit 30 is selected by a one-bit selection signal SEL, and the input signal IN 1 is transmitted. The circuit configured to output the data is described, but according to the same concept, the slave latch unit 30 is provided with 2 m (m is a positive integer) number of latch circuits, and the m-bit It is also possible to select one of the m latch circuits by a selection signal, transmit the input signal, and output it.

Also in this embodiment, since the logical operation unit 20 provided between the master / latch unit 10 and the slave's latch unit 30 is constituted by a transmission MOS FET, the logical operation in the logical operation unit 20 is performed. As a result, the speed of the circuit is increased.

In addition, a logic operation unit 20 composed of a transmission MOSFET provided between the master latch unit 10 and the slave latch unit 30 is connected to a power supply voltage terminal as in a logic gate circuit. Since there is no path through which DC current flows toward the ground potential, low power consumption is achieved.

FIG. 19 shows an equivalent circuit in which the functions of the circuit of FIG. 18 are represented using a conventional logic gate circuit. That is, the circuit of this embodiment is equivalent to a circuit in which the latch circuits SLT 1 and SLT 2 are arranged after the logical operation circuit 20 as shown in FIG. In addition, when a similar logic function is realized in a conventional logic circuit, the case of FIG. Similarly, a master latch circuit and a slave latch circuit are provided before and after the logical operation circuit, respectively.

As is clear from FIGS. 19 and 2 (C), in the conventional circuit, the gate delay in the logical operation circuit cannot be ignored and the delays of the preceding and following latch circuits are added. In the flip-flop circuit of the present embodiment, the input delay in the logical operation circuit section is theoretically “0”, so that the delay of the entire circuit is reduced to one stage of the latch, so that the speed can be greatly increased. I understand.

Figure 20 shows a composite logic function that cannot be configured without cascading multiple logic gate circuits, such as NOR and NAND, between the master / latch unit 10 and the slave / latch unit 30 with the conventional technology. Another embodiment of a flip-flop circuit provided with a logical operation unit 20 having the following is shown.

In the circuit of this embodiment, the master latch unit 10 includes four latch circuits LT1, LT2, LT3, and LT4 so that four types of signals A, B, INI, and IN2 are input. The slave / latch unit 30 is composed of one latch circuit. Then, the logical operation unit 20 transmits transmissions MO SFETQ p11 to Qp14 that enable the signals IN1 and IN2 input to the latch circuits LT3 and LT4 to be transmitted to the slave latch unit 30; Transmission MO SFETs Qp41 and Qp43 for precharging the gate terminals of MO SFETs Qpll to Qp14, MOS FET Qp43 for equalization, and signal B or power supply voltage input to latch circuit LT1 (Vdd, Vss) can be transmitted to the gate terminals of the transmission MOSFETs Q11 to Qp14. The transmission MOSFETs Qnll to Qn14 are provided. The gate terminal is controlled by an input signal A to the latch circuit LT2.

The LT 3 and LT 4 of the four latch circuits constituting the master latch unit 10 in FIG. 20 have the same configuration as the latch circuit LT 3 constituting the master latch unit 10 in the embodiment of FIG. LT 1 in FIG. 20 is constituted by a MOS SFET having a conductivity type opposite to that of the latch circuit LT 1 constituting the mask latch 10 of the embodiment of FIG. LT 2 has the same configuration as the latch circuit LT 2 constituting the master's latch section 10 of the embodiment of FIG.

As a result, the flip-flop circuit of FIG. 20 takes an output state as shown in the following truth table (Table 1) with respect to changes in the input signals A, B, IN1, IN2 and the clock CLK. Works like that. In Table 1, “UT = OUT0” indicates that the output is a value captured at the rising edge of the clock CLK.

table 1

Also in this embodiment, since the logical operation unit 20 provided between the master / latch unit 10 and the slave's latch unit 30 is configured by the transmission MOS FET, the logical operation by the logical operation unit 20 There is no delay, and the circuit speeds up. FIG. 22 shows the operation timing of the circuit of FIG. From the timing chart of FIG. 22, it can easily be seen that the output delay of the flip-flop circuit of FIG. 20 is extremely small.

In addition, a logical operation unit 20 composed of a transmission MOS FET provided between the master / latch unit 10 and the slave / latch unit 30 has a power supply voltage terminal as in a logic gate circuit and a ground potential. Since there is no path through which direct current flows, low power consumption is achieved.

Figures 21 (A) and (B) show the functions of the circuit in Figure 20 using a conventional logic gate circuit. The equivalent circuit is shown below. That is, the circuit of this embodiment has a configuration in which latch circuits LT1, LT2, LT3, and LT4 are arranged in front of the logical operation circuit 20 as shown in FIG. This is equivalent to the case where the slave-latch 30 is arranged at the subsequent stage of the logical operation circuit 20 as shown in FIG. When a similar logic function is implemented in a conventional logic circuit, a master latch circuit and a slave latch circuit are provided before and after the logic operation circuit, respectively, as in the case of FIG. 2 (C). Is provided.

As is clear from Figs. 21 (A), (B) and Fig. 2 (C), in the conventional circuit, the gate delay in the logical operation circuit cannot be ignored and the delay of the latch circuit before and after In the flip-flop circuit of the present embodiment, the delay (output delay or input delay) in the logic operation circuit portion is theoretically “0”, so that the delay of the entire circuit is one stage of the latch. It can be seen that the speed is greatly increased.

Next, an application example of the flip-flop circuit with a logic function of the previous embodiment will be described.

Figure 23 shows

w w

H (zl, z2) = 1 / (1-∑ ∑c (nl, η2) ΧζΓ (-ηΙ) Χζ2 (-η2))

η1 = 0 η2 = 0

If w = l, c (nl, η2) = 0.5 for any nl, n2,

y (nl, n2) = x (nl, n2) + 0.5X {y (nl-1, n2) + y (nl, n2-1)}

+ 0.5Xy (nl-l, n2-1)

The code segment for this is

for k = 0, Μ-1

for j = 0,, Μ-1

A: yl (j, k) = y (j, k-l) + y (j-l, k-1)

B: y2 (j, k) = yl (j, k) + y (j-l, k)

C: y3 (j, k) = 0.5y2 (j, k)

D: A well-known method of performing image processing over time to obtain filtered image data in accordance with an arithmetic expression of y (j, k) = y3 (j, k) + x (j, k). FIG. 23 shows the configuration of the filter circuit for 6 × 16 pixel binary image <In FIG. 23, M in the above arithmetic expression is set to 16, and in FIG. 23, REG 1 to REG 10 are each 16-bit data. Regis evening that can hold evenings, FI FO 1 ~: FI FO 3 is a first-in-first-out MUX 1 and MUX 2 are multiplexers, DEMUX 1 and D EMUX 2 are demultiplexers, H-ADD1, H-ADD2 are half adders, F-ADD is full adders, and SFT. Is the left 1-bit shifter.

FIG. 24 shows an embodiment in which the filter circuit shown in FIG. 23 is configured using the flip-flop circuit with a logic function of the above embodiment. In FIG. 24, the circuit portion surrounded by the broken line with the reference sign FAF is configured by the flip-flop circuit with full addition function shown in FIG. 8, and the broken line with the reference sign FA-FF is used. The circuit part enclosed by the flip-flop circuit with full addition function shown in Fig. 8 is composed of the flip-flop circuit shown in Fig. 8. The circuit part enclosed by the broken line with HA-FF is shown in Fig. 10. The flip-flop circuit with the half-addition function shown is shown in FIG. 12, and the circuit parts enclosed by broken lines with the symbols MUX-FF1 and MUX-FF2 are shown in FIG. The circuit part enclosed by the broken line with the symbol DE MUX-FF is configured by the flip-flop circuit with the demultiplexer function shown in FIG. That means.

The circuits other than these circuit units have the same circuit format as the conventional one. However, instead of configuring the circuit portion enclosed by the dashed line labeled MUX-FF1 with the flip-flop circuit with the multiplexer function shown in FIG. 12, the circuit portion enclosed by the one-dot chain line It is also possible to use a flip-flop circuit with a demultiplexer function shown in FIG.

As described above, by configuring the filter circuit shown in FIG. 23 using the flip-flop circuit with the logic function of the above-described embodiment, it is possible to achieve high speed and low power consumption of each circuit portion. According to the verification of the present inventor, the delay time in the circuit portion using the flip-flop circuit of the above embodiment in the filter circuit of FIG. 24 is the half adder H-ADD1, ADD 1 in the conventional filter circuit of FIG. Since the delay time of the H-ADD2 alone is reduced to about the same level, it was found that the operating frequency (the frequency of the clock CLK of the embodiment) can be doubled as a whole circuit. The power consumption of the filter circuit of Fig. 24 is expected to be reduced by about 20% compared to the power consumption of the filter circuit of Fig. 23.

Further, the flip-flop circuit with a logic function according to the present invention is designed in advance by designing flip-flop circuits having various logics as shown in the above-described embodiment, and using them in a circuit cell constituting a semiconductor integrated circuit. One of these is to register it in a database called a cell library, and then select and use the desired function from the cell library when designing a logic integrated circuit. Large-scale semiconductor integrated circuits) can be designed efficiently. FIG. 25 shows a procedure for designing an LSI using the data of the flip-flop circuit that has been made into a cell library as described above. Designers design LSIs with the desired functions at the functional level, describe them in HDL (hardware 'disk review' language), and write them on CD (optical disk) or MO (magneto-optical disk). Save to a file FL 1 (step S 1). Next, data of a flip-flop circuit of the type used for the LSI designed in step S1 is read from a file FL2 such as a CD or MO in which the cell library is stored, and stored in the file FL1. Perform logic synthesis with the design data described in the HDL description (step S2). Thereafter, a netlist indicating the connection relationship at the logic gate level is created using the synthesized data (step S3), and a pattern is designed based on this netlist (step S4). ). The logic synthesis in step S2, the creation of the netlist in step S3, and the pattern design in step S4 are provided using dedicated design tools. It can be efficiently executed on the evening. Industrial applicability

In the above description, the case where the invention made by the present inventor is mainly applied to a binary image filter has been described. However, the present invention is not limited to this, and is generally applied to logic circuits having a built-in flip-flop circuit. Can be widely used.

Claims

The scope of the claims

1. A master / latch circuit that operates based on a clock signal, a slave / latch circuit that performs a latch operation without using a clock signal, and a master / latch circuit.

A flip-flop circuit comprising: a logic operation circuit configured by a transmission MOS transistor provided between the logic circuit and the latch circuit.

2. The master 'latch circuit includes a differential input transistor pair whose source terminals are commonly connected to each other, and a clock signal connected between the common source terminal and the power supply voltage terminal of the differential input transistor. 2. The flip-flop circuit according to claim 1, wherein the flip-flop circuit is a differential latch circuit including a MOS transistor applied to one terminal.

3. In the master latch circuit, a transistor for precharging or discharging, which is turned on and off by a clock signal, is connected to an output node thereof, and the transistor is turned on or off. 3. The flip-flop circuit according to claim 1, wherein the transmission transistor is turned off so that the slave latch circuit is in a signal holding state.

4. The slave latch circuit has two impellers each including a p-channel MOS transistor and an n-channel MOS transistor connected in series between a first reference potential point and a second reference potential point. 4. The flip-flop circuit according to claim 1, wherein the input / output terminals of these amplifiers are cross-coupled to each other.

5. The flip-flop circuit according to claim 1, wherein the mass latch circuit is configured to latch three or more input signals.

6. The flip-flop circuit according to claim 1, wherein the slave latch circuit is configured to output two or more output signals.

7. The above logic operation circuit is the master. ■ Transmits the output of the latch circuit to the slave latch circuit. A first transmission means comprising a transmission MOS transistor which reaches or cuts off, and a transmission MOS transistor for transmitting or cutting off the output of the master / latch circuit to the gate terminal of the transmission MOS transistor which constitutes the first transmission means. 7. The flip-flop circuit according to claim 1, wherein the flip-flop circuit is constituted by a second transmission means comprising:

8. A semiconductor integrated circuit comprising the flip-flop circuit according to claim 1, 2, 3, 4, 5, 6, or 7.