JPH05308102A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH05308102A JPH05308102A JP4084314A JP8431492A JPH05308102A JP H05308102 A JPH05308102 A JP H05308102A JP 4084314 A JP4084314 A JP 4084314A JP 8431492 A JP8431492 A JP 8431492A JP H05308102 A JPH05308102 A JP H05308102A
- Authority
- JP
- Japan
- Prior art keywords
- electrode wiring
- film
- contact hole
- semiconductor device
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000000034 method Methods 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- 239000011229 interlayer Substances 0.000 claims description 9
- 238000000206 photolithography Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 2
- 238000009792 diffusion process Methods 0.000 abstract description 6
- 239000012535 impurity Substances 0.000 abstract description 6
- 230000001788 irregular Effects 0.000 abstract description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特に多層配線構造を有する半導体装置の電極配線
の形成方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming electrode wiring of a semiconductor device having a multilayer wiring structure.
【０００２】[0002]
【従来の技術】半導体チップ上に形成されたアルミニウ
ム等の導電膜を、フォトリソグラフィー技術を用いて、
所定のパターンの電極配線に加工する場合、フォトレジ
スト膜のパターンはレチクル（フォトマスク）上に描画
された遮光膜パターンを忠実に再現することが望まし
い。ところがアルミニウム等の導電膜は反射率が高いた
め、導電膜の下地に段差や傾斜がある場合には、光の反
射により、エッチングの際のマスクとなるフォトレジス
ト膜が、レチクル上の遮光膜パターンどおりに形成でき
ない。例えば、図２，図３に示すようにシリコン基板１
４に選択的に形成された不純物拡散層１と第１層電極配
線２とを電気的に接続するために形成されるコンタクト
孔Ｃの上部を通る一定幅の第２層電極配線３を形成しよ
うとする場合、フォトレジスト膜８を露光するＵＶ光
は、アルミニウム膜７の表面で反射するが、特に傾斜部
矢印Ｌで示すように散乱される。そのため、図４に示す
ように、現像後に残るフォトレジスト膜８Ａをマスクと
してエッチングされる第２層電極配線３ａの形状は、コ
ンタクト孔Ｃの上方とその近傍でレチクル（フォトマス
ク）上に描画されている遮光膜パターン（図２の第２層
電極配線３に対応する一定幅のストライプ）よりも細く
なる。従来は、このような反射による影響を防ぐため、
導電膜の表面に反射防止膜を形成している。ところが、
このような反射防止膜の形成は製造工程を長くし、また
このような反射防止膜を使用しても、反射による配線の
細りを十分におさえることはできない。2. Description of the Related Art A conductive film such as aluminum formed on a semiconductor chip is formed by photolithography.
When processing the electrode wiring of a predetermined pattern, it is desirable that the pattern of the photoresist film faithfully reproduces the light-shielding film pattern drawn on the reticle (photomask). However, since the conductive film of aluminum or the like has a high reflectance, when there is a step or an inclination in the base of the conductive film, the photoresist film serving as a mask at the time of etching due to the reflection of light is replaced with the light-shielding film pattern on the reticle. It cannot be formed as it is. For example, as shown in FIGS. 2 and 3, a silicon substrate 1
4 to form the second layer electrode wiring 3 having a constant width which passes over the contact hole C formed to electrically connect the impurity diffusion layer 1 selectively formed to the first layer electrode wiring 2 In this case, the UV light that exposes the photoresist film 8 is reflected by the surface of the aluminum film 7, but is scattered especially as indicated by the slanted portion arrow L. Therefore, as shown in FIG. 4, the shape of the second-layer electrode wiring 3a that is etched by using the photoresist film 8A that remains after development as a mask is drawn on the reticle (photomask) above and in the vicinity of the contact hole C. The light-shielding film pattern (a stripe having a constant width corresponding to the second-layer electrode wiring 3 in FIG. 2) has a smaller width. Conventionally, in order to prevent the influence of such reflection,
An antireflection film is formed on the surface of the conductive film. However,
The formation of such an antireflection film lengthens the manufacturing process, and even if such an antireflection film is used, it is not possible to sufficiently suppress the thinning of wiring due to reflection.
【０００３】[0003]
【発明が解決しようとする課題】上述したように、従来
の半導体装置の製造方法では、電極配線用の導電膜表面
の段差部および傾斜部（コンタクト孔上方に形成され
る）で、露光に用いられるＵＶ光が反射し、現像後のフ
ォトレジスト膜の形状およびそのフォトレジスト膜をマ
スクとするエッチングで形成される電極配線が細くなる
のを防ぐため、導電膜の表面に反射防止膜を形成してい
る。そのため、製造工程が長くなること、およびこのよ
うな反射防止膜を使用しても必ずしも反射防止の効果が
十分でないために結局電極配線が局所的に細くなるとい
う欠点を有している。As described above, in the conventional method for manufacturing a semiconductor device, the stepped portion and the inclined portion (formed above the contact hole) on the surface of the conductive film for electrode wiring are used for exposure. An antireflection film is formed on the surface of the conductive film in order to prevent the generated UV light from being reflected and thinning the shape of the photoresist film after development and the electrode wiring formed by etching using the photoresist film as a mask. ing. Therefore, it has a drawback that the manufacturing process becomes long and that even if such an antireflection film is used, the antireflection effect is not always sufficient, so that the electrode wiring is locally thinned.
【０００４】[0004]
【課題を解決するための手段】本発明は、コンタクト孔
を有する層間絶縁膜を選択的に被覆する所定層次の電極
配線を形成したのち、他の層間絶縁膜を堆積し、導電膜
を堆積し、ポジ型フォトレジスト膜を使用するフォトリ
ソグラフィー技術により前記導電膜を上層電極配線にパ
ターニングする工程を有する半導体装置の製造方法にお
いて、前記コンタクト孔の上方で他の部分より太い幅の
遮光膜を有するフォトマスクを用いて露光するというも
のである。According to the present invention, after forming an electrode wiring of a predetermined layer which selectively covers an interlayer insulating film having a contact hole, another interlayer insulating film is deposited and a conductive film is deposited. In a method of manufacturing a semiconductor device including a step of patterning the conductive film into an upper electrode wiring by a photolithography technique using a positive photoresist film, a light shielding film having a width wider than other portions is provided above the contact hole. Exposure is performed using a photomask.
【０００５】[0005]
【実施例】図３に示すように、シリコン基板４の表面部
に選択的に不純物拡散層１を形成し、層間絶縁膜５を形
成し、不純物拡散層１の上部にコンタクト孔Ｃを開孔
し、第１層電極配線２を形成し、更に他の層間絶縁膜６
を堆積し、アルミニウム膜７を堆積し、フォトレジスト
膜８を塗布する。ここまでは、従来公知のプロセスであ
る。EXAMPLE As shown in FIG. 3, an impurity diffusion layer 1 is selectively formed on the surface of a silicon substrate 4, an interlayer insulating film 5 is formed, and a contact hole C is formed on the impurity diffusion layer 1. Then, the first layer electrode wiring 2 is formed, and further another interlayer insulating film 6 is formed.
Is deposited, an aluminum film 7 is deposited, and a photoresist film 8 is applied. The process up to this point is a conventionally known process.
【０００６】次に、図１（ａ）に示すように、遮光膜パ
ターン１０を有するフォトマスクを用いて露光する。遮
光膜パターン１０は、幅広部（幅Ｙ）を有するストライ
プ（幅Ｘ）状になっていて、その幅広部がコンタクト孔
Ｃの上部にくるようにフォトマスクが設置される。次い
で、現像を行ない、残されたフォトレジスト膜をマスク
としてアルミニウム膜７のパターニングを行なう。そう
すると、図１（ｂ）に示すように、幅がほぼ一定の第２
層電極配線３ｂが形成される。コンタクト孔Ｃ上部の段
差によるＵＶ光の乱反射による影響が補正されるからで
ある。Next, as shown in FIG. 1A, exposure is performed using a photomask having a light shielding film pattern 10. The light-shielding film pattern 10 has a stripe (width X) shape having a wide portion (width Y), and the photomask is installed so that the wide portion is located above the contact hole C. Next, development is performed, and the aluminum film 7 is patterned using the remaining photoresist film as a mask. Then, as shown in FIG. 1 (b), the second
The layer electrode wiring 3b is formed. This is because the influence of irregular reflection of UV light due to the step above the contact hole C is corrected.
【０００７】例えば、コンタクト孔Ｃの大きさが１．２
μｍ×１．２μｍ、層間絶縁膜５３、電極配線２、層間
絶縁膜６およびアルミニウム膜７の厚さがそれぞれ６０
０ｎｍ，２００ｎｍ，７００ｎｍおよび１０００ｎｍと
し、幅３μｍの第２層電極配線３ｂを形成する場合、遮
光膜パターン１０の幅広部の寸法Ｙは、寸法Ｘの４／３
にすればよい。For example, the size of the contact hole C is 1.2.
μm × 1.2 μm, the thickness of the interlayer insulating film 53, the electrode wiring 2, the interlayer insulating film 6 and the aluminum film 7 is 60 each.
When the second-layer electrode wiring 3b having a width of 3 μm is formed with 0 nm, 200 nm, 700 nm, and 1000 nm, the dimension Y of the wide portion of the light shielding film pattern 10 is 4/3 of the dimension X.
You can do this.
【０００８】遮光膜パターンの幅が一定の部分より両側
にそれぞれ一定寸法ｄずつ広げた場合について説明した
が、電極配線のレイアウト上の制約があってそうするこ
とが困難な場合は、いずれか片一方に寸法ｄないし２ｄ
だけ広げるようにしても、ある程度電極配線の幅の不均
一を防止することができる。The case where the width of the light-shielding film pattern is expanded by a constant dimension d on both sides from a constant width portion has been described, but when it is difficult to do so due to the layout limitation of the electrode wiring, either one of them is cut. One dimension d to 2d
Even if the width is widened only, it is possible to prevent the width of the electrode wiring from being nonuniform.
【０００９】[0009]
【発明の効果】以上説明したように本発明は所定層次の
電極配線と下層の導電領域（不純物拡散層または下層電
極配線）とを電気的に形成するのに、下方にコンタクト
ホールの存在する領域でコンタクトホールの存在しない
領域よりも幅が広くなっている遮光膜を有するフォトマ
スクを使用することにより、露光用のＵＶ光の乱反射に
よる電極配線の局所的な細りを防止することができると
いう効果を有する。As described above, according to the present invention, in order to electrically form the electrode wiring next to the predetermined layer and the lower conductive area (impurity diffusion layer or lower electrode wiring), the area where the contact hole exists below is formed. By using a photomask having a light-shielding film whose width is wider than the area where the contact hole does not exist, it is possible to prevent local thinning of the electrode wiring due to irregular reflection of UV light for exposure. Have.
【図１】本発明の一実施例の説明に使用するため
（ａ），（ｂ）に分図して示す工程順平面図である。FIG. 1 is a plan view in order of steps, which is divided into (a) and (b) for use in describing an embodiment of the present invention.
【図２】本発明の説明に使用する平面図である。FIG. 2 is a plan view used for explaining the present invention.
【図３】本発明の説明に使用する露光工程における半導
体チップの断面図である。FIG. 3 is a cross-sectional view of a semiconductor chip in an exposure process used for explaining the present invention.
【図４】従来の技術による欠点を示す平面図である。FIG. 4 is a plan view showing a drawback of the conventional technique.
１ 不純物拡散層 ２ 第１層電極配線 ３，３ａ，３ｂ 第２層電極配線 ４ シリコン基板 ５，６ 層間絶縁膜 ７ アルミニウム膜 ８，８Ａ フォトレジスト膜 ９ 非露光領域 １０ 遮光膜パターン Ｃ コンタクト功 1 Impurity Diffusion Layer 2 First Layer Electrode Wiring 3, 3a, 3b Second Layer Electrode Wiring 4 Silicon Substrate 5, 6 Interlayer Insulation Film 7 Aluminum Film 8, 8A Photoresist Film 9 Non-Exposure Area 10 Light-Shielding Film Pattern C Contact Effectiveness
Claims (1)
的に被覆する所定層次の電極配線を形成したのち、他の
層間絶縁膜を堆積し、導電膜を堆積し、ポジ型フォトレ
ジスト膜を使用するフォトリソグラフィー技術により前
記導電膜を上層電極配線にパターニングする工程を有す
る半導体装置の製造方法において、前記コンタクト孔の
上方で他の部分より太い幅の遮光膜を有するフォトマス
クを用いて露光することを特徴とする半導体装置の製造
方法。1. A positive photoresist film is used by depositing another interlayer insulating film and then depositing a conductive film after forming an electrode wiring of a predetermined layer which selectively covers the interlayer insulating film having a contact hole. In the method for manufacturing a semiconductor device, which comprises a step of patterning the conductive film into an upper electrode wiring by a photolithography technique, exposing using a photomask having a light shielding film having a width wider than other portions above the contact hole. A method for manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4084314A JPH05308102A (en) | 1992-04-07 | 1992-04-07 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4084314A JPH05308102A (en) | 1992-04-07 | 1992-04-07 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05308102A true JPH05308102A (en) | 1993-11-19 |
Family
ID=13827051
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4084314A Withdrawn JPH05308102A (en) | 1992-04-07 | 1992-04-07 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05308102A (en) |
-
1992
- 1992-04-07 JP JP4084314A patent/JPH05308102A/en not_active Withdrawn
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990608 |