JPS63292649A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63292649A JPS63292649A JP12890787A JP12890787A JPS63292649A JP S63292649 A JPS63292649 A JP S63292649A JP 12890787 A JP12890787 A JP 12890787A JP 12890787 A JP12890787 A JP 12890787A JP S63292649 A JPS63292649 A JP S63292649A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- silicon layer
- wiring layer
- photolithography
- light
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 20
- 239000010703 silicon Substances 0.000 claims abstract description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 238000000206 photolithography Methods 0.000 claims abstract description 12
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 10
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 150000003376 silicon Chemical class 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 48
- 230000002159 abnormal effect Effects 0.000 abstract description 9
- 239000011229 interlayer Substances 0.000 abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 6
- 238000001020 plasma etching Methods 0.000 abstract description 3
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 230000010354 integration Effects 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000003631 wet chemical etching Methods 0.000 description 1
Landscapes
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、多層配線構造を形成した後、各配線眉間の接
続用コンタクト孔を形成する半導体装置の製造方法に関
する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor device in which a multilayer wiring structure is formed and then contact holes for connection between the eyebrows of each wiring are formed.
第２図（ａ）乃至（ｃ）は、多層配線構造を有する半導
体装置の従来の製造方法を示す断面図である。半導体基
板１１上に、眉間絶縁膜１２を形成し、眉間絶縁膜１２
上に第１の配線層１３を形成する。次いで、この配線層
１３との間に眉間絶縁膜１４を配設した後、第２の配線
層１５を形成する。FIGS. 2(a) to 2(c) are cross-sectional views showing a conventional manufacturing method of a semiconductor device having a multilayer wiring structure. A glabellar insulating film 12 is formed on the semiconductor substrate 11.
A first wiring layer 13 is formed thereon. Next, after disposing a glabellar insulating film 14 between the wiring layer 13 and the wiring layer 13, a second wiring layer 15 is formed.
従来、このようにして形成された多層配線構造を有する
半導体装置において、各配線層間を接続するためには、
第２図（ａ）に示すように、先ず配線層１５を形成した
後、層間絶縁膜１６を形成する。次いで、第２図（ｂ
、）に示すように、この絶縁Ｍ１６上にフォトレジスト
１８を塗布し、光１９を照射してフォトリソグラフィ技
術によりコンタクト孔のパターンを描画する。そして、
ウェットケミカルエツチング又はプラズマエツチングに
より、露光領域２０に、第２図（ｃ）に示すように、コ
ンタクト孔２４を開孔する。このコンタク１〜孔２４に
金属を埋め込むことにより、下層配線層］５が電気的に
導出される。Conventionally, in a semiconductor device having a multilayer wiring structure formed in this way, in order to connect each wiring layer,
As shown in FIG. 2(a), first, a wiring layer 15 is formed, and then an interlayer insulating film 16 is formed. Next, Figure 2 (b
, ), a photoresist 18 is coated on the insulating layer M16, and a contact hole pattern is drawn by photolithography by irradiating the photoresist 18 with light 19. and,
A contact hole 24 is formed in the exposed region 20 by wet chemical etching or plasma etching, as shown in FIG. 2(c). By filling the contacts 1 to 24 with metal, the lower wiring layer 5 is electrically led out.
しかしながら、下層（内部）配線層］５を金属シリサイ
ド又は金属で形成した場合には、フォトリソグラフィ工
程において光１つを照射すると、第２図り１〕）に示す
ように、この配線層１５の表面でこの光が反射する。そ
して、この配線層１５が、第２図（ｂ）に示すように、
段差を有するときには、この段差からの反射光２２によ
り、フォトレジスト］８が、異常露光を受ける。つまり
、コンタクト孔２４のパターンが、異常露光領域２１に
広がってパターニングされてしまう。このため、コンタ
ク１へ孔２４は、第２図（ｃ）に示すように、光１９の
直接露光領域２０の外に、異常露光領域２１にまで拡大
して形成されてしまう。However, when the lower (inner) wiring layer] 5 is formed of metal silicide or metal, when one light beam is irradiated in the photolithography process, the surface of this wiring layer 15 appears as shown in the second diagram 1]). This light is reflected. Then, as shown in FIG. 2(b), this wiring layer 15 is
When there is a step, the photoresist] 8 is subjected to abnormal exposure due to the reflected light 22 from the step. In other words, the pattern of the contact hole 24 is patterned to spread into the abnormally exposed region 21 . For this reason, the hole 24 in the contact 1 is formed outside the direct exposure area 20 of the light 19 to extend into the abnormal exposure area 21, as shown in FIG. 2(c).
従って、従来、コンタクト孔２４と下層配線層１５との
マージンは、この異常露光を見込んだ広さにするか、又
は、段差が存在する部分にはコンタクト孔の開孔を禁止
する等の制約を設けることが必要となる。このため、こ
の段差に起因する異常露光が半導体装置の高集積化を阻
害するという問題点がある。Therefore, conventionally, the margin between the contact hole 24 and the lower wiring layer 15 has been set to a width that takes into account this abnormal exposure, or restrictions such as prohibiting the formation of contact holes in areas where there are steps have been imposed. It is necessary to provide Therefore, there is a problem in that abnormal exposure caused by this step impedes higher integration of semiconductor devices.
本発明は、かかる事情に鑑みてなされたものであって、
内部配線層が段差を有することに起因する異常露光によ
る露光パターンの広がりを防止し、高密度化及び高集積
化が可能の半導体装置の製造方法を提供することを目的
とする。The present invention has been made in view of such circumstances, and
It is an object of the present invention to provide a method for manufacturing a semiconductor device that prevents the spread of an exposure pattern due to abnormal exposure due to an internal wiring layer having a step and that enables high density and high integration.
本発明に係る半導体装置の製造方法は、半導体基板上に
配線層を形成する工程と、この配線層上に絶縁膜を被着
する工程と、この絶縁膜上にシリコン層を被着する工程
と、このシリコン層上にレジストを塗布してフォトリソ
グラフィにより前記絶縁膜にコンタクト孔を開孔する工
程と、を有することを特徴とする。A method for manufacturing a semiconductor device according to the present invention includes a step of forming a wiring layer on a semiconductor substrate, a step of depositing an insulating film on the wiring layer, and a step of depositing a silicon layer on the insulating film. The method is characterized by comprising the steps of applying a resist on the silicon layer and forming a contact hole in the insulating film by photolithography.
この発明においては、フォトリソグラフィにおいてレジ
ストを塗布する前に、絶縁膜表面にシリコン層を被着す
る。このため、レジストを塗布した後露光した場合に、
照射光はシリコン層により阻止されて内部配線層にまで
は到達しない。従って、内部配線層が段差を有していて
も、この段差での反射によるレジストの異常露光が発生
しない。In this invention, a silicon layer is deposited on the surface of the insulating film before applying a resist in photolithography. For this reason, when exposing after applying resist,
The irradiated light is blocked by the silicon layer and does not reach the internal wiring layer. Therefore, even if the internal wiring layer has a step, abnormal exposure of the resist due to reflection at the step does not occur.
以下、本発明の実施例について添付の図面を参照して説
明する。Embodiments of the present invention will be described below with reference to the accompanying drawings.
第１−図（ａ）乃至（ｃ）は本発明の実施例を工程順に
示す縦断面図である。FIGS. 1A to 1C are vertical sectional views showing an embodiment of the present invention in the order of steps.
先ず、第１図（２１）に示すように、半導体基板１の」
二に層間絶縁膜２を形成する。そして、第］及び第２の
配線層３，５を、両者間に層間絶縁膜４を配設して形成
する。次いで、配線層５及び絶縁膜４−］二に眉間絶縁
Ｈり６を、その表面が平坦になるように形成する。その
後、この眉間絶縁膜６の」−に、層厚が約５００人であ
るシリコン層７を被着する。First, as shown in FIG. 1 (21), the semiconductor substrate 1 is
Second, an interlayer insulating film 2 is formed. Then, the first and second wiring layers 3 and 5 are formed with an interlayer insulating film 4 disposed therebetween. Next, the wiring layer 5 and the insulating film 4-] and the glabella insulation layer 6 are formed so that the surfaces thereof are flat. Thereafter, a silicon layer 7 having a thickness of about 500 layers is deposited on the glabellar insulating film 6.
次に、第１図（ｂ）に示すように、フォトレジスト８を
シリコンＮ７の全面に塗布し、光りを照射してコンタク
ト孔のパターンをフォトリソグラフィにより描く。次い
で、第１図（Ｃ）に示すように、レジスト８をマスクに
してウェッＩ−ケミカルエツチング又はプラズマエツチ
ングによりシリコン層７及び絶縁膜６を開孔しコンタク
ト孔］０を形成する。次いで、レジスト８を除去した後
、このコンタクト孔］０を埋めるようにして第３の配線
層（図示せず）を形成するに
のようにすれば、第２の配線層５を金属シリサイド又は
アルミニウム等の金属で形成した場合でも、眉間絶縁膜
６をその表面が平坦になるように形成しておくことによ
り、フォトリソグラフィに際して、その光りはシリコン
層７の表面で反射される。このため、従来のように反射
光が横方向に広がることはない。また、シリコン層７は
配線層５の形成材料である金属シリサイドやアルミニウ
ムに比して光を吸収し易い。このため、シリコン層７で
の反射光は極めて弱く、仮に眉間絶縁膜６の表面が十分
に平坦化されておらず、横方向に広がる反射光が存在し
たとしても、これにより解像してしまうことはない。Next, as shown in FIG. 1(b), a photoresist 8 is applied to the entire surface of the silicon N7, and a contact hole pattern is drawn by photolithography by irradiating light. Next, as shown in FIG. 1C, a contact hole 0 is formed in the silicon layer 7 and the insulating film 6 by wet I-chemical etching or plasma etching using the resist 8 as a mask. Next, after removing the resist 8, a third wiring layer (not shown) is formed so as to fill this contact hole 0. Then, the second wiring layer 5 is formed of metal silicide or aluminum. Even when the glabella insulating film 6 is formed with a metal such as metal, by forming the glabella insulating film 6 so that its surface is flat, the light is reflected by the surface of the silicon layer 7 during photolithography. Therefore, the reflected light does not spread laterally as in the conventional case. Furthermore, the silicon layer 7 absorbs light more easily than metal silicide or aluminum, which are the materials for forming the wiring layer 5. Therefore, the reflected light from the silicon layer 7 is extremely weak, and even if the surface of the glabellar insulating film 6 is not sufficiently flattened and there is reflected light that spreads laterally, this will cause resolution. Never.
以上説明したように、本発明においては、シリコン層を
形成した後レジストを塗布してフォトリソグラフィによ
りコンタクト孔を描画するから、内部の配線層（下層の
配線層）が段差を有していても、フォトリソグラフィ時
の異常露光を朋避することができる。従って、この発明
によれば、高密度化及び高集積化された半導体装置を製
造することができる。As explained above, in the present invention, after forming a silicon layer, a resist is applied and contact holes are drawn by photolithography, so even if the internal wiring layer (lower wiring layer) has a step, , abnormal exposure during photolithography can be avoided. Therefore, according to the present invention, a semiconductor device with high density and high integration can be manufactured.
第１図（ａ）乃至（Ｃ）は本発明の実施例を工程順に示
す縦断面図、第２図（ａ’）乃至（ｃ）は従来例を示す
縦断面図である。
１；半導体基板、２，４，６．層間絶縁膜、３；第１の
配線層、５；第２の配線層、７；シリコン層、８；フォ
トレジスト、９；光、１０；コンタクト孔、２０；露光
領域２１；異常露光領域、２２；反射光
−←FIGS. 1(a) to 1(C) are longitudinal sectional views showing an embodiment of the present invention in the order of steps, and FIGS. 2(a') to 2(c) are longitudinal sectional views showing a conventional example. 1; semiconductor substrate, 2, 4, 6. Interlayer insulating film, 3; first wiring layer, 5; second wiring layer, 7; silicon layer, 8; photoresist, 9; light, 10; contact hole, 20; exposure region 21; abnormal exposure region, 22 ;Reflected light−←
Claims (3)
線層上に絶縁膜を被着する工程と、この絶縁膜上にシリ
コン層を被着する工程と、このシリコン層上にレジスト
を塗布してフォトリソグラフィにより前記絶縁膜にコン
タクト孔を開孔する工程と、を有することを特徴とする
半導体装置の製造方法。(1) A process of forming a wiring layer on a semiconductor substrate, a process of depositing an insulating film on this wiring layer, a process of depositing a silicon layer on this insulating film, and a process of depositing a resist on this silicon layer. 1. A method of manufacturing a semiconductor device, comprising the steps of coating and forming contact holes in the insulating film by photolithography.
特徴とする特許請求の範囲第１項に記載の半導体装置の
製造方法。(2) The method for manufacturing a semiconductor device according to claim 1, wherein the silicon layer has a flat surface.
することを特徴とする特許請求の範囲第２項に記載の半
導体装置の製造方法。(3) The method of manufacturing a semiconductor device according to claim 2, wherein the insulating film is formed so that its surface is flat.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12890787A JPS63292649A (en) | 1987-05-25 | 1987-05-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12890787A JPS63292649A (en) | 1987-05-25 | 1987-05-25 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63292649A true JPS63292649A (en) | 1988-11-29 |
Family
ID=14996310
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12890787A Pending JPS63292649A (en) | 1987-05-25 | 1987-05-25 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63292649A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5302538A (en) * | 1992-08-04 | 1994-04-12 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing field effect transistor |
| US5403781A (en) * | 1992-07-17 | 1995-04-04 | Yamaha Corporation | Method of forming multilayered wiring |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6055642A (en) * | 1983-08-12 | 1985-03-30 | コミツサリア タ レネルギ− アトミ−ク | Method of installing connecting wire of integrated circuit |
| JPS62293645A (en) * | 1986-06-12 | 1987-12-21 | Oki Electric Ind Co Ltd | Interconnection forming method for semiconductor device |
| JPS63271957A (en) * | 1987-04-28 | 1988-11-09 | Sony Corp | Formation of multilayer interconnection |
-
1987
- 1987-05-25 JP JP12890787A patent/JPS63292649A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6055642A (en) * | 1983-08-12 | 1985-03-30 | コミツサリア タ レネルギ− アトミ−ク | Method of installing connecting wire of integrated circuit |
| JPS62293645A (en) * | 1986-06-12 | 1987-12-21 | Oki Electric Ind Co Ltd | Interconnection forming method for semiconductor device |
| JPS63271957A (en) * | 1987-04-28 | 1988-11-09 | Sony Corp | Formation of multilayer interconnection |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5403781A (en) * | 1992-07-17 | 1995-04-04 | Yamaha Corporation | Method of forming multilayered wiring |
| US5302538A (en) * | 1992-08-04 | 1994-04-12 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing field effect transistor |
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