JP3017179B1 - Semiconductor integrated circuit device, method of manufacturing the same, and mask - Google Patents

Abstract

An object of the present invention is to reliably form a wiring layer in a contact portion and improve reliability. A first contact portion formed on a wafer is provided.
The wiring layer 1 is formed so as to cover a portion where the width of the wiring layer 1 changes with a second wiring layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a contact portion in which a wiring width is different at a boundary portion between a wiring portion of a lower wiring layer and a contact portion, and a portion where a concave shape or a hook shape can be formed in the lower wiring layer is formed as an upper wiring layer. The present invention relates to a semiconductor integrated circuit device, a method of manufacturing the same, and a mask covered with a mask.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device, a pattern drawn on a reticle is transferred to a photoresist coated on a wafer by exposure, and then etching or the like is performed based on the photoresist pattern formed by exposure. It is formed by this.

FIG. 5 is a plan view showing a contact portion of a semiconductor integrated circuit device. The contact portion includes a contact hole 3 that electrically connects the first wiring layer 1 and the second wiring layer 2. The contact portion is formed with a margin of dimensional variation in each process and a misalignment between the contact hole 3 and the first wiring layer 1 and the second wiring layer 2. For this reason, the contact portion is often made wider than the width of the wiring layer other than the contact portion. This is particularly remarkable in a place where the wirings are dense because a narrow wiring width is used.

FIGS. 6 to 8 are views showing a method of forming the contact portion. FIG. 6 shows a state in which the first wiring layer 1 and the second wiring layer 2 are overlapped and extend in parallel for convenience of explanation. FIG. 8 is a cross-sectional view taken along line BB ′ of FIG.
It is a line sectional view. That is, as shown in FIG. 6, when the second wiring layer 2 is formed on the first wiring layer 1 with the interlayer insulating film 6 interposed therebetween, as shown in FIG. A photoresist 5 is applied thereon. Next, after irradiating exposure light 7 through a reticle pattern 4 for forming the second wiring layer 2 and then performing processing such as etching, a second layer is formed on the interlayer insulating film 6 as shown in FIG. Two wiring layers 2 are formed. Incidentally, the contact hole 3 is formed in a step before the second wiring layer 2.

[0005]

However, in the above-described conventional method of forming a contact portion, as shown in FIG. 7, the interlayer insulating film 6 formed on the first wiring layer 1 has a step on the base. , A hook-shaped or concave-shaped step occurs in a portion corresponding to a corner of the first wiring layer 1. This step portion occurs in a portion indicated by a symbol a in FIG. For this reason, a step having the same shape also occurs in the second wiring layer 2 formed above the interlayer insulating film 6, so that the reticle pattern 4
The exposure light 7 radiated through the second wiring layer 2 is reflected by the step portion a of the second wiring layer 2. When such reflection occurs, the reflected light concentrates in the vicinity of the corner of the first wiring layer 1, and the photoresist for forming the nearby wiring portion is exposed to the reflected light (indicated by reference numeral b in FIG. 7). Part) will be. In this case, the photoresist on the wiring portion after the photoresist development processing does not sufficiently remain. Therefore, if the wiring layer is etched using the photoresist as a pattern,
In a portion where the photoresist is not sufficiently left, there is a problem that the wiring is thinned or disconnected.

The present invention has been made in view of such a situation, and a semiconductor integrated circuit device capable of reliably forming a wiring layer at a contact portion and improving reliability and a method of manufacturing the same. It is an object to provide a method as well as a mask.

[0007]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit device in which a lower wiring layer and a contact portion continuous with the lower wiring layer are formed. A boundary portion between the lower wiring layer and the contact portion is covered with an upper wiring layer having a width of the contact portion, and the width is a length of the lower wiring layer in a width direction. And The lower wiring layer is a first wiring layer, and the upper wiring layer is a second wiring layer.
A step portion formed at the boundary between the first wiring layer of the contact portion and the first wiring layer other than the contact portion. . Further, the boundary portion may be a step portion formed at a boundary between the first wiring layer of the contact portion and the first wiring layer other than the contact portion. 5. The method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein: a first step of forming a lower wiring layer and a contact portion continuous with the lower wiring layer that is wider than the lower wiring layer; Forming a boundary portion with the contact portion so as to be covered with an upper wiring layer having the width of the contact portion . Further, in the first and second steps, a step of forming the lower wiring layer of polysilicon or silicide as a wiring material on the wafer by CVD or sputtering, and a step of applying a photoresist on the wafer. Thereafter, a step of transferring the wiring pattern drawn on the first mask by exposure with a stepper, a step of removing the photoresist portion exposed by the exposure, and forming the remaining photoresist as a pattern, and etching the photoresist. Forming a pattern of a lower wiring layer, forming an insulating interlayer film on the wafer to electrically separate the lower wiring layer and the upper wiring layer, and forming a photoresist on the wafer. After applying,
Transferring a contact hole pattern drawn on a second mask by exposure with a stepper, removing a photoresist portion exposed by the exposure, forming the remaining photoresist into a pattern, and etching the insulating layer by etching. Forming a contact hole in the interlayer film, forming an upper wiring layer of polysilicon or silicide as a wiring material on the insulating interlayer film by CVD or sputtering, and applying a photoresist on the upper wiring layer And then transferring the wiring pattern drawn on the third mask by exposure with a stepper;
Removing the photoresist portion exposed by the exposure, and forming the upper wiring layer so as to cover the boundary where the width of the lower wiring layer changes by etching with the remaining photoresist as a pattern; Can be included. 7. The mask according to claim 6, wherein a pattern of the upper wiring layer having the width of the contact portion is formed to cover a boundary portion where the width of the lower wiring layer changes in the contact portion, and the width of the contact portion is larger than that of the contact portion.
It is characterized by the length in the width direction of the lower wiring layer .

[0008]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings described below, the same parts as those in FIGS. 5 to 8 are denoted by the same reference numerals. FIG. 1 is a plan view showing a contact portion according to one embodiment of the semiconductor integrated circuit device of the present invention. As shown in the figure, the contact portion is provided with a contact hole 3 for electrically connecting a first wiring layer 1 as a lower wiring layer and a second wiring layer 2 as an upper wiring layer. I have. The second wiring layer in the contact portion is formed widely so as to cover the hook-shaped or concave-shaped step portion a of the first wiring layer 1.

Next, a method of forming the above-mentioned contact portion will be described with reference to FIGS. In addition, FIG.
For convenience of explanation, a state where the first wiring layer 1 and the second wiring layer 2 are overlapped and extend in parallel is shown. FIG.
FIG. 3 is a sectional view taken along line AA ′ of FIG. 2.

First, as shown in FIG. 3, a first wiring layer 1 is formed on a wafer. In forming the first wiring layer 1, a wiring layer of polysilicon or silicide, which is a material for wiring, is formed on a wafer by CVD or sputtering.
Next, after a photoresist is applied on the wafer, a wiring pattern drawn on a reticle (not shown) is transferred by exposure with a stepper. At this time, the exposure light is shielded at a portion having a reticle pattern, and the photoresist is exposed to the exposure light at a portion having no reticle pattern. Next, the photoresist portion exposed by the photoresist developing process is removed. When the remaining photoresist is used as a pattern and etched by plasma etching or the like, a pattern of the first wiring layer 1 is formed.

Here, the contact portion of the first wiring layer 1 needs a margin in manufacturing with respect to the size of the contact hole 3 formed in the next step. The manufacturing margin is a margin for misalignment of the reticle between the first wiring layer 1 and the contact hole 3, a margin for a variation in the size of the contact hole 3, and the like. For this reason, the wiring layer of the contact portion is wider than the width of the wiring layer other than the contact portion. And two concave step portions a are formed. Incidentally, FIG. 1 shows a state where hook-shaped or concave-shaped steps a are formed at four places.

Next, in order to electrically separate the first wiring layer 1 and the second wiring layer 2, an insulating interlayer film 6 such as a silicon oxide film is formed on the wafer. At this time, the insulating interlayer film 6
Is affected by the underlayer, a step is formed between a portion of the wafer surface where the first wiring layer 1 is formed and a portion where the first wiring layer 1 is not formed.

Next, a contact hole 3 is formed. In forming the contact hole 3, as in the case of forming the first wiring layer 1, after applying a photoresist on the wafer, a contact hole pattern drawn on a reticle (not shown) is transferred by exposure with a stepper. . Next, the photoresist portion exposed by the photoresist developing process is removed. Using the remaining photoresist as a pattern and etching the insulating interlayer film 6 by plasma etching or the like, a contact hole 3 is opened.

Next, a second wiring layer 2 is formed. When forming the second wiring layer 2, similarly to the case of forming the first wiring layer 1, a wiring layer of polysilicon or silicide as a wiring material is formed on the wafer by CVD or sputtering. After applying a photoresist on the wafer, the wiring pattern drawn on the reticle 4 is transferred by exposure with a stepper. Next, the photoresist portion exposed by the photoresist developing process is removed. When the remaining photoresist is used as a pattern and etched by plasma etching or the like, a second wiring layer 2 is formed as shown in FIG.

The wiring pattern of the second wiring layer 2 is as follows:
As in the case of the first wiring layer 1, a margin in manufacturing is provided for the contact hole 3, and the width of the wiring layer in the contact portion is widened. In FIG. 2, the first wiring layer 1 and the second wiring layer 2 have the same margin. Here, in the present embodiment, as shown in FIG. 2, the second wiring layer 2 is formed so as to cover the above-described hook-shaped or concave-shaped step portions a formed at two places of the first wiring layer 1. Has formed. Also, as shown in FIG.
In the case where hook-shaped or recessed step portions a are formed at four places in the first wiring layer 1, the second portions are formed so as to cover the respective step portions a.
Wiring layer 2 is formed. When forming such a second wiring layer 2, the wiring pattern drawn on the reticle 4 is formed to be wide so as to cover the step a of the first wiring layer 1.

As a result, as shown in FIG. 2, the exposure light 7 radiated through the reticle pattern 4 is not radiated to the step a of the first wiring layer 1. For this reason, the concentration of the reflected light in the vicinity of the corner of the first wiring layer 1 is avoided, and the photoresist for forming the nearby wiring portion is not exposed to the reflected light. Therefore, since the photoresist in the wiring portion after the photoresist development processing is sufficiently left, etching the wiring layer using the photoresist as a pattern forms the second wiring layer 2 having an appropriate width.

[0017]

As described above, according to the semiconductor integrated circuit device, the method of manufacturing the same, and the mask according to the present invention, the portion where the width of the lower wiring layer of the contact portion formed on the wafer changes is covered by the upper wiring layer. As a result, it is possible to reliably form the wiring layer in the contact portion,
Reliability can be improved.

[Brief description of the drawings]

FIG. 1 is a plan view showing a contact section according to an embodiment of a semiconductor integrated circuit device of the present invention.

FIG. 2 is a plan view showing a state where a first wiring layer and a second wiring layer of FIG. 1 are overlapped and extended in parallel.

FIG. 3 is a cross-sectional view for explaining a method of manufacturing the contact section of FIG.

FIG. 4 is a cross-sectional view taken along the line AA ′ showing the contact portion of FIG. 2;

FIG. 5 is a plan view showing a contact portion of a conventional semiconductor integrated circuit device.

FIG. 6 is a plan view showing a state in which the first wiring layer and the second wiring layer of FIG. 5 are overlapped and extended in parallel.

FIG. 7 is a cross-sectional view for explaining a method of manufacturing the contact section in FIG.

FIG. 8 is a sectional view taken along the line BB ′ showing the contact portion in FIG. 6;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st wiring layer 2 2nd wiring layer 3 contact hole 4 reticle 5 photoresist 6 interlayer insulating film 7 exposure light a step part

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) H01L 21/3205 H01L 21/321 H01L 21/3213 H01L 21/768

Claims (6)

(57) [Claims] 1. A semiconductor integrated circuit device in which a lower wiring layer and a contact portion continuous with the lower wiring layer are formed, wherein a boundary portion between the lower wiring layer and the contact portion is formed. A semiconductor integrated circuit device covered with an upper wiring layer having a width of the contact portion, wherein the width is a length in a width direction of the lower wiring layer. 2. The method according to claim 1, wherein the lower wiring layer is a first wiring layer.
The upper wiring layer is a second wiring layer, and the portion where the width of the lower wiring layer changes is the boundary between the first wiring layer of the contact portion and the first wiring layer other than the contact portion. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is a step formed at the portion. 3. The method according to claim 2, wherein the boundary portion is a step portion formed at a boundary between the first wiring layer of the contact portion and the first wiring layer other than the contact portion. 13. The semiconductor integrated circuit device according to claim 1. 4. A lower wiring layer, a first step of forming a said lower wiring wider contact portion than layer continuous with this, and the lower wiring layer boundary portion between the contact portion, before
A second step of forming the semiconductor integrated circuit device so as to cover it with an upper wiring layer having a width of the contact portion . 5. The first and second steps include: forming the lower wiring layer of polysilicon or silicide as a wiring material on the wafer by CVD or sputtering; and forming a photoresist on the wafer. After applying, the step of transferring the wiring pattern drawn on the first mask by exposure with a stepper, the step of removing the photoresist portion exposed by the exposure, the remaining photoresist as a pattern, Forming a pattern of the lower wiring layer by etching; forming an insulating interlayer film on the wafer to electrically separate the lower wiring layer and the upper wiring layer; After applying the photoresist, the contact hole pattern drawn on the second mask is exposed by a stepper. Transferring the resist, removing the photoresist exposed by the exposure, forming a contact hole in the insulating interlayer by etching the remaining photoresist as a pattern, and forming a contact hole on the insulating interlayer by etching. Forming an upper wiring layer of polysilicon or silicide as a wiring material by CVD or sputtering, and applying a photoresist on the upper wiring layer,
Transferring the wiring pattern drawn on the mask by exposure with a stepper, removing the photoresist portion exposed by the exposure, forming the remaining photoresist into a pattern, and etching the lower wiring layer by etching. 5. The method of manufacturing a semiconductor integrated circuit device according to claim 4, further comprising the step of forming the upper wiring layer so as to cover a boundary portion where the width changes. 6. A pattern of an upper wiring layer having a width of the contact portion covering a boundary portion where a width of the lower wiring layer changes in the contact portion, wherein a pattern of the upper wiring layer is formed .
The mask is characterized in that the width is a length in a width direction of the lower wiring layer .