JPH0528794A - Semiconductor memory device - Google Patents

Abstract

PURPOSE: To prevent redundant cell array area from increasing by controlling access to a normal column according to a select signal selecting the column corresponding to a redunancy sense signal. CONSTITUTION: A normal column decoder NCD and a redundant column decoder RCD are provided and a defective normal memory cell is substituted for by a spare cell. At this time, a block selecting circuit BLS generates a block select signal for selecting a specific block corresponding to a row address RA. A redundancy sense circuit generates the redundancy sense signal actuating the substitution for the spare cell according to a column address matching a fuse circuit and the said block select signal. Then a redundancy selecting circuit RS selects a column to be replaced corresponding to the sense signal. Then a normal decoder control circuit NCD controls access to the normal column decoder NCD according to the redundancy signal, so redundant cell arrays RCA are prevented from increasing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a redundant structure such as dynamic RAM.

[0002]

2. Description of the Related Art In a semiconductor memory device, when a defect occurs in a normal memory cell, a row address corresponding to the defect occurrence position is decoded, and a spare cell complements the defect of the normal cell. Have. A spare cell array (or redundant cell array) in which spare cells (or redundant cells) are arranged is
A decoder, which is arranged around the normal cell array and is necessary for address decoding and redundant cell selection, is separately installed. A generally known decoding method for redundancy is that when a defect occurs in a normal cell of one block in a normal cell array divided into a large number of blocks, the entire block including this normal cell is deleted. This is a method of replacing with a corresponding redundant cell block.

A generally known redundancy scheme will be observed and viewed with reference to the conventional configuration shown in FIG. Figure 1
The memory cell array is composed of an m × n normal cell array and an m × k redundant cell array. As shown in FIG. 1, in the conventional structure for redundancy, sensing signals (φREN1 and φRE) for sensing whether an externally input address is a defective normal cell address or not.
N2, ..., φRENk) pass through a normal decoder control circuit (NDC) to a normal column decoder (NDC).
CD1, NCD2, ... NCDn), and each of the normal column decoders is connected to an input / output gate (I) connected to a normal cell array (NCA) in the column direction.
O) are commonly controlled. That is, the NCD1 includes input / output gates (IO11, IO21, ...) Connected to the normal cell arrays (NCA11, NCA21, ... NCAm1).
IOm1) is temporarily controlled through a common column selection line (not shown), and NCDn is a normal cell array (NCA1n, NCA2n, ..., NCAmn).
I / O gates (IO1n, IO2n,
... IOmn) is controlled at one time.

The fuse box (FB1, FB2,
, FBk), each redundant sensing signal (φR
EN1, φREN2, ..., φRENk) are redundant column decoders (RCD1, RCD2, ..., RCDk).
Is also entered. The redundant column decoder (RCD1,
RCD2, ..., RCDk) and redundant cell array (RCA1)
, ... RCAmk) is the same as the connection relationship in the normal cell array described above.

In the conventional structure as described above, there is one
When there is a defect in an address position corresponding to one normal cell, for example, a normal cell in (NCA11), an input / output gate connected to a normal cell array (NCA11, NCA21, ..., NCDm1) by a normal column decoder (NCD1). (IO11, IO21, ..., IO
m1) are all disabled, and the input / output gate (RIO1) connected to the redundant column decoder (RCD1)
, RIO21, ..., RIOm1) are all enabled to replace the cell. Here, it should be noted that the input / output lines are commonly used in both the normal cell array and the redundant cell array.

The process of generating the redundant sensing signal (φRENk) can be understood with reference to FIG. The fuse box (FBk) shown in detail in FIG. 2 controls three fuse decoders (10a, 10b and 10c) and transfer gates (13-18) in the fuse decoders (10a, 10b, 10c). It is composed of a gate control circuit (10). By disconnecting the main fuse (11) in the gate control circuit (10), transfer gates (13-18)
Transmits the address (A1 to A9) input from the outside to one end of the sub fuse (19 to 24). The 6 sub-fuse (19-24) form 3 pairs. By cutting one sub-fuse in each pair, a combination of defective addresses is determined, and a combination of externally input addresses (A1 to A9) is set to the sub-fuse (19 to 24). NAND gate (28) only if it matches the specified combination.
Output becomes "low". In the other fuse decoders (10b, 10c), the "low" state signal is output only in the case where the combinations match by the same process. If all of these conditions are met, the NOR that finally generates the redundant sensing signal (φRENk)
The output of the gate (29) is in the "high" state.

When the redundant sensing signal (φRENk) becomes "high", the redundant column decoder (RCD) shown in FIG.
The redundant column selection signal (RCSLk) which is the output of k) becomes "high", and the output (DAij) of the normal decoder control circuit (NDC) shown in FIG. 4 is "low".
It becomes a state. The output (DAij) of this normal decoder control circuit (NDC) disables the normal column decoders (NCD1, ..., NCDn). Therefore, the normal column decoder (NCD
n) controlled by normal input / output gates (IO11,
, IOm1) connected to normal bit lines (normal cell array (NCA11, ..., NCAm1))
Corresponds to the redundant input / output gates (RIO11, ..., RIO) controlled by the redundant column decoder (RCDk).
m1) are replaced by redundant bit lines (redundant cell arrays RCA11, ..., RCAm1).

That is, if a group of normal cell arrays connected to one normal column decoder is a normal array block and a group of redundant cell arrays connected to one redundant column decoder is a redundant array block, one normal array block is used. The array block and one redundant array block are replaced 1: 1.

[0009]

However, in the above-mentioned conventional method, the larger the number of defective normal array blocks, the more the redundant array blocks are consumed. Therefore, it is inevitable to increase the array area. On the other hand, even a normal memory cell having no defect in the normal cell array block is replaced with a redundant cell, which causes a problem of redundancy inefficiency.

Therefore, it is an object of the present invention to provide a semiconductor memory device in which the array area is prevented from increasing by increasing the redundancy efficiency.

[0011]

In order to achieve the above object of the present invention, a semiconductor memory device of the present invention has a normal column decoder and a redundant column decoder, and replaces a defective normal memory cell with a spare cell. A semiconductor memory device capable of performing a block selection circuit for generating a block selection signal for selecting a specific block corresponding to a row address, and a fuse circuit, and a column address matching the fuse circuit and the column address A redundant sensing circuit for generating a redundant sensing signal for activating replacement in a spare cell based on the block selection signal, and a redundant selection circuit for generating a redundant selection signal for selecting a column for replacement corresponding to the redundant sensing signal. And controlling access to the normal column of the normal column decoder based on the redundancy selection signal. Comprising a chromatography circle decoder control circuit.

Also, in a semiconductor memory device having a plurality of columns of normal memory cells and a plurality of columns of spare memory cells, a plurality of normal column decoders corresponding to the number of columns of the normal memory cells and the spare memory cells are provided. It includes a plurality of redundant column decoders corresponding to the number of columns, a plurality of block selection circuits for generating a plurality of block selection signals for selecting a block of a memory cell by inputting a row address, and a fuse circuit. A predetermined number of redundant sensing circuits for generating a redundant sensing signal for activating replacement in a spare cell based on the column address and each block selecting signal from the block sensing circuit, and each redundant sensing signal from the redundant sensing circuit. And a redundancy select signal for selecting a column to be replaced based on The redundant column decoder includes a plurality of redundant selection circuits corresponding to the number of columns of the memory cells and a normal decoder control circuit for controlling access to the normal column of the normal column decoder based on the plurality of redundant selection signals. Each of the redundant selection signals is input to.

Also, a semiconductor memory device having a plurality of normal column decoders and redundant column decoders, which substitutes a defective normal memory cell with a spare memory cell by utilizing fuses, and corresponds to a row address. A plurality of block selection circuits for generating a plurality of block selection signals for selecting a specific block, a predetermined number of sub fuses connected to a predetermined number of column addresses, one main fuse, and detection of disconnection of the main fuses. A plurality of fuse circuits each having a logic gate for receiving a signal and the block selection signal, and for outputting a plurality of redundant sensing signals for activating replacement to a spare memory cell.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the accompanying drawings. FIG. 5 is a block diagram showing the configuration of the semiconductor memory device of this embodiment. The structure of the memory cell array (normal cell array and redundant cell array) is the same as that in the case of FIG. However, the redundant sensing signal, which is the output signal from the fuse box, is not directly connected to the input of the normal decoder control circuit (NDC) that controls the normal column decoders (NCD1, ..., NCDn) as in the case of FIG. Then, the redundancy selection circuit (RS
, ..., RSk) through the redundant selection signal (φRS1,
, ΦRSk) are connected.

Each redundant selection circuit (RS1, ..., RS
k) is the k number of fuse boxes (FB1, FB2, ...,
FBi) each main fuse box (MF
B1, ..., MFBk). That is, the redundancy selection circuit (RS1) is supplied to the redundancy sensing signal (φRE) output from the main fuse box (MFB1).
N11, ..., φREN1i) is input, and when one of the redundant sensing signals indicates a redundant sensing state, the corresponding redundant column decoder is enabled. Main fuse boxes (MFB1, MFB2, ..., MFBk)
A fuse selection box (FB) inside is supplied with a block selection signal (φBLS) which is an output of the block selection circuit (BLS) and which is determined by a row address.

As can be understood from FIG. 5, the block selection signal (φBLS) generated by the row address is applied to the fuse box (FB), and the redundancy selection signal (φRS) is created from the fuse box (FB). The above configuration is different from the conventional configuration of FIG. In FIG. 5, the normal array and the redundant array are shown in FIG.
, M × n and m × k arrays, and m row decoders (RD1, ..., RDm), n normal column decoders (NCD1, ..., NCDn), and k redundant column decoders ( , RCDk), one normal decoder control signal (φNDC), k redundant selection signals (φRS1, ..., φRSk), k main fuse boxes (MFB1, ..., MFBk), k
X i number of fuse boxes (FB11, ..., FBki)
And redundant sensing signals (φREN11, ..., φRENk
i), and one block selection signal (φBLS11, ..., φBLSki) is used for each fuse box.

The row address (RA) applied to the block selection circuit (BLS) is a part of the row address applied to the row decoder (RD), which is derived from the address buffer (or row address buffer). This is the output signal. Therefore, the fuse box (FB1
1, ..., FBki) is a block [cell array (eg NCA11, NCA11, NCA) corresponding to one row decoder (eg RD1)] selected by a combination of row addresses.
CA12, ..., NCA1n, RCA11, RCA12,
, RCA1k)]] is input.

FIG. 6 shows the fuse box (F) of FIG.
It is a figure which shows the internal structural example of B). As shown in the figure, the fuse box used in this embodiment has the block selection signal (φBLS) through the NAND gate (52).
ki) is applied. So Main House (51)
If the block selection signal (φBLSki) is disabled (“low” state) even if the block is cut off to enter the redundant mode (that is, the block is not substantially the corresponding block), the NOR gate (54) is used. The redundant sense signal (φREN) of the output fuse fuse box (FBki)
ki) does not operate the redundancy selection circuit (RS) (“low” state). 6, the internal structure of the blocks (10a, 10b, 10c) to which the addresses (A1 to A9) are applied is the same as that of FIG. 2 and therefore not shown. The addresses (A1 to A9) are address signals capable of selecting the bit line of the defective normal memory cell.

FIGS. 7 and 8 illustrate an embodiment capable of generating a block select signal (φBLSki) applied as one input of the NAND gate (52) of FIG. 6 above. In the case of FIG. 7, the NAND gate (5
5) and the NOR gate (57) are used to combine row addresses (RA7 to RA10).
Is a form utilizing fuses (F1 to F6). Figure 8
, ΦFP is a precharge signal, and φPE is an enable signal.

FIG. 9 is a diagram showing an example of a normal decoder control circuit (NDC) used in this embodiment. FIG. 10 shows a redundancy selection circuit (RS
FIG. 3 is a diagram showing an example of the internal configuration of k) and a redundant column decoder (RCDk). The redundancy selection signal (φRS) which is the output of the redundancy selection circuit (RSk) composed of the NOR gate (65)
k) is simultaneously supplied to the redundant column decoder (RCDk) and the normal decoder control circuit (NDC) of FIG.

A redundant operation in the semiconductor memory device of this embodiment will be described based on the above configuration. First, as can be understood from FIG. 6, when the main fuse (51) is cut off and the potential of the node (53) becomes the “low” state, it is notified that the redundancy mode has been entered. However, the block selection signal (φB which is one input of the NAND gate (52)
When LSki) is disabled (“low” state), the output of the NAND gate (52) is maintained in “high” state, so that the redundant sensing signal (φRENki) which is the output of fuse box (FBki) is Do not work.

To understand this in more detail, refer to the fuse decoder (10a) of FIG. NAN in Figure 6
While the output of the D gate (52) is in the "high" state, all the transfer gates (13 to 18) are turned off, and the N-type MMOS transistors (25 to 27) connected to the ground voltage terminal (V _SS ) are When turned on, the inputs of NAND gate (28) are all "low". NAND
When the output of the gate (52) is in the "low" state, all the transfer gates (13-18) are turned on and the address signals (A1, A2, A3) are input to the NAND gate (28). The N-type MOS transistors (25 to 27) connected to the end (V _SS ) are turned off. Therefore, the address signals (A1, A
2, A3) matches the disconnection of the sub fuses (19 to 23), all the inputs of the NAND gate (28) are "high".
Becomes

When the main fuse (51) is cut off, one of the pairs of fuses (19, 20), (20, 21), (22, 23) to which the addresses (A1 to A9) are connected is cut off. You need to be careful. Therefore, if the combination of the input addresses (A1 to A9) is the same as the address of the defective cell, the NAND gate (2
The input signals of 8) are all in the "high" state, and the output signals thereof are in the "low" state, and the NOR gate (5
The redundant sensing signal (φRENki) which is the output of 4) is set to the “high” state.

The redundant sensing signal (φRE in the "high" state)
Nki) inputs the redundancy selection signal (φRSk) in the “low” state to the normal decoder control circuit (KDCk) of FIG. 9 through the redundancy sensing circuit (RSK) [see FIG. 10]. Therefore, the normal decoder control signal (φNDCij) is in the "low" state to disable the normal decoder, and the redundant column selection signal (RCSLk) is in the "high" state to drive the corresponding redundant array block.

Here, the redundant sensing signal (φRENk
It is important that i) is a signal including the block selection signal (φBLSk) by the row address as well as the column (or bit line) related to the defective normal memory cell.

[0026]

According to the present invention, it is possible to provide a semiconductor memory device which prevents an increase in array area by increasing the efficiency of redundancy. That is, by applying the block selection signal by the row address to the column redundancy fuse box, there is an effect that an efficient redundancy operation is performed. Further, since the normal columns and the redundant columns can be made to correspond to each other in a block-to-block manner, there is an advantage that an unnecessary area increase of the redundant cell array is reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a conventional semiconductor memory device.

FIG. 2 is a diagram showing an example of an internal configuration of a fuse box shown in FIG.

FIG. 3 is a diagram showing an internal configuration example of a redundant column decoder of FIG.

4 is a diagram showing an internal configuration example of a main decoder control circuit of FIG.

FIG. 5 is a block diagram showing a configuration of a semiconductor memory device of this embodiment.

6 is a diagram showing an example of an internal configuration of the fuse box shown in FIG.

FIG. 7 is a diagram showing an example of a circuit for generating the block selection signal of FIG.

FIG. 8 is a diagram showing another example of a circuit for generating the block selection signal of FIG.

9 is a diagram showing an internal configuration example of a main decoder control circuit of FIG.

10 is a diagram showing an internal configuration example of a redundant selector and a redundant column decoder of FIG.

[Explanation of symbols]

BLS ... Block selection circuit, MFB ... Main fuse box, FB ... Fuse box, RS ... Redundancy selection circuit, NDC ... Normal decoder control circuit, NC
D ... Normal column decoder, RCD ... Redundant column decoder, NCA ... Normal cell array, RCA ... Redundant cell array, RD ... Row decoder, IO ... Input / output gate

Claims (11)

[Claims] 1. A semiconductor memory device having a normal column decoder and a redundant column decoder, in which a defective normal memory cell can be replaced by a spare cell, and a specific block is selected according to a row address. A redundant sensing circuit that includes a block selection circuit that generates a block selection signal and a fuse circuit that generates a redundant sensing signal that activates replacement in a spare cell based on the column address that matches the fuse circuit and the block selection signal. A circuit, a redundancy selection circuit for generating a redundancy selection signal for selecting a column to be replaced in response to the redundancy sensing signal, and a normal circuit for controlling access to a normal column of the normal column decoder based on the redundancy selection signal. A semiconductor memory device including a decoder control circuit . 2. The normal column decoder controls access to a specific block of a normal column based on the output of the normal decoder control circuit, and the redundant column decoder specifies a redundant column based on the redundant selection signal. 2. The semiconductor memory device according to claim 1, wherein access to the block is controlled. 3. The semiconductor memory device according to claim 1, wherein the block selection circuit comprises a logic gate or a fuse. 4. The fuse circuit has a main fuse and a sub fuse, and comprises a logic gate for receiving at least a signal for detecting disconnection of the main fuse and the block selection signal. A semiconductor memory device as described. 5. A semiconductor memory device having a plurality of columns of normal memory cells and a plurality of columns of spare memory cells, the plurality of normal column decoders corresponding to the number of columns of the normal memory cells, and the spare memory cells. Includes a plurality of redundant column decoders corresponding to the number of columns, a plurality of block selection circuits that generate a plurality of block selection signals that input a row address and select a block of a memory cell, and a fuse circuit. A predetermined number of redundant sensing circuits for generating a redundant sensing signal for activating replacement in a spare cell based on the column address and each block selecting signal from the block sensing circuit; and each redundant sensing signal from the redundant sensing circuit. And a redundancy select signal for selecting a column to be replaced based on The redundant column decoder includes a plurality of redundant selection circuits corresponding to the number of columns of the memory cells, and a normal decoder control circuit for controlling access to the normal column of the normal column decoder based on the plurality of redundant selection signals. A semiconductor memory device, wherein each of the redundancy selection signals is input to the. 6. The semiconductor memory device according to claim 5, wherein the block selection circuit comprises a logic gate or a fuse for inputting the row address. 7. Each of the fuse circuits has a main fuse and a sub fuse, and is provided with a logic gate for receiving at least a signal for detecting disconnection of the main fuse and the block selection signal. Item 6. The semiconductor memory device according to item 5. 8. The semiconductor memory device according to claim 7, wherein the sub fuse is connected to each of the column addresses. 9. A semiconductor memory device having a plurality of normal column decoders and redundant column decoders, wherein a defective normal memory cell is replaced by a spare memory cell by using fuses, and the semiconductor memory device corresponds to a row address. A plurality of block selection circuits for generating a plurality of block selection signals for selecting a specific block, a predetermined number of subfuses connected to a predetermined number of column addresses, one main fuse, and detection of disconnection of the main fuse A plurality of fuse circuits each having a logic gate for receiving a signal and the block selection signal, and for outputting a plurality of redundant sensing signals for activating replacement to a spare memory cell. apparatus. 10. A plurality of redundancy selection circuits which respectively input the plurality of redundancy sensing signals and output one redundancy selection signal for selecting a column to perform substitution, and a plurality of redundancy selection signals which are input, 10. The semiconductor memory device of claim 9, further comprising a normal decoder control circuit that controls access to the normal column of the normal column decoder. 11. The block selection circuit according to claim 9, wherein each of the block selection circuits comprises a logic gate or a fuse.
A semiconductor memory device as described.