KR100375599B1 - Row redundancy circuit - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a row redundancy circuit that increases the efficiency of a redundant cell and increases the number of repairable cells. The present invention relates to a switch transistor of a cell by using a redundant row address fixed at a constant level in a device having an NK refresh cycle. By switching the gate lines of the gate lines from single to double structures, the double word lines can be arranged to the left and right of the entire cell array and enable control with redundant row addresses. If this happens, one of the two word lines in one row can be given up and the other word line can continue to be used, and the redundancy word line can also use one of the two repair word lines in one row to repair the defects of the whole row and the other. One to use for another loo defect .

Description

Row redundancy circuit

The present invention relates to a row redundancy circuit, and more particularly, to a row redundancy circuit employing a double word line structure as a row redundancy structure.

In the conventional DRAM, in the case of a defect in a cell during a process, the fuses are programmed to an address corresponding to each cell, and when a real defect occurs, the information (address) of the cell is blown to the fuse to the redundant cell. The alternative method is adopted.

The conventional repair algorithm using a redundant cell and a programmed fuse cannot actually perform a repair by matching one redundant cell to one cell. If this is to be possible, there must be a fuse with a combination of all addresses (i.e. column and row address) programmed and a redundant cell that has a one-to-one correspondence to every cell. It becomes a redundancy structure.

As a result, most of the conventional memory devices are performed strictly at the row or column level using the redundancy word line and the redundancy column (or bit line) selection instead of the redundancy cell.

Thus, if more loot defects occur in a single cell array than pre-prepared redundancy word lines, or more loot defects occur in the entire block than pre-prepared fuse boxes, the device can no longer be repaired. Likewise, if more column defects occur than the prepared redundancy line, the device is also impossible to repair. This is a limiting factor in increasing yield in the mass production stage.

As shown in FIG. 1, the conventional row redundancy structure has one loo defect and one repair word line rw1 regardless of the scale of the defect, regardless of whether the defect is one cell or all the cells connected to the word line. This one-to-one correspondence.

The repair word line rw1 includes a fuse box unit 18 that stores an address of a defective cell in the cell block 24, and a plurality of repair lines for determining whether an input address signal is a normal cell or a defective cell. A block / redundancy word line, which is a comparator 20 that is a decoder and a replacement device for disabling a word line connected to a defective cell and a repair word line rw1 connected to a spare cell when a redundancy address is input. It is finally selected by the selection unit 22 or the like.

In FIG. 1, the first buffer 10 receives and buffers an address add_2NK bisecting the cell block 24 and a low active refresh mode designation signal NK-refreshb that designates the NK refresh mode. The buffer 12 receives and buffers a block selection address (add_block) for selecting a desired block from the divided cell block, and the third buffer 14 generates a defect in the cell array in the block selected from the divided cell block. A word line selection address (add_wordline) for selecting a word line to which a cell is connected is received and buffered.

When the refresh mode designation signal NK_refreshb is " low ", all the output signals addx_2NK and addxb_2NK of the first buffer 10 are fixed to " high ". It is input to the block controller 16 together with the output signal of the two buffers 12.

In the block controller 16, since the cell block dividing address add_2NK is fixed at a predetermined level, the block / redundancy word line selector 22 and the fuse box unit 18 are selected to select two of 2N cell blocks. To control. The output signal of the third buffer 14 is provided to the fuse box unit 18, and the output value of the comparator 20 is determined according to the fuse disconnection signal from the fuse box unit 18.

FIG. 2 is a diagram illustrating an address (add_2NK) for dividing an entire cell array into one half of a conventional 2NK cell block. The conventional 2NK cell block is composed of two 1NK cell blocks, and each cell array 0 to N is represented by FIG. It has K word lines. The most significant bit is an address that bisects the entire cell array in the 2NK cell block at an address (0..00 to 11 ... 11) designating each cell array. add_2NK). On the other hand, the remaining addresses except for the most significant bit become a block select address (add_block). Accordingly, when NK refresh is performed, the cell block divided into the upper NK cell block and the lower NK cell block due to the address fixed at the high level (add_2NK) and the upper one of the cell arrays by the same block selection address (add_block). The corresponding lower cell array is selected at the same time.

Such a conventional redundancy algorithm has a very poor limit as illustrated in FIGS. 3 and 4 because one loo defect and one repair word line rw1 correspond one to one.

That is, when more defects occur than the number of repair word lines rw1 existing in the cell array having the same block address as in FIG. 3, more repairs are possible.

In addition, as shown in FIG. 4, even when more erosion defects occur than the number of fuse boxes (Fuse Box 0 to Fuse Box 7) in the fuse box unit 10, which is an address memory device existing in all cell blocks, is repaired. Is impossible. In other words, repair is not possible when more than the number of fuses occurs in the row repair unit block in which fuse boxes 0 through fuse box 7 are bundled into one unit.

Accordingly, the present invention has been made in view of the above-described conventional circumstances, and an object of the present invention is to provide a low-redundancy circuit that can increase the efficiency of a redundant cell and increase the number of repairable cells.

In order to achieve the above object, a low redundancy circuit according to a preferred embodiment of the present invention includes a cell block having a plurality of cell arrays, and each of the cell arrays includes a plurality of repair word lines. In a semiconductor memory device capable of a repair operation on a generated word line,

Each repair word line in the cell array is divided into double repair word lines that are symmetrical to each other.

Determining means for determining a cell array to which the defective cell belongs;

Selection means for selecting a repair wordline for the defective cell;

Setting means for setting any one of the divided repair word lines,

Drive means connected to each repair word line divided into the left and right symmetric double repair word lines,

As the defective cell is generated, one line of the corresponding repair word line divided in the corresponding cell array is enabled.

1 is an example of a conventional low redundancy structure,

2 is a diagram illustrating an address for dividing an entire cell array into half of a conventional 2NK cell block;

3 is a block diagram illustrating the limitations of a low redundancy scheme according to a conventional embodiment;

4 is a block diagram illustrating the limitations of a low redundancy structure according to another embodiment of the prior art;

5 is a block diagram of a row redundancy circuit according to an embodiment of the present invention;

6 is an internal circuit diagram of the first buffer shown in FIG. 5;

7 is a configuration diagram illustrating an example of improving a repair rate according to an embodiment of the present invention;

8 is a configuration diagram of another example illustrating the improvement of the repair rate according to the embodiment of the present invention.

<Description of Symbols for Major Parts of Drawings>

10, 34: first buffer 12, 36: second buffer

14, 38: third buffer 16, 40: block control unit

18, 42: fuse box 20, 44: comparison unit

22, 32: block / redundancy word line selector

24, 30: cell block

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

5 is a block diagram of a low redundancy circuit according to an embodiment of the present invention, in which the device to which the embodiment of the present invention is applied is a device in which 2NK refresh mode and 1NK refresh mode are implemented, and which refresh mode is selected. The embodiment applies when a device supported up to 2NK refresh is selected as the NK refresh cycle.

Reference numeral 30 denotes a cell block provided with a plurality of cell arrays, and each repair word line existing in each cell array in the cell block 30 is divided into two to form a double word line structure. That is, there are two repair word lines rw1i, _1 and rw1i_r on the left and the right in one row. In the embodiment of the present invention, two repair word lines (rw1i, _1 and rw1i_r) on the left and the right are collectively referred to as a row repair word line.

Driving elements brs0 to brs15 are connected to each row repair word line in the cell block 30 in a one-to-one manner, and each of the driving elements brs0 to brs15 is driven by a control signal input from an external cell. Enables one of the two left and right repair word lines rw1i, _1 and rw1i_r for defective cells in the array.

The driving elements brs0 to brs15 are collectively referred to as a block / redundancy word line selector 32. As shown in FIG. 1, four driving elements are commonly connected to one decoder, and are controlled by a control signal from the corresponding decoder. It works alternatively.

Reference numeral 34 designates an address (add_2NK) for dividing the cell block of 2NK into two NK cell blocks and whether the refresh cycle of the device is set to 2NK or NK. ) Is a signal for fixing a constant level (e.g., a high level) to a value of NK-refreshb, and a Nk refresh cycle device uses a double word line for normal access and a single word line for refresh. The first buffer is configured to receive and buffer the refresh request signal Refresh_requestb.

Reference numeral 36 is a second buffer that receives and buffers a block selection address (add_block) irrelevant to the refresh cycle and provides the block control unit 40 to the block control unit 40. 38 is a fuse box unit which receives and buffers a word line selection address (add_wordline). A third buffer provided at 42.

When the semiconductor memory device to which the embodiment of the present invention is applied has a 1NK refresh cycle instead of 2NK, addx-2NK and addxb_2NK are high level values among the output signals addx_2NK, addxb_2NK, addx_NK, and addxb_NK of the first buffer 34. The fixed address is added to the block controller 40 and an address (addx_NK <addxb_NK) for a row repair using a double word line structure is newly generated and sent to the block / redundancy word line selector 32. Only one word line of a row repair word line having a double structure is selected by the value of the address (addx_NK, addxb_NK).

The block controller 40 determines a corresponding cell array in the cell block 30 according to the block selection address add_block buffered in the second buffer 36.

The fuse box section 42 stores an address of a defective cell and is composed of a plurality of fuse boxes fb0 to fb7. The fuse boxes fb0 and fb1 are connected to the decoder 0 of the comparator 44, the fuse boxes fb2 and fb3 are connected to the decoder 1, the fuse boxes fb4 and fb5 are connected to the decoder 2, and the fuse Boxes fb6 and fb7 are connected to decoder 3. Thus, for example, in the case of decoder 0, among the driving elements brs0, brs4, brs8, brs12 in the block / redundancy word line selector 32 by decoding a signal according to whether fuses are blown in the fuse boxes fb0 and fb1. Drive either one. The other decoder performs the same operation as above.

6 is an example of an internal circuit of the first buffer 934 illustrated in FIG. 5, wherein the first buffer 34 compares a cell block dividing address (add_2NK) signal with a reference voltage. And a NAND gate that receives the output terminal N1 signal of the differential amplifier 60 and the refresh mode designation signal NK-refershb, and outputs a signal add_2NK to be fixed to a predetermined level by NAND processing. ND1 and the other output terminal N2 signal of the differential amplifier 60 and the refresh mode designation signal NK_refreshb are input and NAND processed to receive another signal addxb_2NK to be fixed at the same level as the signal add_2NK. The NAND gate NK2 to be output, the output terminal N1 signal of the differential amplifier 60, the refresh mode designation signal NK_refreshb, and the refresh request signal Refrsh_requestb are inputted and logically combined to obtain a double word according to the present invention. Loo in the Russian rescue A logic unit circuit unit 62 outputting a signal for repair (addx_2NK), and an output terminal N2 coral of the differential amplifier 60, the refresh mode designation signal NK_refreshb, and a refresh request signal Refresh_requestb. In combination with a logic circuit section 64 for outputting a signal addxb_2NK for low repair in the double word line structure sought in the present invention.

The differential amplifier 60 is connected to the PMOS transistors P2 and P3 and NMOS transistor N2 and the PMOS transistor P2 which are cross-coupled with each other in parallel, and turned on / off by a buffering start signal. A PMOS transistor P1 and a PMOS transistor P4 connected in parallel to the PMOS transistor P3 and turned on / off by a buffering start signal and a gate thereof, and a gate of the NMOS transistor N2. An NMOS transistor N1 connected to the output terminal N1 and having a drain connected thereto, a NMOS transistor N4 having its gate connected to the gate of the NMOS transistor N3 and a drain connected to the output terminal N2; An NMOS transistor N5 having its drain connected in common to the sources of the NMOS transistors N2 and N3, the source being grounded, and receiving a buffering start signal delayed by a plurality of inverters as a gate; Prize A drain is connected to a source of the NMOS transistor N1 and a drain is connected to an NMOS transistor N8 operating on / off to the buffering start signal buffering_startb, and a drain is connected to a source of the NMOS transistor N4, and the buffering start signal. an NMOS transistor N18 that is turned on / off at buffering_startb, an NMOS transistor N9 whose drain is connected to a source of the NMOS transistor N8 and is controlled by a cas signal cas, and the NMOS transistor ( NMOS transistor N10 and NMOS transistor N18, which are connected between the source of N9 and ground Vssi and are controlled by the cell block dividing address add_2NK signal, are connected in parallel to each other. NMOS transistors N12 and N14, which operate opposite to a predetermined level of cas signal cas, are connected between the NMOS transistors N12 and ground Vssi and are connected to an existing voltage reference_voltage; NMOS transistor N13 that receives Vinti / 2 as a gate, and NMOS transistor N15 that is connected between the NMOS transistor N14 and ground Vssi and receives a reference voltage (Vinti / 2) as a gate. ).

The logic circuits 62 and 64 respectively include an inverter I1 and I2 for inverting the refresh mode designation signal NK_refreshb, an output signal of the inverter I1 and I2 and an output terminal N1 of the differential amplifier 60; N2) and a three-input gate (ND3) (ND4) for receiving a NAND signal and a refresh request signal (Refresh_requestb).

Referring to the operation of the first buffer 34 configured as described above, the refresh mode designation signal (NK_refreshb) is "low" and the refresh request signal (refersh_requestb) is "high" (that is, a double word line structure in the NK refresh mode) When the signal of the cell block dividing address add_2NK is larger than the reference voltage (reference_voltag) in the ecology for performing the access operation of the output terminal, the output terminal N1 of the differential amplifier 60 is low level and the other output terminal N1 is It becomes high level, and the logic circuit part 62 outputs the high level signal add_2NK, and the logic circuit part 64 outputs the low level signal addxb_2NK.

On the other hand, in the state where the refresh mode designation signal NK_refreshb is " low " and the refresh request signal refersh_requestb is " high " (that is, a state in which the access operation of the double word line structure is performed in the NK refresh mode) When the signal of the address add_2NK is smaller than the reference_voltage, the output terminal N1 of the differential amplifier 60 is at a high level and the output terminal N1 is at a low level, and the logic circuit 62 has a low level. The signal add_2NK is output, and the logic circuit unit 64 outputs the high level signal addxb_2NK.

As described above, when the output signal addx_2NK of the first buffer 34 is at the "high" level in the NK refresh mode, the left repair is performed in the structure of double repair word lines rw1i_1 and rw1i_r for one row. When the word line rw1i_1 is selected and the output signal addxb_2NK of the first buffer 34 is at the “high” level under the NK refresh mode, the repair word line rw1i_r on the right side is selected on the contrary.

Referring to the operation of the low redundancy circuit according to an embodiment of the present invention configured as described above are as follows.

In the case of a device having an NK refresh cycle, an address (addx_2NK, addxb_2NK) made in the first buffer 34 is decoded and applied to the driving devices brs0 to brs15 constituting the block / redundancy word line selector 32. In the block control unit 40, the first buffer 34 receives only one access by the address (addx_2NK, addxb_2NK) fixed to a high level value and the block selection address add_block through the second buffer 36. A signal for simultaneously selecting two cell arrays is applied to the driving elements brs0 to brs15 and the fuse box unit 42.

In addition, the third buffer 38 buffers the input word line selection signal add_wordline to the fuse box unit 42. In this fuse box 42, the input word line selection signal add_wordline is input. It is determined whether there are any defective cells in the word line corresponding to the result, and the result is transmitted to the comparator 44.

Accordingly, the comparison unit 44 analyzes the signal from the fuse box unit 42 and, when a redundancy address is input, disables the word line connected to the defective cell and repairs the repair word line connected to the spare cell. A signal for enabling the signal is sent to the driving devices brs0 to brs15.

For example, if it is assumed that the fuse of the fuse box fb0 is blown, the decoder 0 drives the driving element brs0 of the driving elements brs0, brs4, brs8, and brs12.

Thus, when the output signal addx_NK of the first buffer 34 is at the "high" level under the NK refresh mode, the driving element brs0 enables the repair word line rw10_1 on the left side. When the output signal of the first buffer 34 is at the "high" level (addxb_NK), the repair word line rw10_r on the right side is enabled on the contrary.

In other words, if the circuit is configured to select the left repair word line rw1i_1 when "addx_NK" is high under the NK refresh mode, the left repair word line rw1_1 is NK in one cell block by the high level "addx_NK". It is enabled in accordance with the refresh cycle to enable one word line for every NK word lines.

As described above, when the refresh request signal Refresh_requestb input to the first buffer 34 is "high" in the NK refresh mode, an access operation of the double word line structure is performed, and the refresh request signal is performed. If (Refresh_requestb) is "low", the normal NK refresh operation is performed. In other words, when the refresh request signal (refresh_requestb) indicating the start of refresh is enabled as "low", all of the "addx_NK and addxb_NK" outputs of the NAND gates ND3 and ND4 in the first buffer 34 become "high", The repair word line of the array is enabled at the same time without distinguishing between left and right.

7 is a configuration diagram of an example illustrating the improvement of the repair rate according to the embodiment of the present invention, and FIG. 8 is a configuration diagram of another example illustrating the improvement of the repair rate according to the embodiment of the present invention. In the case of the example, since the number of repair word lines is doubled, as compared with the related art, the repair success rate is increased by about 2 times as compared with FIGS. 3 and 4.

According to the present invention as described above, the word line connected to the gate of the switch transistor of the cell is switched from single to double structure by using a redundant row address fixed to a constant level in a device having an NK refresh cycle. The word lines can be arranged to the left and right of the entire cell array and can be controlled with surplus row addresses so that even if a defect occurs due to a cell defect, only one of the two word lines in one row is abandoned and the other word lines Can still be used, and the redundancy word line can likewise use one of two repair word lines in one row to repair defects throughout the whole row and the other for other loo defects.

That is, the repair rate can be improved by employing the double word line structure as the redundancy structure.

On the other hand, the present invention is not limited only to the above-described embodiments, but may be modified and modified without departing from the scope of the present invention.

Claims (8)

A semiconductor memory device comprising a cell block having a plurality of cell arrays, each cell array having a plurality of repair word lines, and capable of a repair operation on a word line where a defective cell is generated. Each repair word line in the cell array is divided into double repair word lines that are symmetrical to each other. Determining means for determining a cell array to which the defective cell belongs; Selection means for selecting a repair wordline for the defective cell; Setting means for setting one of the lines in the repair word line divided in accordance with a combination of a block set dividing address signal, a refresh mode designation signal, and a refresh request signal; Drive means connected to each repair word line divided into the left and right symmetric double repair word lines, And enabling one line of a corresponding repair word line divided in a corresponding cell array as the defective cell is generated. The method of claim 1, The setting means is configured to receive a differential amplifier for comparing the block set bipartition address signal and a reference voltage with each other, a first output terminal signal of the differential amplifier and the refresh mode designation signal, and output a signal to be fixed at a predetermined level. A second combination circuit that receives a first combination circuit, a second output terminal signal of the differential amplifier and the refresh mode designation signal, combines the first combination circuit, and outputs another signal to be fixed at a predetermined level together with a signal to be fixed at a predetermined level A first logic circuit unit configured to receive and logically combine the first output stage signal of the differential amplifier, the refresh mode designation signal, and the refresh request signal, and the second output stage signal, the refresh mode designation signal, and the refresh request signal of the differential amplifier And a second logic circuit for receiving and logically combining Redundancy Circuit. The method of claim 2, The first combination circuit is a low redundancy circuit, characterized in that the NAND gate, The method of claim 2, And said second combination circuit is a NAND gain. The method of claim 2, The first logic circuit unit includes an inverter for inverting the refresh mode designation signal, and a logic circuit for receiving and outputting an output signal of the inverter, a first output terminal signal of the differential amplifier, and a refresh request signal. Roo redundancy circuit. The method of claim 5, The logic circuit is a redundancy circuit, characterized in that the NAND gate. The method of claim 2, The first logic circuit unit includes an inverter for inverting the refresh mode designation signal, and a logic circuit for receiving and outputting an output signal of the inverter, a second output terminal signal of the differential amplifier, and a refresh request signal. Roo Redundancy Circuit The method of claim 7, wherein The logic circuit is a redundancy circuit, characterized in that the NAND gate.