JPH05282886A - Nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent the loss of data already written even if destruction occurs in the case of additional writing. CONSTITUTION:The nonvolatile semiconductor memory comprises memory means 1 having a memory cell array divided into blocks formed of a plurality of pages, reading means for reading data of a non-selected page in the block including a selected page before writing data of the selected page, and holding means 10 for holding the read data of the non-selected page until writing of data on the selected page is completed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a flash EEPRO.
The present invention relates to a non-volatile semiconductor memory device using M (especially NAND type EEPROM).

[0002]

2. Description of the Related Art Conventionally, a magnetic disk device has been widely used as a storage device of a computer system. However, since the magnetic disk device has a highly precise mechanical drive mechanism, it is weak against impact and heavy, and therefore has poor portability, consumes a large amount of power, is not easily driven by a battery, and cannot access at high speed.

Therefore, in recent years, development of a semiconductor memory device using an EEPROM has been advanced. Since the semiconductor memory device has no mechanical driving part, it is strong against impact, has light weight and is highly portable, and has low power consumption, so that it can be easily driven by a battery and has high speed access.

However, the EEPROM has a finite lifespan in the number of times of writing / erasing, and in order to secure its reliability, system control which is not necessary for the magnetic disk device is required.

As one of the EEPROMs, a NAND-type EEPROM capable of high integration is known. As shown in FIG. 6, a plurality of memory cells M _{1 to} M ₈ are connected in series so that their sources and drains are shared by adjacent ones to form one unit, and are connected to a bit line BL. is there. The memory cells M ₁ ~M ₈ generally has a FETMOS structure in which the control gate are laminated with the charge storage layer.
The memory cell array is integrated and formed in a p-type well formed on a p-type substrate or an n-type substrate. NAND type EEP
The drain side of the ROM is connected to the bit line BL via the selection gate S ₁ , and the source side is also connected to the source line (reference potential wiring) via the selection gate S ₂ . As shown in FIG. 7, the control gate CG of each of the memory cells M _{1 to} M ₈ is
_{1 to} CG ₈ are continuously connected in the row direction to form a word line. Usually, a set of memory cells connected to the same word line is called one page, and a set of pages sandwiched between a set of drain side and source side select gates is called one NAND block or simply one block. Normally, one block is the minimum unit that can be independently erased.

The operation of the NAND type EEPROM is as follows. Data is erased simultaneously for the memory cells in one NAND block. That is, the selected NAND
All control gates of the block are set to the reference potential V _SS, and the high voltage V _PP (for example, 20 V) is applied to the p-type well and the n-type substrate. As a result, in all the memory cells, electrons are emitted from the floating gate to the substrate, and the threshold value shifts in the negative direction. Usually, this state is defined as the "1" state. Chip erasing is performed by putting all NAND blocks in the selected state.

The data write operation is sequentially performed from the memory cell located farthest from the bit line BL. NAN
A high voltage V is applied to the selected control gate in the D block.
_PP (for example, 20 V) is applied, and the intermediate potential V _M (for example, 10 V) is applied to the other non-selected gates. Bit line B
V _SS or V _M is given to L depending on the data. When V _SS is applied to the bit line ("0" write), the potential is transmitted to the selected memory cell, and electron injection occurs in the floating gate. This shifts the threshold value of the selected memory cell in the positive direction. Normally, this state is defined as the "0" state. V _M is given to the bit line ("1" write)
No electron injection occurs in the memory cell, so the threshold remains unchanged and remains negative.

In the data read operation, the control gate of the selected memory cell in the NAND block is set to V _SS ,
The other control gates and select gates are set to V _CC to detect whether or not a current flows in the selected memory cell.

Here, a 4M bit NAND type EEPROM is used.
Conventional data writing will be described by taking a memory system using M as an example. 4M bit NAND type EEP
One page of the ROM has 512 bytes (1 byte is 8 bits), and one NAND block has 8 pages (512 × 8 =
4K bytes) and has 128 blocks. As described above, in the NAND type EEPROM, data writing is performed in page units in order from the page on the most source side. Further, in the NAND type EEPROM, since erasing cannot be performed in page units, it is necessary to erase blocks in order to rewrite data of a page in which data has already been written. However, when data is written only to a part of the pages in the NAND block (for example, when data is written only to 4 pages from the source side after erasing, the 4 pages on the drain side remain erased. It is possible to perform writing without additional block erasing in the additional writing to the remaining pages later. This is an effective means in terms of improving the data writing speed and reducing the number of writing / erasing. However, in this case, the data is not saved.

In the NAND type EEPROM,
Consider the destruction mode during operation. NAND type EEP
In the ROM, a high electric field is applied to the tunnel oxide film of the memory cell during the write operation, which may cause destruction. When the breakdown occurs, the insulating film between the floating gate and the control gate is also destroyed at the same time, and the control gate and the substrate may be short-circuited, resulting in a row defect (one page defect). When a row defect occurs in the NAND type EEPROM, the entire NAND block does not operate normally. This is because the word line must function properly as a transfer gate even when it is not selected, and if one page becomes defective, the data in the entire NAND block is destroyed or cannot be erased / written.

[0011]

As described above, the conventional N
In the AND-type non-volatile semiconductor memory device, if a NAND block in which data has already been partially written is destroyed when additional writing is performed later in a page in which the remaining data has not been written, the data is already written. There was a problem that the existing data might be lost.

The present invention has been made in view of the above problems. An object of the present invention is to prevent data already written from being lost even if destruction occurs during additional writing. It is an object of the present invention to provide a non-volatile semiconductor memory device that can maintain high reliability.

[0013]

In order to solve the above problems, the present invention firstly provides a memory having a non-volatile memory function, which comprises a memory cell array divided into blocks composed of a plurality of pages. Means and read means for reading data of a non-selected page in a block including the selected page before writing data to the selected page, and data of the read non-selected page for the selected page And a holding unit that holds the data until the writing of data to the storage unit is completed.

Secondly, in the first structure, the memory cell array is composed of a NAND type EEPROM,
The page from which data is read is selected NAND from the selected page
The gist is that the page is a non-selected page located on the source line side in the EEPROM.

Thirdly, in the first or second configuration, when the data writing to the selected page is not normally completed, the data held in the holding means does not include the selected page. The gist is to have a writing means for writing to another block.

Fourthly, in the above-mentioned first, second or third configuration, the reading means reads the data stored in the selected page itself before writing the data in the selected page, and the holding means. The gist is to retain the read data of the selected page itself until the data writing to the selected page is completed.

Fifth, in the above-mentioned fourth structure, the holding means holds the read data of the selected page itself after the data is modified.

[0018]

In the above structure, first, when additional writing to the selected page occurs, even if the memory cell is destroyed and the entire block becomes defective, the data already written to the non-selected page of the block. Is backed up by a holding means so it will not be lost.

Secondly, in the memory cell array composed of the NAND type EEPROM, since writing is normally performed in order from the source line side, the page from which data is read is
It is a non-selected page located on the source line side of the selected page.

Third, when data writing to the selected page is not normally completed and the entire block becomes defective, the data backed up by the holding means is written to another block to maintain high reliability. It becomes possible to do.

Fourth, when data is already stored in the selected page, the data is also backed up in the holding means, and higher reliability can be maintained.

Fifth, by correcting the read data of the selected page itself, such as the data to be additionally written, and holding the data in the holding means, it is possible to realize a wide backup system of the data.

[0023]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the structure of a nonvolatile semiconductor memory device. In the figure, reference numeral 1 denotes a NAND type EEPROM module as a memory means, which is composed of a memory cell array divided into blocks composed of a plurality of pages. The EEPROM module 1 is connected to a host system (not shown) via a host interface 2 connected by a data line. A multiplexer 9 and a data buffer 10 functioning as a holding unit are provided on the data line. Further, in the host interface 2, a data register 3, an address register 4, a count register 5, and a command register 6
And a status register 7 are provided. 11 is a control logic, 12 is an ECC (error correction code) generator / checker, 13 is an address generator,
Reference numeral 14 is a CPU that executes a control program such as writing and reading, 15 is a work RAM, and 16 is a control program ROM. The work RAM 15 is loaded with a management table for the user area of the EEPROM module 1, and the control program ROM 16 is used to store a series of control programs for writing data.

Next, the operation of the nonvolatile semiconductor memory device configured as described above will be described.

The operation of writing to the EEPROM module 1 will be described.

The host system sets the access start address in the address register 4 in the host interface 2, sets the sector length of the data to be accessed in the count register 5, and finally sets the write command in the command register 6. When an access command is written in the command register 6 of the host interface 2, the CPU 14 in the controller reads the access command in the command register 6 and writes a series of controls described below for writing the data stored in the control program ROM 16. Run the program. In the work RAM 15, when the memory device is activated, the management table for the user data area of the EEPROM module 1 is read from the EEPROM module 1.

FIG. 2 is a flow chart showing a procedure in which additional writing is performed later on a selected page in which the remaining data has not been written to the NAND block in which partial data has already been written.

The CPU 14 refers to the start address set in the host interface 2 and the address conversion table in the management table stored in the work RAM 15 to refer to the NAND assigned to the address to be written by the host system. A block on the type EEPROM 1 is determined (step 101). If the request from the host system does not rewrite all the data in this block, the data already written in the non-selected page in the block is read into the data buffer 10 in preparation for loss due to block destruction (no in step 102). , 103). Next, data transfer from the host system to the data buffer 10 as described in detail later, write processing of this transferred data, error processing, etc. are performed, and additional writing is performed on the selected page in the determined block. Is executed (steps 104 to 108).

FIG. 3 is a flowchart showing a procedure for reading data from the EEPROM module to the data buffer. First, the EEPROM module 1 is accessed through the multiplexer 9 to set the read mode,
Further, the data buffer 10 is set to the read mode (steps 201 and 202). The EEPROM physical address of the data already written in the block is set in the address generator 13 (step 20).
3) The head address of the area for storing this data is also set in the data buffer 10 as a write address to the data buffer (step 204). After this, the CPU
14 sends a command to the control logic 11 to execute a predetermined sequence for reading data. The control logic 11 sets the multiplexer 9 so that the read data from the EEPROM module 1 flows to the data buffer 10, and increments the content of the address generator 13 while reading out one page of predetermined data (step 205).
Further, the ECC generator / checker 12 is controlled so as to detect an error by using these data and the ECC code read accompanying this data. When the data for one page has been read, the CPU 14 checks the ECC generator / checker 12 for an error in the data (step 206). An error is detected (step 207)
Yes), and if it is a correctable error, the data in the data buffer 10 is corrected (y in step 208).
es, 209). In the case of an uncorrectable error, information on the detected error is saved in a predetermined area of the work RAM 15 for later error processing (step 208).
No, 210). The process of FIG. 3 is repeated until all the data in the non-overwritten portion of the block is read into the data buffer 10.

FIG. 4 is a flow chart showing the procedure for transferring write data from the host system to the data buffer. The CPU 14 sets the data buffer 10 in the write mode (step 301), and sets the address on the data buffer 10 in which the data transferred from the host system is stored as the write address to the data buffer 10 (step 302). .. afterwards,
The control logic 11 is instructed to transfer data for one sector from the host system. The control logic 11 controls the data buffer 10 and the host interface 2 so that the
When the data for the sector is received and this is completed, the CPU
14 is notified that the transfer is completed (step 30).
3). In the processing of FIG. 4, data to be transferred from the host system remains, and the NAN is set in the data buffer 10.
This continues as long as there is insufficient data for the block that is about to write to the D-type EEPROM 1. When the transfer from the host system is completed, this data will be N
It is written on the AND type EEPROM 1.

FIG. 5 shows the data in the data buffer NA.
6 is a flowchart showing a procedure for writing data in an ND type EEPROM. The CPU 14 initializes the EEPROM module 1 and the data buffer 10 if necessary (steps 401 and 402), sets the start address of the page to be written in the address generator 13 (step 403), and sets it in the data buffer 10. Sets the start address of the data to be written as the read address of the data buffer 10 (step 404). Then, the control logic 11 is instructed to execute a predetermined sequence for writing data. The control logic 11 is the multiplexer 9
Write data from the data buffer 10 is EEP
It is set so as to flow into the ROM module 1, and data is written while incrementing the contents of the address generator 13 (step 405). Also, the ECC generator / checker 12 is controlled to generate an ECC code from these data, and this code is also stored together with the data (step 406). If the data cannot be written normally, error processing is performed, and then the data in the data buffer 10 is written to the EEPROM module 1 as necessary for alternative processing or the like. When the writing is normally completed and all the data requested by the host system is completely stored or the processing is interrupted because the recovery from the error is impossible (step 408), the CPU 14 causes the status register 7 in the host interface 2 to operate. Is set to a predetermined code to notify the host system that the execution of the instruction is completed.

As described above, according to the present embodiment, when additional writing is performed later on a page in which the remaining data has not been written to a NAND block in which partial data has already been written, it is already written. By reading the data that had been written and saving it in the buffer memory, it is possible that the data might be destroyed during the write operation and its NA
Even if the entire ND block becomes defective, data will not be lost, and it becomes possible to maintain high reliability as a system.

The present invention is not limited to the above embodiment.
For example, consider that additional writing is performed on a page in which data has already been written without an erase operation. Of course, in this case, it is impossible to return a cell in which "0" is written (electron-injected and has a positive threshold value) to "1" data (erased state). It is only possible to rewrite a cell that holds "1" data to "0" data. In this case, according to the idea described above, it is easily conceivable that the data itself of the selected page must be read and held until the writing is completed at the time of the additional writing. The data read at this time may be held after being corrected for the data to be additionally written. Further, when the data writing to the selected page is not normally completed, a process of writing the data held in the data buffer to another block not including the selected page may be performed. As mentioned above,
The present invention can be variously modified and used without departing from the spirit thereof.

[0035]

As described above, according to the present invention,
First, before writing the data to the selected page, the data of the non-selected page in the block including the selected page is read and held by the holding means until the data writing to the selected page is completed. When writing to a page, even if the memory cell is destroyed and the entire block becomes defective, the data already written to the non-selected page of the block is not lost.

Secondly, in the memory cell array composed of the NAND type EEPROM, since the writing is normally performed in order from the source line side, the page from which data is read is the non-selected page located on the source line side with respect to the selected page. As a result, the read address can be set easily and reliably.

Thirdly, when the data writing to the selected page is not normally completed, the data held in the holding means is written to another block not including the selected page, so that the data is surely written. It can be maintained and high reliability can be obtained.

Fourth, when data is already stored in the selected page itself, the holding means holds the data until the data writing to the selected page is completed. The reliability can be obtained.

Fifth, since the read data of the selected page itself is corrected by the additional writing data and the like and then held by the holding means, higher reliability can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a nonvolatile semiconductor memory device according to the present invention.

FIG. 2 is a flowchart for explaining a process of additionally writing data to a selected page in this embodiment.

FIG. 3 is a flowchart for explaining a process of reading data from an EEPROM module to a data buffer in this embodiment.

FIG. 4 is a flowchart for explaining a transfer process of write data from a host system to a data buffer in this embodiment.

FIG. 5 is a flow chart for explaining a process of writing the data in the data buffer to the EEPROM module in the present embodiment.

FIG. 6 is an equivalent circuit diagram showing a cell configuration of a NAND type EEPROM.

FIG. 7 is an equivalent circuit diagram showing a memory cell array of a NAND type EEPROM.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 EEPROM module (memory means) 10 Data buffer (holding means) 14 CPU for executing reading and writing of data with respect to EEPROM module

Claims (5)

[Claims] 1. A memory means having a memory cell array divided into blocks composed of a plurality of pages, the memory means having a nonvolatile memory function, and the selected page before writing data to the selected page. It has a reading means for reading the data of the non-selected page in the containing block, and a holding means for holding the read data of the non-selected page until the data writing to the selected page is completed. Non-volatile semiconductor memory device. 2. The memory cell array is a NAND type EE
2. The non-volatile semiconductor memory device according to claim 1, wherein the page composed of a PROM and reading data is a non-selected page located on the source line side of the NAND type EEPROM with respect to the selected page. 3. A writing unit for writing the data held in the holding unit to another block that does not include the selected page when the data writing to the selected page is not normally completed. The non-volatile semiconductor memory device according to claim 1 or 2. 4. The reading means reads the data stored in the selected page itself before writing the data to the selected page, and the holding means transfers the read data of the selected page itself to the selected page. The non-volatile semiconductor memory device according to claim 1, wherein the data is held until data writing is completed. 5. The non-volatile semiconductor memory device according to claim 4, wherein the holding unit holds the read data of the selected page itself after the data is modified.