JP4561110B2 - MEMORY CONTROLLER, FLASH MEMORY SYSTEM PROVIDED WITH MEMORY CONTROLLER, AND FLASH MEMORY CONTROL METHOD - Google Patents

Description

  The present invention relates to a memory controller, a flash memory system including the memory controller, and a flash memory control method.

  In recent years, a flash memory is often used as a semiconductor memory used in a memory system such as a memory card or a silicon disk. This flash memory is a kind of non-volatile memory, and is required to retain data regardless of whether power is turned on.

  The NAND flash memory used in the above-described device has a memory cell unit when a memory cell is changed from an erased state (logical value “1”) to a written state (logical value “0”). However, when a memory cell is changed from a written state (logical value “0”) to an erased state (logical value “1”), it cannot be performed in units of memory cells. This can only be done with a predetermined erase unit (block) of memory cells. Here, the memory cell is changed from the erased state (logical value “1”) to the written state (logical value “0”), or from the written state (logical value “0”) to the erased state (logical value “0”). When the value is changed to “1”), a high voltage is applied to the memory cell to inject and discharge electrons.

  Data written to the flash memory is once held in a register in the flash memory and then copied from the register to each memory cell constituting the memory cell array. While the copying is being performed, the flash memory is in a busy state that does not accept other processing, and therefore, the flash memory cannot be accessed until the busy state is canceled. When performing this copying, a high voltage must be applied to the memory cell and electrons must be injected as described above, so the busy period during execution of the copying becomes longer and the processing efficiency of the writing process deteriorates. It is a factor to make.

In order to solve this problem, in Patent Document 1 (Japanese Patent Laid-Open No. 10-63442), a device is constituted by a plurality of chips of flash memory, and processing is sequentially performed from the flash memory in which the busy state is detected to be released. Is doing.
Japanese Patent Laid-Open No. 10-63442

  In the case of Patent Document 1 (Japanese Patent Laid-Open No. 10-63442), a signal indicating a busy state output from each flash memory must be detected individually. Therefore, a detection circuit and a signal line for detecting a busy state are provided for each flash memory. Must be provided. When the memory controller that controls this processing is packaged as an IC, it is necessary to provide as many input terminals (terminals that receive a signal indicating the busy state output from the flash memory) as the number of chips of the rush memory to be controlled. . Therefore, if the busy state is detected for each flash memory, the mounting efficiency is lowered.

  Accordingly, the present invention provides a memory controller that can improve the efficiency of write processing to a flash memory of a plurality of chips without detecting a busy state for each flash memory, a flash memory system including the memory controller, and a flash memory It is an object to provide a control method.

The purpose of the present invention, based on the request of the host system or al, a memory controller that controls access to the flash memory of the plurality of connected chips to a common bus, via the bus, said plurality of chips A data transfer function for transferring write data to the data holding unit in the flash memory, and an instruction to start a copy process for copying the write data held in the data holding unit to the memory cell in the flash memory , An instruction function given to the flash memories of the plurality of chips via the bus, and a control function of individually controlling the activation state of the flash memories of the plurality of chips, and the period during which the transfer function is operating, The control function sequentially activates the plurality of chips of flash memory one by one, whereby the host The write data given from the system is sequentially distributed to the plurality of chips of flash memory, and the control function activates all of the plurality of chips of flash memory during the period when the instruction function is operating. flash memory chips is achieved by a memory controller, wherein the benzalkonium to start the copying process based on a common instruction. The object of the present invention is also achieved by a flash memory system comprising the memory controller and a flash memory.

  In other words, in the writing process using the memory controller, a plurality of flash memories simultaneously copy data from a data holding unit (for example, a register) in the flash memory to a memory cell, so that any one of the flash memories is busy. It is possible to reduce the sum total of the periods in which the processing request is not accepted.

Further, according to the present invention, a signal which is output from the flash memory of the plurality of chips, a busy signal indicating that it is executing the copy processing, the detection function of detecting via a common signal line It is preferable that the transfer function and the instruction function do not operate during a period in which the detection function detects a busy signal .

The object of the present invention, based on the request of the host system or al, A method of controlling a flash memory to control access to the flash memory of the plurality of connected chips to a common bus, via the bus Te, start a transfer process of transferring write data in the data holding unit in the flash memory of the plurality of chips, the write data that is held in the data holding unit, a copying process for copying the memory cell in the flash memory Including an instruction process for giving an instruction to the flash memories of the plurality of chips via the bus, and a control process for individually controlling an activation state of the flash memories of the plurality of chips, while the transfer process is being executed. By sequentially activating the flash memories of the plurality of chips one by one by the control process, the host The write data given from the system is sequentially distributed to the flash memories of the plurality of chips, and during the execution of the instruction process, the flash memories of the plurality of chips are activated by activating all the flash memories of the plurality of chips by the control process. Is achieved by a flash memory control method characterized in that the copying process is started based on a common instruction .

  That is, in the writing process composed of the transfer process and the copying process, the copying process is simultaneously performed in a flash memory of a plurality of chips. Therefore, based on the copying process, it is possible to reduce the total sum of periods during which any of the flash memories is busy (a state where processing requests are rejected).

In addition, according to the present invention, a detection process for detecting a busy signal indicating that the copying process is being executed, which is output from each of the flash memories of a plurality of chips , through a common signal line. Further, it is preferable that the transfer process and the instruction process are not executed during a period in which a busy signal is detected by the detection process .

According to the present invention, since copying of data from a data holding unit (for example, a register) to a memory cell, which is performed in the flash memory, is performed simultaneously by a plurality of chip flash memories, any one of the flash memories It is possible to reduce the total sum of periods during which processing requests are not accepted (for example, a busy state to be described later). In addition, since the command for copying data from the data holding unit (for example, register) to the memory cell is simultaneously output to the flash memory of a plurality of chips, the total period during which the command is output can be reduced. . If the command for transferring the write data to the register in the flash memory is simultaneously output to the flash memories of a plurality of chips, the total period during which the command is output can be further reduced.

  Therefore, by using the present invention, it is possible to improve the efficiency of write processing for a plurality of chips of flash memory without detecting a busy state for each flash memory. Further, since it is not necessary to provide a detection circuit for detecting the busy state for each flash memory, a line for the detection circuit, a terminal, and the like, the mounting efficiency is not lowered.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[Description of flash memory system 1]
FIG. 1 is a block diagram schematically showing a flash memory system 1 according to the present invention. As shown in FIG. 1, the flash memory system 1 includes a flash memory 2 and a controller 3 that controls the flash memory 2. The flash memory system 1 is normally used by being detachably attached to the host system 4, and is used as a kind of external storage device for the host system 4.

  Examples of the host system 4 include various information processing apparatuses such as a personal computer and a digital still camera that process various information such as characters, sounds, and image information.

  The flash memory 2 is a device that executes reading or writing in units of pages and erasing in units of blocks. For example, one block is composed of 32 pages, and one page is a 512-byte user area and a 16-byte redundant area. It is configured.

  The controller 3 includes a host interface control block 5, a microprocessor 6, a host interface block 7, a work area 8, a buffer 9, a flash memory interface block 10, an ECC (error collection code) block 11, And a flash memory sequencer block 12. The controller 3 constituted by these functional blocks is integrated on one semiconductor chip. The function of each block will be described below.

  The microprocessor 6 is a functional block that controls the operation of the entire functional blocks constituting the controller 3.

  The host interface control block 5 is a functional block that controls the operation of the host interface block 7. Here, the host interface control block 5 includes an operation setting register (not shown) for setting the operation of the host interface block 7, and the host interface block 7 operates based on the operation setting register.

The host interface block 7 is a functional block that exchanges data, address information, status information, and external command information with the host system 4. That is, when the flash memory system 1 is attached to the host system 4, the flash memory system 1 and the host system 4 are connected to each other via the external bus 13, and in this state, the host system 4 connects to the flash memory system 1. The supplied data is taken into the controller 3 through the host interface block 7 as an entrance, and the data supplied from the flash memory system 1 to the host system 4 is supplied to the host system 4 through the host interface block 7 as an exit. Is done.

  Further, the host interface block 7 includes a task file register (not shown) for temporarily storing a host address and an external command supplied from the host system 4 and an error register (not shown) set when an error occurs. ) Etc.

  The work area 8 is a work area in which data necessary for controlling the flash memory 2 is temporarily stored, and is a functional block configured by a plurality of SRAM (Static Random Access Memory) cells.

  The buffer 9 is a functional block that temporarily holds data read from the flash memory 2 and data to be written to the flash memory 2. That is, data read from the flash memory 2 is held in the buffer 9 until the host system 4 can receive the data, and data to be written to the flash memory 2 is stored in the buffer 9 until the flash memory 2 becomes writable. Retained.

  The flash memory sequencer block 12 is a functional block that controls the operation of the flash memory 2 based on internal commands. The flash memory sequencer block 12 includes a plurality of registers (not shown), and information necessary for executing an internal command is set in the plurality of registers. When information necessary for executing an internal command is set in the plurality of registers, the flash memory sequencer block 12 executes processing based on the information. Here, the “internal command” is a command given from the controller 3 to the flash memory 2 and is distinguished from an “external command” which is a command given from the host system 4 to the flash memory system 1.

  The flash memory interface block 10 is a functional block that exchanges data, address information, status information, internal command information, device ID information, and the like with the flash memory 2 via the internal bus 14.

The ECC block 11 generates an error correction code to be added to data to be written to the flash memory 2, and detects and corrects errors included in the read data based on the error correction code added to the read data. Function block.
[Description of memory cell]
Next, a specific structure of the memory cell 16 constituting the flash memory 2 shown in FIG. 1 will be described with reference to FIGS.

  FIG. 2 is a cross-sectional view schematically showing the structure of the memory cell 16 constituting the flash memory. As shown in the figure, the memory cell 16 includes an N-type source diffusion region 18 and a drain diffusion region 19 formed in the P-type semiconductor substrate 17, and a P between the source diffusion region 18 and the drain diffusion region 19. Tunnel oxide film 20 formed to cover type semiconductor substrate 17, floating gate electrode 21 formed on tunnel oxide film 20, insulating film 22 formed on floating gate electrode 21, and insulating film 22 The control gate electrode 23 is formed on the top. A plurality of memory cells 16 having such a configuration are connected in series in the flash memory.

The memory cell 16 has either an “erased state (a state where no electrons are accumulated)” or a “written state (a state where electrons are accumulated)” depending on whether electrons are injected into the floating gate electrode 21 or not. Is shown. Here, one memory cell 16 corresponds to 1-bit data, the “erased state” of the memory cell 16 corresponds to data of “1” of the logical value, and the “written state” of the memory cell 16 corresponds to the logical value. Corresponds to “0” data.

  In the “erased state”, since electrons are not accumulated in the floating gate electrode 21, when the read voltage (high level voltage) is not applied to the control gate electrode 23, the source diffusion region 18 and the drain diffusion region 19 In the meantime, no channel is formed on the surface of the P-type semiconductor substrate 17, and the source diffusion region 18 and the drain diffusion region 19 are electrically insulated. On the other hand, when a read voltage (high level voltage) is applied to the control gate electrode 23, a channel (not shown) is formed on the surface of the P-type semiconductor substrate 17 between the source diffusion region 18 and the drain diffusion region 19. The source diffusion region 18 and the drain diffusion region 19 are electrically connected by this channel.

  That is, in the “erased state”, when the read voltage (high level voltage) is not applied to the control gate electrode 23, the source diffusion region 18 and the drain diffusion region 19 are electrically insulated, and the control gate electrode 23 In the state where the read voltage (high level voltage) is applied, the source diffusion region 18 and the drain diffusion region 19 are electrically connected.

  FIG. 3 is a cross-sectional view schematically showing the memory cell 16 in the “written state”. As shown in the figure, the “written state” refers to a state in which electrons are accumulated in the floating gate electrode 21. Since the floating gate electrode 21 is sandwiched between the tunnel oxide film 20 and the insulating film 22, the electrons once injected into the floating gate electrode 21 stay in the floating gate electrode 21 for a very long time. In this “write state”, since electrons are accumulated in the floating gate electrode 21, regardless of whether or not a read voltage (high level voltage) is applied to the control gate electrode 23, A channel 24 is formed on the surface of the P-type semiconductor substrate 17 between the drain diffusion region 19. Therefore, in the “written state”, the source diffusion region 18 and the drain diffusion region 19 are always electrically connected by the channel 24 regardless of whether or not a read voltage (high level voltage) is applied to the control gate electrode 23. Connection state.

  Whether the memory cell 16 is in an erased state or a written state can be read as follows. A plurality of memory cells 16 are connected in series in the flash memory. A low level voltage is applied to the memory cell 16 selected in the series body, and a high level voltage is applied to the control gate electrode 23 of the other memory cells 16. In this state, it is detected whether or not the serial body of the memory cells 16 is in a conductive state. As a result, if the serial body is in a conductive state, it is determined that the selected memory cell 16 is in a written state, and if it is in an isolated state, it is determined that the selected flash memory cell 16 is in an erased state. The In this way, it is possible to read out whether the data held in any memory cell 16 included in the serial body is “0” or “1”.

When the memory cell 16 in the erased state is changed to the written state, a high voltage is applied so that the control gate electrode 23 is on the high potential side, and electrons are injected into the floating gate electrode 21 through the tunnel oxide film 20. To do. At this time, an FN (Fowler-Nordheim) tunnel current flows and electrons are injected into the floating gate electrode 21. On the other hand, when changing the flash memory cell 16 in the written state to the erased state, a high voltage is applied to the control gate electrode 23 on the low potential side, and the voltage is stored in the floating gate electrode 21 via the tunnel oxide film 20. Discharge electrons.
[Description of flash memory structure]
Next, the memory structure of the flash memory will be described. FIG. 4 schematically shows a memory structure of the flash memory. As shown in FIG. 4, the flash memory is composed of pages, which are processing units for reading and writing data, and blocks, which are data erasing units.

  The page is composed of, for example, a user area 25 of 512 bytes and a redundant area 26 of 16 bytes. The user area 25 is an area mainly storing data supplied from the host system 4, and the redundant area 26 stores additional information such as an error collection code, a corresponding logical block address and a block status. It is an area.

  The error collection code is additional information for correcting an error included in the data stored in the user area 25, and is generated by an ECC block. Based on the error collection code, if the number of errors included in the data stored in the user area 25 is equal to or less than a predetermined number, the error is corrected.

  The corresponding logical block address indicates to which logical block address the block corresponds when data is stored in the block. If no data is stored in the block, the corresponding logical block address is not stored. Therefore, whether or not the block is an erased block depends on whether or not the corresponding logical block address is stored. Judgment can be made. That is, if the corresponding logical block address is not stored, it is determined that the block is an erased block.

  The block status is a flag indicating whether or not the block is a bad block (a block in which data cannot be normally written). If it is determined that the block is a bad block, the block status is bad. A flag indicating a block is set.

  In addition, since data cannot be overwritten in the flash memory, when data is rewritten, new data (data after rewriting) is written to the erased block that has been erased, and old data (before rewriting) is written. A process of erasing a block in which (data) has been written must be performed. At this time, since erasure is processed in units of blocks, data of all pages of a block including a page in which old data (data before rewriting) is written is erased. Therefore, when data is rewritten, it is necessary to perform processing for moving the data of other pages of the block including the page to be rewritten to the erased block.

When rewriting data as described above, since the data after rewriting is written in a different block from before rewriting, the logical block address given from the host system side and the physical block which is the block address in the flash memory The correspondence with the address changes dynamically every time data is rewritten. For this reason, an address conversion table showing the correspondence between logical block addresses and physical block addresses is required. This address conversion table is created based on the corresponding logical block address written in the redundant area of the flash memory, and each time the data is rewritten, the correspondence relationship of the part involved in the rewriting is updated.
[Description of writing to flash memory]
Within the flash memory, the received data is temporarily held in a register, and the data held in the register is written into each memory cell constituting the memory cell array. In the copying operation from this register to the memory cell array, as described above, a high voltage is applied to the memory cell and the logical value of the bit corresponding to the memory cell is changed. The processing efficiency of embedded processing is reduced.

Further, while executing data copying from the register to the memory cell array, the flash memory outputs a signal indicating a busy state (hereinafter, a signal indicating whether it is in a busy state is referred to as a busy signal), and the like. The processing request is not accepted. Here, if the busy signal is detected for each chip (chip of the flash memory), it is possible to distinguish between a busy chip and a non-busy chip. However, a detection circuit for detecting a busy signal must be provided for each chip in the memory controller, and each chip and the detection circuit must be connected in a line. On the other hand, when the busy signal output from each chip is detected by one detection circuit, the busy signal output from each chip is output to the common line. Accordingly, it can be understood that any one of the plurality of chips is busy, but a chip that is busy and a chip that is not busy cannot be distinguished. In other words, if the line that outputs the busy signal is a common line, only one detection circuit or line that outputs the busy signal may be provided, but no other processing can be performed when any of the chips is busy. Therefore, in the write process according to the present invention, the write process is performed by shortening the period during which the line outputting the busy signal (common line) shows the busy state (the period during which any chip is in the busy state). The processing efficiency is improved.

  Here, in order to compare with the writing process according to the present invention, a conventional writing process (when a line outputting a busy signal is a common line) will be described with reference to FIG. FIG. 7 shows signal waveforms in the writing process to the flash memory of chip 0 and signal waveforms in the writing process to the flash memory of chip 1.

  7, S21 indicates a signal supplied to the data bus of the flash memory, S22 indicates a signal supplied to the chip enable terminal of the flash memory of chip 0, and S23 indicates a chip enable terminal of the flash memory of chip 1. S24 indicates a signal to be supplied, and S24 indicates a signal of a line (common line) from which the flash memory outputs a busy signal. Here, the data bus is shared by the flash memories of chip 0 and chip 1, and the line for outputting the busy signal is a common line of the flash memories of chip 0 and chip 1. The flash memories of chip 0 and chip 1 are activated when the signal supplied to the chip enable terminal is at a low level. Further, the flash memories of chip 0 and chip 1 output a low level signal indicating the busy state during the busy state.

  In the writing process to the flash memory of the chip 0, the signal supplied to the chip enable terminal of the flash memory of the chip 0 becomes a low level (S22), and the write data is flashed to the data bus during this low level period. A command C for transferring to a register in the memory, a write destination address A, write data D0 to Dn, and a command C ′ for copying the data held in the register to the memory cells constituting the memory cell array are sequentially supplied. (S21). Here, when the flash memory of the chip 0 starts the operation of copying the data held in the register to the memory cell specified by the address A based on the command C ′, the flash memory of the chip 0 is busy. And a low level signal indicating a busy state is output. Further, since the flash memory of the chip 0 outputs a low level signal indicating the busy state, the common line for outputting the busy signal is also set to the low level indicating the busy state (S24).

During the low level period when the common line that outputs the busy signal is in a busy state, no flash memory can be accessed, so the common line that outputs the busy signal after the busy state is released is at the high level. Then, the next process is started. That is, the writing process to the flash memory of the chip 1 is started after the common line for outputting the busy signal becomes high level. In the writing process to the flash memory of the chip 1, the signal supplied to the chip enable terminal of the flash memory of the chip 1 becomes a low level (S23), and the write data is transferred to the data bus during the low level period. A command C to be transferred to a register in the flash memory, a write destination address A, write data D0 to Dn, and a command C ′ for copying the data held in the register to the memory cells constituting the memory cell array are sequentially supplied. (S21). Here, when the flash memory of the chip 1 starts the operation of copying the data held in the register to the memory cell designated by the address A based on the command C ′, the flash memory of the chip 1 is busy. And a low level signal indicating a busy state is output. Further, since the flash memory of the chip 1 outputs a low level signal indicating the busy state, the common line for outputting the busy signal is also set to the low level indicating the busy state (S24).

  As described above, in the conventional writing process, every time data for one page, which is a processing unit of the writing process, is written, the common line for outputting the busy signal becomes a low level indicating a busy state. Accordingly, if the busy state period generated by one write process is T, the busy state period (total) generated by the write process for M pages is T × M.

  Next, the writing process according to the present invention will be described with reference to FIG. FIG. 5 shows signal waveforms when writing processing is performed on the flash memories of chip 0 to chip N. In FIG. 5, S11 indicates a signal supplied to the data bus of the flash memory, S12 indicates a signal supplied to the chip enable terminal of the flash memory of chip 0, and S13 indicates a chip enable terminal of the flash memory of chip 1. S14 indicates a signal supplied to the chip enable terminal of the flash memory of chip N, and S15 indicates a signal of a line (common line) from which the flash memory of chip 0 to chip N outputs a busy signal. Show. Here, the data bus is shared by the flash memories of chip 0 to chip N, and a line for outputting a busy signal is a common line of the flash memories of chip 0 to chip N. The flash memories of chip 0 to chip N are activated when the signal supplied to the chip enable terminal is at a low level. The flash memories of chip 0 to chip N output a low level signal indicating the busy state during the busy state.

  In the write processing shown in FIG. 5, the write data is sequentially transferred to the registers in the flash memory of chip 0 to chip N, and then the copy from the register to the memory cell array is performed in the flash memory of chip 0 to chip N. Done at the same time.

  In the operation of transferring the write data to the registers in the flash memories of chip 0 to chip N, the signals supplied to the chip enable terminals of the flash memories of chip 0 to chip N are sequentially lowered (S12, S13, S14). During this low level period, a command C for transferring write data to a register in the flash memory, a write destination address A, and write data D0 to Dn are sequentially supplied to the data bus (S11). Here, during the period when the signal supplied to the chip enable terminal of the flash memory of chip 0 is at a low level (S12), the signals (command C, address A, data D0 to Dn) supplied to the data bus are During the period when the signal supplied to the chip enable terminal of the flash memory of chip 1 is at a low level (S13), the signal supplied to the data bus (command C, address A, data D0 to Dn) are valid for the flash memory of chip 1, and in the same manner, during the period when the signal supplied to the chip enable terminal of the flash memory of chip N is at a low level (S14), The supplied signals (command C, address A, data D0 to Dn) are valid for the flash memory of chip N.

In the transfer operation, the write data transferred to the registers in the flash memory of chip 0 to chip N is copied to the memory cells constituting the memory cell array. All the supplied signals become low level (S12, S13, S14), and during this low level period, the data held in the register is copied to the memory cells constituting the memory cell array for the data bus. Command C ′ is supplied (S11). Here, since the command C ′ is valid for all the flash memories from chip 0 to chip N, the command C ′ is held in the register in the memory cell specified by address A in each flash memory of chip 0 to chip N. The operation of copying the stored data is started. When this copying operation is started, all the flash memories of chip 0 to chip N are in a busy state and output a low level signal indicating the busy state. Therefore, the common line for outputting the busy signal is also a low level indicating the busy state. (S15). The common line for outputting the busy signal is held at a low level until the busy states of the flash memories of chip 0 to chip N are all released, but the copying operation in the flash memories of chip 0 to chip N proceeds simultaneously. The period when the common line for outputting the busy signal is low is almost the same as the period of the busy state that occurs when each of the flash memories of chip 0 to chip N is performing the copying operation alone.

  In the writing process according to the present invention, the period during which the common line for outputting the busy signal is at a low level is reduced according to the number of flash memories (the number of chips) simultaneously performing the copying operation. For example, when a period of busy state that occurs in one writing process (copying operation) is T and a writing process for M pages is performed in the conventional writing process, the common line that outputs the busy signal becomes low level. The total period is TxM. On the other hand, when the write process of the same number of pages is performed in the write process according to the present invention (the write process in which the flash memory of N + 1 chips simultaneously performs the copying operation), the common line for outputting the busy signal becomes low level. The total period is T × M / (N + 1). In addition, since the number of times of outputting the command C ′ for copying the data held in the register to the memory cells constituting the memory cell array is reduced from M times to M / (N + 1) times, the command C ′ is output. Such time is also shortened.

  In the write process shown in FIG. 5, a command C for transferring write data to a register in the flash memory is supplied to each flash memory of chip 0 to chip N. As shown in the write process of FIG. In addition, the command C may be simultaneously supplied to the rush memories of the chip 0 to the chip N. In this process, a command C for transferring write data to a register in the flash memory with all the signals supplied to the chip enable terminals of the flash memories of chip 0 to chip N being at a low level (S12, S13, S14). Is supplied (S11 ′). Since the command C is valid for all the flash memories of the chip 0 to the chip N, the write destination address A and the write data D0 to Dn are sequentially supplied to each flash memory thereafter (S11). '). Therefore, in this process, the time taken to output the command C is shortened.

  In the write processing according to the present invention, the number of chips of the flash memory that simultaneously performs the copying operation is not particularly limited. However, if at least two chips of the flash memory simultaneously perform the copying operation, the common line that outputs the busy signal has a low level. Is reduced by 50%.

FIG. 1 is a block diagram schematically showing a flash memory system according to the present invention. FIG. 2 is a cross-sectional view schematically showing the structure of the memory cell constituting the flash memory. FIG. 3 is a cross-sectional view schematically showing a memory cell in a written state. FIG. 4 is a diagram schematically showing the structure of the address space of the flash memory. FIG. 5 is a waveform diagram showing signals input to the flash memory and signals output from the flash memory (write processing according to the present invention). FIG. 6 is a waveform diagram showing signals input to the flash memory and signals output from the flash memory (write processing according to the present invention). FIG. 7 is a waveform diagram showing signals input to the flash memory and signals output from the flash memory (conventional write processing).

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Flash memory system 2 Flash memory 3 Controller 4 Host computer 5 Host interface control block 6 Microprocessor 7 Host interface block 8 Work area 9 Buffer 10 Flash memory interface block 11 ECC block 12 Flash memory sequencer block 13 External bus 14 Internal bus 16 Memory Cell 17 P-type semiconductor substrate 18 Source diffusion region 19 Drain diffusion region 20 Tunnel oxide film 21 Floating gate electrode 22 Insulating film 23 Control gate electrode 24 Channel 25 User region 26 Redundant region

Claims (5)

Based on the request of the host system or al, a memory controller that controls access to the flash memory of the plurality of connected chips to a common bus,
A data transfer function for transferring write data to a data holding unit in the flash memory of the plurality of chips via the bus ;
An instruction function for giving an instruction to start a copying process for copying write data held in the data holding unit to a memory cell in the flash memory to the flash memories of the plurality of chips via the bus ;
A control function for individually controlling the activation state of the flash memory of the plurality of chips ,
During the period when the transfer function is operating, the control function sequentially activates the flash memories of the plurality of chips one by one, so that the write data given from the host system is transferred to the flash memories of the plurality of chips. Sorted sequentially,
During the period when the instruction function is operating, the control function activates all of the flash memories of the plurality of chips, so that the flash memories of the plurality of chips start the copying process based on a common instruction. A memory controller featuring. Wherein a plurality of chips signals outputted from the flash memory, a busy signal indicating that it is executing the copy processing, further comprising a detection function of detecting via a common signal line,
The memory controller of claim 1 wherein the detection period that detects a busy signal, characterized in that the transfer function and the indicating function is configured not to operate. Flash memory system comprising: a flash memory of the memory controller and a plurality of chips according to claim 1 or 2. Based on the request of the host system or al, A method of controlling a flash memory to control access to the flash memory of the plurality of connected chips to a common bus,
A transfer process for transferring write data to a data holding unit in the flash memory of the plurality of chips via the bus ;
The write data that is held in the data holding unit, an instruction to start the copying process for copying the memory cell in the flash memory, via said bus, the instruction processing to be supplied to the flash memory of the plurality of chips,
Control processing for individually controlling the activation state of the flash memory of the plurality of chips ,
During the execution of the transfer process, the plurality of chips of flash memory are sequentially activated one by one by the control process, so that write data given from the host system is sequentially distributed to the plurality of chips of flash memory. ,
During execution of the instruction process, the control process activates all the flash memories of the plurality of chips, so that the flash memories of the plurality of chips start the copying process based on a common instruction. Flash memory control method. A detection process for detecting, via a common signal line, a busy signal indicating that the copying process is being performed, which is a signal output from each of the flash memories of a plurality of chips ,
5. The flash memory control method according to claim 4 , wherein the transfer process and the instruction process are not executed during a period in which a busy signal is detected by the detection process.