JPH05342891A - Nonvolatile semiconductor storage device - Google Patents

Abstract

(57) [Summary] [Object] An object of the present invention is to speed up the operation by omitting unnecessary writing operations or shortening the rewriting time. A data detection means 9 for detecting whether or not all write data to a predetermined unit of data write area in the memory means 1 is data for maintaining the erased state of the memory cell, and the write data is all erased for the memory cell. And a write mode terminating unit 8 for terminating the write mode when it is detected that the data is the state-maintaining data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a flash EEPRO.
The present invention relates to a nonvolatile semiconductor memory device using M (especially NAND type EEPROM).

[0002]

2. Description of the Related Art Conventionally, a magnetic disk device has been widely used as a storage device of a computer system. However, since the magnetic disk device has a highly precise mechanical drive mechanism, it has weaknesses against impacts and is heavy and therefore poor in portability, consumes a large amount of power, is not easily driven by a battery, and cannot be accessed at high speed.

Therefore, in recent years, development of a semiconductor memory device using an EEPROM has been advanced. Since the semiconductor memory device has no mechanical driving part, it is strong against impact, has light weight and is highly portable, and has low power consumption, so that it can be easily driven by a battery and has high speed access.

However, the EEPROM has a finite lifespan in the number of times of writing / erasing, and in order to secure its reliability, system control which is not necessary for the magnetic disk device is required.

As one of the EEPROMs, a NAND type EEPROM capable of high integration is known. this is,
A plurality of memory cells are connected in series so that their sources and drains are shared by adjacent ones to form one unit, and are connected to a bit line. The memory cell usually has a FETMOS structure in which a charge storage layer and a control gate are stacked. The memory cell array is integrated and formed in a p-type well formed on a p-type substrate or an n-type substrate. NAND type EE
The drain side of the PROM is connected to the bit line via the selection gate, and the source side is also connected to the source line (reference potential wiring) via the selection gate. The control gates of the memory cells are continuously connected in the row direction to form word lines. Usually, a set of memory cells connected to the same word line is 1
A page is called a page, and a set of pages sandwiched between a set of drain-side and source-side select gates is called one NAND block or simply one block. Normally, one block is the minimum unit that can be independently erased.

The operation of the NAND type EEPROM is as follows. Data is erased simultaneously for the memory cells in one NAND block. That is, the selected NAND
All control gates of the block are set to the reference potential VSS and p
High voltage VPP (eg, 20V) on the well and n-type substrate
Is applied. As a result, in all the memory cells, electrons are emitted from the floating gate to the substrate, and the threshold value shifts in the negative direction. Usually, this state is defined as the "1" state. Chip erasing is performed by putting all NAND blocks in the selected state.

The data write operation is sequentially performed from the memory cell located farthest from the bit line. NAND
A high voltage VPP is applied to the selected control gate in the block.
(For example, 20 V) is applied, and the intermediate potential VM (for example, 10 V) is applied to the other non-selected gates. Further, VSS or VM is given to the bit line according to the data. When VSS is applied to the bit line ("0" write), the potential is transmitted to the selected memory cell, and electron injection occurs in the floating gate. This shifts the threshold value of the selected memory cell in the positive direction. Normally, this state is defined as the "0" state. No electron injection occurs in the memory cell in which VM is applied to the bit line ("1" write), and therefore the threshold value remains unchanged and remains negative. The data read operation is performed by setting the control gate of the selected memory cell in the NAND block to VSS and the other control gates and select gates to VCC to detect whether or not a current flows in the selected memory cell. The read data is latched by the sense amplifier / data latch circuit.

Here, based on FIG. 10, a conventional NAND
The write verify method in the EEPROM will be described. There is a sense amplifier / data latch circuit (FF) composed of a CMOS flip-flop, and the first output thereof is an E type N-channel MOS controlled by ΦF.
It is connected to the bit line BLi via the transistor Qn7. E type n controlled by the first output of the flip-flop FF is provided between the bit lines BLi and VCC.
E-type n-channel MOS transistor Qn9 controlled by channel MOS transistor Qn8 and signal ΦV
Are connected in series. An E type p-channel MOS transistor Qp5 that precharges the bit line and an E type n-channel MOS transistor Qn10 that discharges the bit line are connected. Also flip-flop FF
Detection transistor Qn11 which receives the second output of
Thus, the sense lines VDTC and VSS are connected.

At the time of writing, F is written when "1" is written.
"H" is latched at the bit line side node of F, and the intermediate potential is sent to the bit line. FF when writing "0"
"L" is latched at the node on the bit line side of, and VSS is transferred to the bit line.

In the write confirmation operation, when Qn7 is OFF, the precharge signal ΦP bar is set to "L" to precharge the bit line to VCC. Then ΦP ▲
The bar ▼ becomes "H", and the bit line becomes floating. In this state, the write data is held in the FF. After this, the selection gate and the control gate are driven.
Here, if the memory cell is a D type, the bit line is V
It is discharged to SS. If the memory cell is of the E type, the bit line maintains the VCC level. Select gate and
After the control gate is reset, verify signal ΦV
Becomes "H", and the bit line holding "1" data is charged to VCC-VTH. After that, after deactivating the CMOS inverter that constitutes the FF, Qn7 is turned on, the potential of the bit line is sensed and latched, and it is used as rewrite data. That is, "H" is the bit line for writing "1", and the bit line for writing "0" is
"H" is latched for those that have been sufficiently written. Bit lines for "0" writing, "L" is latched only for those for which writing is insufficient. Rewriting continues until "H" is latched in the bit line side nodes of all FFs.

This is detected as follows. Sense transistors of all FFs are connected to the sense line VDTC. VDTC is connected to the p-channel transistor. After the above-mentioned latch is completed, the p-channel transistor is activated for a predetermined time. At this time, if writing of all bits is completed, all the detection transistors are in the OFF state, so VDTC is charged to VCC. If there are cells that are underwritten,
Since the detection transistor corresponding to that bit line is in the ON state, the potential of VDTC decreases to VSS.
By detecting the potential of VDTC, whether or not the writing is completed is collectively performed (that is, the address is changed,
It can be detected (rather than reading all bits).

Here, consider a case where all the data on one page is "1" (keeps the erased state). In this case, since the state of the memory cell does not change, it is not necessary to perform the write operation originally, but the conventional NAND type EEPROM performs the same write operation as usual because it does not make such a judgment. That is, as shown in the flowchart of FIG. 11, first, after setting the write mode (step 30
1) Intermediate potential is applied to all bit lines on one page
The data of 1 "write is set (step 302),
VPP is applied to the control gate for a predetermined time, and the operation of writing "1" is performed (step 303). After that, the verify operation described above is performed. As described above, the conventional
Even if all "1" s are written to the page, the VP is output for the predetermined time.
Since P is applied and the verify operation is required, there is a problem that it takes time.

On the other hand, here, a 4M bit NAND type EEP
A conventional file management method in a memory device using a ROM will be described. 4Mbit NAND type EEPR
One page of the OM has 512 bytes (in addition, it has several bytes of redundant data area.) One NAND block has 8 pages (4 Kbytes + redundant data area).
It has 8 blocks (1024 pages). A redundant block for relieving the initial failure is also provided, but it will not be described here. In the memory device using the block erasable EEPROM, the basic unit for storing data is a byte or page smaller than the block of the erasing unit, so that the stored data is also managed in this unit. .. The EEPROM has a finite lifespan in the number of writing / erasing, and if the rewriting of data concentrates in a specific area where the file management information and the dictionary file are stored, the life of the chip itself is shortened. An operation in which the storage position of a file that is frequently rewritten is not fixed is performed for each unit of data management described above.

[0014]

As described above, the conventional N
The AND-type EEPROM has a problem that it takes time because VPP is applied for a predetermined time and a verify operation is required even when all "1" s are written in one page.
Further, regarding the file management method, for example, page-based management has been performed, so that one type of file is discretely stored and held in a plurality of NAND blocks as shown in FIG. For example, in a NAND type EEPROM in which one block consists of 8 pages, when a file of 8 pages in size is stored, the worst case is 8
It is stored separately on each NAND block, and is stored in the page on the most drain side in the block.
Consider rewriting this file in the situation where other file information is written in other pages. First, the data written in a page other than the page for which the first NAND block is rewritten is read page by page and saved in the buffer memory. In the NAND type EEPROM, erasing is performed in NAND block units. Therefore, it is necessary to save data other than the page to be rewritten, then erase the block and rewrite. NAN consisting of 512 bytes per page
In case of D-type EEPROM, it takes about 50 to read one page.
It takes μsec. Since this is performed for 7 pages, it takes about 350 μsec. Next, regarding block erasing, this takes about 10 msec. Next, the data for seven pages saved in the buffer memory first is written in page units. Including a verify operation after writing, it takes 1 msec as a typical value per page. Therefore, page 7 requires 7 msec. Furthermore, the writing time of the page itself to be rewritten requires 1 msec. Therefore, it takes about 20 msec per block, and it takes 160 msec in total to rewrite a file of 8 blocks, that is, 8 pages. Further, each page of 8 blocks (64 pages in total) is rewritten once. As described above, when the contents of a file are divided into a plurality of blocks and stored, the rewriting time is long and the number of rewritings is also large, which shortens the rewriting life of the memory system. .. This becomes a larger problem as the size of the file becomes larger and the number of pages constituting one block becomes larger (for example, 1 block has 16 pages structure).

The present invention has been made in view of the above problems, and an object of the present invention is to provide a nonvolatile semiconductor memory device capable of speeding up by omitting unnecessary writing operations or shortening rewriting time. ..

[0016]

In order to solve the above-mentioned problems, the present invention firstly provides a memory means having a predetermined unit of data writing area composed of a plurality of memory cells,
Data detection means for detecting whether or not all the write data in the predetermined unit is data for maintaining the erased state of the memory cell, and the write data in the predetermined unit for all the erased state of the memory cell by the data detection means The gist is to have a write mode terminating means for terminating the write mode when it is detected that the data is to be kept.

Secondly, it has a memory means having a memory cell array divided into a plurality of blocks, and a management means for managing so that a file having a data amount equal to or smaller than the block size is stored in one of the blocks. That is the summary.

Thirdly, it has a memory means having a memory cell array divided into a plurality of blocks, and a management means for managing so that only one type of file is stored in one block. To do.

Fourthly, in the third structure,
The summary is that the number of blocks used for storing a file of a type is N or less N = [(data amount / block size) +1] (however, () is an integer rounded down to the nearest whole number). To do.

Fifth, the memory means having a memory cell array divided into a plurality of blocks and the number of the blocks used for storing one type of file are N = [(data amount / block size) +2] (However, it is a gist to have a management means for managing such that the number is within N of (integers with decimal points omitted).

[0021]

In the above structure, firstly, when all the write data to one page, which is the data write area of a predetermined unit, is data to be kept in the erased state, for example, "1", an unnecessary write operation is performed. Can be omitted,
Higher speed is achieved.

Second, if one block consists of eight pages, for example, a file having a size of eight pages is stored in one block. Now, when the rewriting time of this file is estimated, since all pages are rewritten first, it is not necessary to save the data in the buffer memory. Next, it takes 10 msec to erase the block. 8 more
1mse per page for writing page data
c, a total of 8 msec is required, and a total rewriting time of 18 msec is required. In addition, rewriting is performed once for eight pages. When this result is compared with the conventional example in which the file is distributed and stored over 8 blocks, the rewriting time is reduced to about 1/10 and the number of rewritings is also greatly reduced to 1/8. As described above, according to the present invention, it is possible to reduce the rewriting time and the number of times of rewriting, and it is possible to simultaneously improve the high speed and the reliability. The present invention also allows multiple small files to be stored in one block. For example, two files having a data amount of 4 pages may be stored. In this way, although the rewriting time is slightly increased, the memory area can be used effectively.

Thirdly, since only one type of file is stored in one block, when rewriting a file, it is not necessary to save unrewritten data in the buffer memory, and the rewriting time can be shortened.

Fourthly, it is assumed that the size of a file managed to store only one type of file in one block of the present invention is larger than the block size. In this case, the number of blocks used to store one file is N = [(data amount / block size) +1]
No more than N. That is, when the amount of data is exactly a positive multiple of the block size, the number of blocks used is N-1.
It is an individual. If it is not a positive multiple, N are used. By storing one type of file in the minimum necessary blocks in this way, the time required for file rewriting and the number of times of rewriting are minimized.

Fifth, the present invention is intended for the case where files are written continuously on physical addresses, for example.
In this case, if there is an open page in the block and the amount of data remaining after writing data for that page is not a positive multiple of the block size, the maximum number of blocks to use is N = [(data amount / block size ) +2]. By storing one type of file in the minimum necessary blocks in this way, the time required for file rewriting and the number of times of rewriting are minimized.

[0026]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a NAN according to the first embodiment of the present invention.
FIG. 6 is a block diagram showing a configuration of a nonvolatile semiconductor memory device using a D-type EEPROM. A memory cell array 1 as a memory means is provided with a sense amplifier / latch circuit 2 for performing data write, read, write and erase verify. The memory cell array 1 is
It is divided into blocks each consisting of a set of pages, which is a data writing area of a predetermined unit, and this block is configured as a minimum erase unit. The sense amplifier / latch circuit 2 is connected to the data input / output buffer 6 and receives the output of the column decoder 3 which receives the address signal from the address buffer 4 as an input. Further, a row decoder 5 for controlling the control gate and the select gate is provided for the memory cell array 1, and a substrate potential for controlling the potential of the p-type substrate (or p-type well) in which the memory cell array 1 is formed. A control circuit 7 is provided.
Further, a data detection circuit 9 as a data detection means is provided to receive an input from the data input / output buffer 6 and to provide an output to a verification end detection circuit 8 which also functions as a write mode end means.

FIG. 2 shows the internal structure of the data detection circuit 9. Basically, the logical sum of the outputs of the respective data input / output buffers 6 is input to the flip-flop circuit 10, which is reset at the beginning of the write mode and one page of data is sent from the outside. When data other than 1 "data is input, the set state is set and the output of the flip-flop circuit 10 becomes" L ". Normal data input is performed in synchronization with the WE pulse, and the data is latched in the rising state of the WE pulse. Therefore, the flip-flop circuit 10 is controlled by the ENB (“L” at activation) signal so as to be activated after the data is determined. If all the data for one page is "1", the output of the flip-flop circuit 10 is "H" and the signal END is "H".
Becomes If you have entered the data for one page, press E
If the ND signal is "H", it is considered that all the data is "1" and the END signal is input to the verify end detection circuit 8 to end the write mode.
If the END signal is "L", it is considered that there is "0" data, and the write and verify operations are continued.

FIG. 3 shows a general flow chart of the write operation. First, the write mode is set (step 101), and then the write data is set (step 102). The next write data is all
It is determined whether or not it is "1" (step 103), and N
If O, write operation is performed (step 104), and Y
If SE, the write operation is not performed and the process ends.

Next, the operation including writing and verifying will be described with reference to the flowchart of FIG. This flowchart shows a NAND-type EEPROM that automatically performs writing and verification in the chip. First, the automatic write mode is set (step 201). Next, data for one page is set (step 202). After that, the operation is performed inside the chip (inside the broken line). Here, it is verified whether all the data are "1" (step 203). If NO, a write operation is performed (step 204), and then a verify operation is performed (step 205). If the verify is NG, rewrite data is automatically set and the writing is repeated again (steps 206 to 208). If the verify is OK, the automatic write mode is canceled (step 209),
It ends. For termination, specific data may be output to the data output section, or a READY / BUSY signal may be used. When all the data are "1", the automatic write mode is released and the process ends.

The verification of whether or not all the write data is "1" is not limited to the above embodiment. After inputting one page of data, the contents of the sense amplifier / latch circuit may be detected all at once, as in the write verify described in the conventional example. At this time, all data is "1"
In this case, a signal indicating the end of writing is obtained, which can save the time for applying VPP to the control gate. Further, although the above-mentioned embodiment has explained the page writing of the NAND type EEPROM, it is also effective for the EEPROM which performs writing in byte units. If all 1-byte data is "1" (meaning that the erased state is maintained, definition of "1" and "0" is optional), write or verify operation ends It is also possible to omit unnecessary operations as the state.
In this case, it is possible to shift to the write or verify end state simply by ORing the outputs of the input / output buffers.

Next, FIG. 5 shows a second embodiment of the present invention. This drawing is a block diagram showing the configuration of the nonvolatile semiconductor memory device in this embodiment. This device comprises a memory unit 11 as a memory unit, a control unit 12 serving as a management unit for the memory unit, and an interface unit 13 with a host system 14. The memory unit 11 has a NAND-type EEPROM divided into blocks including a plurality of pages.
Memory cell array.

Next, an example of storing a file in the memory unit 11 under the control of the control unit 12 in the nonvolatile semiconductor memory device configured as described above will be described.

FIG. 6 shows a first memory map example on the memory section 11. In this example, 3 files are stored for 3 NAND blocks, and 1 NAN is stored.
It is controlled so that only one type of file exists in the D block. In this case, to rewrite file 1, NAN
After erasing D block 1, new data is written in order from the most source side page.

FIG. 7 shows a second memory map example on the memory section 11. In this example, one NAND block is controlled to store a plurality of files each having a size equal to or smaller than the block size. In this case, to rewrite file 1, file 2 existing in the same NAND block
Are saved in the buffer memory and then the NAND block 1
Is erased, the data saved in the buffer memory is read and rewritten, and then the file 1 is sequentially written.

FIG. 8 shows a third memory map example on the memory section 11. In this example, while maintaining the principle that only one file is stored in one NAND block, the number of NAND blocks used for storage is controlled to the minimum. In this case, 2 NAND blocks are the minimum required number of blocks for the file 1 having a data amount of 1.5 blocks. Of course NAND
Block 1 and NAND block 2 need not be physically contiguous block addresses.

FIG. 9 shows a fourth memory map example on the memory section 11. In this example, files 1 and 2 are continuously stored so that no empty area occurs in the NAND block. In this case, the data amount of 1.75 blocks is stored over 3 NAND blocks. Of course, the three NAND blocks do not have to be physically continuous block addresses.

As described above, the file is converted into the NAND type EE.
When the data is stored in the memory unit configured by the memory cell array of the PROM, the number of readings, the number of block erasing, and the rewriting necessary to save the data are controlled by controlling the data to be stored in as few NAND blocks as possible. The number of times of rewriting is reduced, and the rewriting time can be shortened and the number of times of rewriting can be reduced.

[0039]

As described above, according to the present invention,
Firstly, when all the write data to the data write area of a predetermined unit is data which should keep the erased state of the memory cell, for example, "1", unnecessary write operation can be omitted and the speed can be increased.

Secondly, since the file having the data amount equal to or smaller than the block size is stored in one block, the rewriting time can be shortened and the number of rewritings can be reduced to improve the speed and reliability. be able to.

Thirdly, since only one type of file is stored in one block, it is not necessary to save unrewritten data in the buffer memory at the time of rewriting the file, so the rewriting time is shortened. Higher speed is possible.

Fourth, when only one type of file is stored in one block, the number of blocks used for the storage is N = [(data amount / block size) +
1] Since the number of files is N or less, one type of file can be stored in the minimum necessary block, and the time required for file rewriting and the number of times of rewriting are minimized.
The reliability can be improved as well as the speedup.

Fifth, since the number of blocks used for storing one type of file is set to N = [(data amount / block size) +2] N or less when files are continuously written on physical addresses, One type of file can be stored in the minimum necessary blocks, and the same effect as the fourth aspect of the invention can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a nonvolatile semiconductor memory device according to the present invention.

FIG. 2 is a diagram showing an internal configuration of a data detection circuit in FIG.

FIG. 3 is a flow chart for explaining a write operation in the first embodiment.

FIG. 4 is a flowchart for explaining an operation including writing and verifying in the first embodiment.

FIG. 5 is a block diagram showing a second embodiment of the present invention.

FIG. 6 is a diagram showing a first memory map example on a memory unit in the second embodiment.

FIG. 7 is a diagram showing a second memory map example on the memory unit in the second embodiment.

FIG. 8 is a diagram showing a third memory map example on the memory unit in the second embodiment.

FIG. 9 is a diagram showing a fourth memory map example on the memory unit in the second embodiment.

FIG. 10 is a circuit diagram showing a sense amplifier / latch circuit in a conventional nonvolatile semiconductor memory device.

FIG. 11 is a flowchart for explaining a write operation according to a conventional example.

FIG. 12 is a diagram showing a memory map on a memory unit in a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 memory cell array (memory means) 8 verify end detection circuit having the function of write mode end means 9 data detection circuit (data detection means) 11 memory section (memory means) 12 control section (management means)

Continuation of front page (51) Int.Cl. ⁵ Identification number Internal reference number FI Technical indication location H01L 29/792 H01L 29/78 371 (72) Inventor Hiroshi Nakamura 1 Komukai Toshiba-cho, Kawasaki-shi, Kanagawa Prefecture 1 Share Incorporated Toshiba Research Institute (72) Inventor Hideko Ohira 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Incorporated Toshiba Research Institute

Claims (5)

[Claims] 1. A memory means having a data writing area of a predetermined unit composed of a plurality of memory cells, and detecting whether or not all the write data of the predetermined unit is data for maintaining an erased state of the memory cell. And a write mode terminating means for terminating the write mode when it is detected by the data detecting means that all the write data of the predetermined unit is data for maintaining the erased state of the memory cell. A characteristic non-volatile semiconductor memory device. 2. A memory means having a memory cell array divided into a plurality of blocks, and a managing means for managing a file having a data amount equal to or smaller than a block size to be stored in one block. A characteristic non-volatile semiconductor memory device. 3. A nonvolatile memory comprising a memory means having a memory cell array divided into a plurality of blocks, and a management means for managing so that only one type of file is stored in one block. Semiconductor memory device. 4. The number of the blocks used to store the one type of file is N = [(data amount / block size) +1] (however, the number inside the parentheses is an integer rounded down to the nearest whole number). 4. The nonvolatile semiconductor memory device according to claim 3, wherein: 5. A memory means having a memory cell array divided into a plurality of blocks, and the number of the blocks used for storing one type of file is N = [(data amount /
Block size) +2] (however, the number inside () is an integer rounded down to the nearest whole number), and the management means for managing the number to be N or less.