JPH05282075A - Microcomputer - Google Patents

Abstract

PURPOSE:To reduce the power consumption of the whole microcomputer which has a dynamic logic circuit internally by reducing the power consumption of the dynamic logic circuit. CONSTITUTION:An ALU decoder 80 consists of the dynamic logic circuit and decodes the output of a latch circuit 60 to control an ALU 90. Further, the ALU decoder 80 performs precharging and sampling according to a timing signal and a clock signal which are inputted through latch signal lines 52 and 56 and become active when an instruction being executed requires arithmetic operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer, and more particularly to a microcomputer incorporating a dynamic logic circuit.

[0002]

2. Description of the Related Art As a conventional microcomputer,
There is a microcomputer provided with an ALU decoder as a unit for controlling an ALU that performs arithmetic logic operations.
When the instruction to be executed requires an arithmetic operation, the ALU decoder decodes the μ program of the instruction and controls the ALU. The logic of the ALU decoder is often complicated because it corresponds to various operations.
It is often designed with a dynamic logic circuit such as LA.

[0003]

However, in the above-described conventional microcomputer, the built-in ALU decoder repeats the precharge / sampling even when the instruction being executed does not require an operation. There is a problem that the power consumption of the entire microcomputer increases more than necessary due to the power consumption.

The present invention has been made in view of the above problems, and in a microcomputer incorporating a dynamic logic circuit, it is possible to reduce the power consumption in the dynamic logic circuit and to reduce the power consumption in the entire microcomputer. It is an object to provide a microcomputer that can reduce power consumption.

[0005]

A microcomputer according to the present invention is a microcomputer having a dynamic logic circuit that functions by performing a precharge operation and a discharge operation, and the output data of the dynamic logic circuit is required. And a means for generating a predetermined signal when the above-mentioned is set, and a means for prohibiting the precharge operation of the dynamic logic circuit by the predetermined signal.

[0006]

In the microcomputer according to the present invention, in the microcomputer incorporating the dynamic logic circuit, the dynamic logic circuit includes means for generating a predetermined signal when output data is required, and the predetermined signal. Is controlled by the means for inhibiting the precharge operation of the dynamic logic circuit, and the μ program is decoded and the ALU is controlled only when the instruction to be executed requires an operation. Therefore, the dynamic logic circuit precharges / samps only when the instruction being executed requires an operation, so that the power consumption in the dynamic logic circuit can be reduced, and as a result, the entire microcomputer can be reduced. Power consumption can be reduced.

[0007]

Embodiments of the present invention will now be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an instruction executing section in a microcomputer according to a first embodiment of the present invention.

As shown in FIG. 1, the instruction execution unit 1 has a register group 70 required for instruction execution and an AL for performing arithmetic logic operation.
U90, micro program ROM (hereinafter referred to as μROM) 20, PSW 65, and instruction code to μROM
A μ address generation unit 10 for generating 20 addresses,
A μ code output section 30 for latching the output of the ROM 20, and
Decoder 40 for decoding the output of the μ code output unit 30
A latch circuit 45 for latching a part of the output of the decoder 40, AND circuits 50 and 55, and a μ code output unit 3
A latch circuit 60 for latching the output of 0, and a latch circuit 6
An ALU that controls the ALU 90 by decoding the output of 0
It is composed of a decoder 80.

The μ code output section 30, the latch circuit 60, and the decoder 40 are the μ code bus 32, and the decoder 40,
The AND circuit 50 and the latch circuit 45 use the decode signal line 4
1, the AND circuit 50, the latch circuit 60 and the ALU decoder 80 are connected to the latch signal line 52 and the AND circuit 55 and the ALU decoder 80 are connected.
The LU decoders 80 are connected by the latch signal lines 56, respectively.

Next, the operation of the instruction executing section 1 in the microcomputer according to the first embodiment constructed as described above will be described. The μ address generation unit 10 inputs an instruction code via the instruction code bus 11 and generates a μ address of an instruction to be executed based on the instruction code. The μROM 20 outputs μcode data for the μaddress generated by the μaddress generation unit 10 to the μcode output unit 3
Output to 0. The μ code output unit 30 latches the μ code data at a timing based on the signal on the first clock signal line 31, and outputs the μ code data to the μ code bus 32. The μ code data output to the μ code bus 32 is divided into two fields, one of which is a field for controlling the data bus. The other is ALU such as arithmetic instruction
Branch control such as arithmetic control or conditional branch instruction for branching according to internal state of PSW65, or PSW65
Is a field of internal control for prohibiting the operation of the above and interruption acceptance, and the decoder 40 activates the decode signal line 41 when the code of the ALU operation control is output in this field. The AND circuit 50 is
A signal on the decode signal line 41 for controlling the ALU operation and the like and a signal on the second clock signal line 51 are ANDed and the result is output to the latch signal line 52. The latch circuit 60 is
The ALU operation control code on the μ code bus 32 is latched at the timing of the signal on the latch signal line 52. here,
The AND circuit 55 performs a logical product of the output of the latch circuit 45 and the signal on the first clock signal line 31, and outputs the result to the latch signal line 56. Then, the ALU decoder 80
Is designed by PLA which is a dynamic logic circuit, pre-charges the inside with the signal on the latch signal line 52, latches the decoding result based on the signal on the latch signal line 56, and outputs it to the ALU 90.

The ALU 90 performs various arithmetic operations based on the decoding result output by the ALU decoder 80.

As described above, in the instruction execution unit 1 of the microcomputer according to the first embodiment, the ALU decoder 80 composed of the dynamic type logic circuit is used.
Since the ALU 90 performs precharge / sampling only when the ALU 90 performs an operation, the power consumption can be reduced.

Next, a microcomputer according to the second embodiment of the present invention will be described. FIG. 2 shows an instruction execution unit 2 in the microcomputer according to the second embodiment.
It is a block diagram showing. 2, the same components as those of the instruction execution unit 1 in the microcomputer according to the first embodiment shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

In the instruction execution unit 2 in the microcomputer according to the second embodiment shown in FIG. 2, the components different from the instruction execution unit 1 in the microcomputer according to the first embodiment shown in FIG. This is a portion in which a latch signal line 42 is added instead of the decode signal line 41. The μ-code output unit 30 puts A on the μ-code bus 32.
A signal that becomes active when the LU operation control code is output is output to the latch signal line 42. The signal on the latch signal line 42 is input to the AND circuit 50 and the latch circuit 45, and functions equivalent to the signal on the decode signal line 41 shown in FIG. The points other than the above are the same as those in the first embodiment.

[0016]

As described above, according to the microcomputer of the present invention, in a microcomputer incorporating a dynamic logic circuit, the dynamic logic incorporated therein is provided only when an instruction being executed requires an operation. Since the circuit performs precharging / sampling, it is possible to reduce the power consumption in the dynamic logic circuit, thereby reducing the power consumption in the entire microcomputer.

[Brief description of drawings]

FIG. 1 is a block diagram showing an instruction execution unit in a microcomputer according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing an instruction execution unit in a microcomputer according to a second embodiment of the present invention.

[Explanation of symbols]

 1; instruction execution unit 10; μ address generation unit 20; μROM 30; μ code output unit 40; decoders 45, 60; latch circuits 50, 55; AND circuit 80; ALU decoder 90; ALU

Claims (1)

[Claims] 1. A microcomputer having a dynamic logic circuit which functions by performing a precharge operation and a discharge operation, and means for generating a predetermined signal when output data of the dynamic logic circuit is required. A means for inhibiting the precharge operation of the dynamic logic circuit by the predetermined signal.